aboutsummaryrefslogtreecommitdiff
path: root/drivers/gpu/drm/amd/amdgpu
AgeCommit message (Collapse)AuthorFilesLines
2020-07-10drm/amdgpu/gfx10: fix race condition for kiqJack Xiao1-1/+8
During preemption test for gfx10, it uses kiq to trigger gfx preemption, which would result in race condition with flushing TLB for kiq. Signed-off-by: Jack Xiao <[email protected]> Reviewed-by: Hawking Zhang <[email protected]> Acked-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-07-10drm/amdgpu: minor cleanup of phase1 suspend codeNirmoy Das1-10/+13
Cleanup of phase1 suspend code to reduce unnecessary indentation. Signed-off-by: Nirmoy Das <[email protected]> Acked-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-07-10drm/amd/powerplay: revise calling chain on retrieving frequency rangeEvan Quan2-5/+3
This helps to maintain clear code layers and drop unnecessary parameter. Signed-off-by: Evan Quan <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-07-10drm/amd/powerplay: revise calling chain on setting soft limitEvan Quan1-1/+3
This helps to maintain clear code layers and drop unnecessary parameter. Signed-off-by: Evan Quan <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-07-10drm/amdgpu: enable gpu recovery for sienna cichlidLikun Gao1-0/+1
Enable gpu recovery for sienna cichlid by default to trigger gpu recovery once needed. Signed-off-by: Likun Gao <[email protected]> Reviewed-by: Hawking Zhang <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-07-10drm/amdgpu: remove unnecessary logic of ASIC checkLikun Gao3-15/+2
Remove some unused ASIC check logic. Remove some definition of amdgpu_device which only used by the removed ASIC check logic.(V2) Signed-off-by: Likun Gao <[email protected]> Reviewed-by: Hawking Zhang <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-07-10drm/amdgpu: don't do soft recovery if gpu_recovery=0Marek Olšák1-1/+2
It's impossible to debug shader hangs with soft recovery. Signed-off-by: Marek Olšák <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Reviewed-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-07-09drm/amdgpu: don't do soft recovery if gpu_recovery=0Marek Olšák1-1/+2
It's impossible to debug shader hangs with soft recovery. Signed-off-by: Marek Olšák <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Reviewed-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]> Cc: [email protected]
2020-07-09drm/amdgpu: add TMR destory function for pspHuang Rui1-4/+53
TMR is required to be destoried with GFX_CMD_ID_DESTROY_TMR while the system goes to suspend. Otherwise, PSP may return the failure state (0xFFFF007) on Gfx-2-PSP command GFX_CMD_ID_SETUP_TMR after do multiple times suspend/resume. Signed-off-by: Huang Rui <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]> Cc: [email protected]
2020-07-09drm/amdgpu: asd function needs to be unloaded in suspend phaseHuang Rui1-0/+6
Unload ASD function in suspend phase. Signed-off-by: Huang Rui <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]> Cc: [email protected]
2020-07-08gpu/drm: Remove debug info about CPU addressTiezhu Yang1-3/+2
When I update the latest kernel, I see the following "____ptrval____" boot messages. [ 1.872600] radeon 0000:01:05.0: fence driver on ring 0 use gpu addr 0x0000000048000c00 and cpu addr 0x(____ptrval____) [ 1.879095] radeon 0000:01:05.0: fence driver on ring 5 use gpu addr 0x0000000040056038 and cpu addr 0x(____ptrval____) Both radeon_fence_driver_start_ring() and amdgpu_fence_driver_start_ring() have the similar issue, there exists the following two methods to solve it: (1) Use "%pK" instead of "%p" so that the CPU address can be printed when the kptr_restrict sysctl is set to 1. (2) Just completely drop the CPU address suggested by Christian, because the CPU address was useful in the past, but isn't any more. We now have a debugfs file to read the current fence values. Since the CPU address is not much useful, just remove the debug info about CPU address. Reviewed-by: Christian König <[email protected]> Signed-off-by: Tiezhu Yang <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-07-08drm/amdgpu: use register distance member instead of hardcode in mmhub v9.4Huang Rui1-16/+21
This patch updates to use register distance member instead of hardcode in mmhub v9.4. Signed-off-by: Huang Rui <[email protected]> Tested-by: AnZhong Huang <[email protected]> Reviewed-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-07-08drm/amdgpu: use register distance member instead of hardcode in mmhub v2Huang Rui1-15/+24
This patch updates to use register distance member instead of hardcode in mmhub v2. Signed-off-by: Huang Rui <[email protected]> Tested-by: AnZhong Huang <[email protected]> Reviewed-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-07-08drm/amdgpu: use register distance member instead of hardcode in mmhub v1Huang Rui1-15/+24
This patch updates to use register distance member instead of hardcode in mmhub v1. Signed-off-by: Huang Rui <[email protected]> Tested-by: AnZhong Huang <[email protected]> Reviewed-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-07-08drm/amdgpu: use register distance member instead of hardcode in gfxhub v2.1Huang Rui1-15/+24
This patch updates to use register distance member instead of hardcode in gfxhub v2.1. Signed-off-by: Huang Rui <[email protected]> Tested-by: AnZhong Huang <[email protected]> Reviewed-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-07-08drm/amdgpu: use register distance member instead of hardcode in gfxhub v2Huang Rui1-15/+24
This patch updates to use register distance member instead of hardcode in gfxhub v2. Signed-off-by: Huang Rui <[email protected]> Tested-by: AnZhong Huang <[email protected]> Reviewed-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-07-08drm/amdgpu: use register distance member instead of hardcode in gfxhub v1Huang Rui1-16/+25
This patch updates to use register distance member instead of hardcode in gfxhub v1. Signed-off-by: Huang Rui <[email protected]> Tested-by: AnZhong Huang <[email protected]> Reviewed-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-07-08drm/amdgpu: use register distance member instead of hardcode in VCN2/JEPG2Huang Rui2-3/+4
This patch updates to use register distance member instead of hardcode in VCN2/JEPG2. They are for the same ASIC. Signed-off-by: Huang Rui <[email protected]> Tested-by: AnZhong Huang <[email protected]> Reviewed-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-07-08drm/amdgpu: use register distance member instead of hardcode in UVD7/VCE4Huang Rui2-3/+5
This patch updates to use register distance member instead of hardcode in UVD7/VCE4. They are for the same ASIC. Signed-off-by: Huang Rui <[email protected]> Tested-by: AnZhong Huang <[email protected]> Reviewed-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-07-08drm/amdgpu: use register distance member instead of hardcode in VCN1/JEPG1Huang Rui2-3/+4
This patch updates to use register distance member instead of hardcode in VCN1/JEPG1. They are for the same ASIC. Signed-off-by: Huang Rui <[email protected]> Tested-by: AnZhong Huang <[email protected]> Reviewed-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-07-08drm/amdgpu: use register distance member instead of hardcode in GMC10Huang Rui1-17/+26
This patch updates to use register distance member instead of hardcode in GMC10. Signed-off-by: Huang Rui <[email protected]> Tested-by: AnZhong Huang <[email protected]> Reviewed-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-07-08drm/amdgpu: use register distance member instead of hardcode in GMC9Huang Rui1-14/+25
This patch updates to use register distance member instead of hardcode in GMC9. Signed-off-by: Huang Rui <[email protected]> Tested-by: AnZhong Huang <[email protected]> Reviewed-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-07-08drm/amdgpu: add register distance members into vmhub structureHuang Rui7-0/+54
This patch is to abstract register distances between two continuous context domains and invalidation engines. In different ip headers, these distances may be differences. Signed-off-by: Huang Rui <[email protected]> Tested-by: AnZhong Huang <[email protected]> Reviewed-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-07-08drm/amdgpu: Move the mutex lock/unlock outAlex Jivin1-8/+4
Move the mutext lock/unlock outside of the if(), as the mutex is always taken: either in the if() branch or in the else branch. Signed-off-by: Alex Jivin <[email protected]> Suggested-By: Luben Tukov <[email protected]> Reviewed-by: Luben Tuikov <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-07-08drm/amdgpu: fix coding error of mmhub pg enablementLikun Gao1-3/+3
MMHUB powergating should be disabled on navi12 and enabled on sienna cichlid. Signed-off-by: Likun Gao <[email protected]> Reviewed-by: Hawking Zhang <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-07-08drm/amdgpu: use RREG32_KIQ to read register when get cg stateLikun Gao2-6/+6
Use RREG32_KIQ to read gfx register when try to get gfx/sdma clockgating state instead of RREG32, as it will result to system hard hang when GPU is enter into GFXOFF state. Signed-off-by: Likun Gao <[email protected]> Reviewed-by: Hawking Zhang <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-07-08drm/amdgpu: updated ta ucode loadingJohn Clements2-0/+101
add support for loading ucode with ta_firmware_header_v2_0 Reviewed-by: Bhawanpreet Lakha <[email protected]> Signed-off-by: John Clements <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-07-08drm/amdgpu: updated ta ucode headerJohn Clements1-0/+26
added definition for ta_firmware_header_v2_0 Reviewed-by: Bhawanpreet Lakha <[email protected]> Signed-off-by: John Clements <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-07-08drm/amdgpu: add TMR destory function for pspHuang Rui1-4/+53
TMR is required to be destoried with GFX_CMD_ID_DESTROY_TMR while the system goes to suspend. Otherwise, PSP may return the failure state (0xFFFF007) on Gfx-2-PSP command GFX_CMD_ID_SETUP_TMR after do multiple times suspend/resume. Signed-off-by: Huang Rui <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-07-08drm/amdgpu: asd function needs to be unloaded in suspend phaseHuang Rui1-0/+6
Unload ASD function in suspend phase. Signed-off-by: Huang Rui <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-07-02drm/amdgpu: use %u rather than %d for sclk/mclkAlex Deucher1-2/+2
Large clock values may overflow and show up as negative. Reported by prOMiNd on IRC. Acked-by: Nirmoy Das <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-07-02drm/amdgpu/atomfirmware: update vram info handling for renoirAlex Deucher1-1/+10
Add support for integrated_system_info table v12. Use the actual v12 structure. Acked-by: Evan Quan <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-07-02drm/amdgpu/atomfirmware: fix vram_info fetching for renoirAlex Deucher1-0/+1
Renoir uses integrated_system_info table v12. The table has the same layout as v11 with respect to this data. Just reuse the existing code for v12 for stable. Fixes incorrectly reported vram info in the driver output. Acked-by: Evan Quan <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-07-02Revert "drm/amdgpu: support access regs outside of mmio bar"Hawking Zhang3-29/+39
This reverts commit 2eee0229f65e897134566888e5321bcb3af0df7a. Fallback to a stable base until we have a correct new one Signed-off-by:Hawking Zhang <[email protected]> Reviewed-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-07-02drm/amdgpu: make IB test synchronize with init for SRIOV(v2)Monk Liu1-0/+3
issue: originally we kickoff IB test asynchronously with driver's init, thus the IB test may still running when the driver loading done (modprobe amdgpu done). if we shutdown VM immediately after amdgpu driver loaded then GPU may hang because the IB test is still running fix: flush the delayed_init routine at the bottom of device_init to avoid driver loading done prior to the IB test completes Signed-off-by: Monk Liu <[email protected]> Acked-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-07-02drm/amdgpu: correct discovery_tmr_size init valWenhui Sheng1-1/+1
The legacy way to initialize discovery_tmr_size is using DISCOVERY_TMR_SIZE, while after we reduce DISCOVERY_TMR_SIZE from 64KB to 4KB, variable discovery_tmr_size is also reduced to 4KB, this is not correct, it still should be 64KB, discovery_tmr_size will be used to calculate ip_discovery reserved mem's start address and size. Using DISCOVERY_TMR_OFFSET to init discovery_tmr_size instead. Signed-off-by: Wenhui Sheng <[email protected]> Reviewed-by: Hawking Zhang <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-07-02drm/amdgpu: reduce ip discovery data reading sizeWenhui Sheng2-2/+3
Only read first 4K data instead of whole TMR block, so we can reduce the time in full access mode. Signed-off-by: Wenhui Sheng <[email protected]> Reviewed-by: Hawking Zhang <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-07-02drm/amdgpu: merge atombios init blockWenhui Sheng1-22/+1
After we move request full access before set ip blocks, we can merge atombios init block of SRIOV and baremetal together. Signed-off-by: Wenhui Sheng <[email protected]> Reviewed-by: Hawking Zhang <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-07-02drm/amdgpu: invoke req full access early enoughWenhui Sheng1-31/+23
From SIENNA_CICHLID, HW introduce a new protection feature which can control the FB, doorbell and MMIO write access for VF, so guest driver should request full access before ip discovery, or we couldn't access ip discovery data in FB. Signed-off-by: Wenhui Sheng <[email protected]> Reviewed-by: Hawking Zhang <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-07-02drm/amdgpu: move reg base init forward for soc15Wenhui Sheng1-7/+22
Init soc15 reg base early enough so we can touch mailbox related registers in request full access for sriov before set_ip_blocks, vi&nv arch doesn't use reg base in virt ops. v2: fix reg_base_init missed in bare metal case. Signed-off-by: Wenhui Sheng <[email protected]> Reviewed-by: Hawking Zhang <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-07-02drm/amdgpu: request init data in virt detectionWenhui Sheng7-12/+46
Move request init data to virt detection func, so we can insert request full access between request init data and set ip blocks. Signed-off-by: Wenhui Sheng <[email protected]> Reviewed-by: Hawking Zhang <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-07-02drm/amdgpu: Let KFD use more VMIDs on ArcturusFelix Kuehling1-3/+8
When there is no graphics support, KFD can use more of the VMIDs. Graphics VMIDs are only used for video decoding/encoding and post processing. With two VCE engines, there is no reason to reserve more than 2 VMIDs for that. Signed-off-by: Felix Kuehling <[email protected]> Reviewed-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-07-02drm/amdgpu: Clean up KFD VMID assignmentFelix Kuehling16-43/+22
The KFD VMID assignment was hard-coded in a few places. Consolidate that in a single variable adev->vm_manager.first_kfd_vmid. The value is still assigned in gmc-ip-version-specific code. Signed-off-by: Felix Kuehling <[email protected]> Reviewed-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-07-02drm/amdgpu: SI support for UVD and VCE power managmentAlex Jivin2-18/+68
Port functionality from the Radeon driver to support UVD and VCE power management. Signed-off-by: Alex Jivin <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Acked-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-07-02drm/amdgpu: SI support for VCE clock controlAlex Jivin3-1/+167
Port functionality from the Radeon driver to support VCE clock control. Signed-off-by: Alex Jivin <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Acked-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-07-02drm/amdgpu: SI support for UVD clock controlAlex Jivin2-6/+229
Port functionality from the Radeon driver to support UVD clock control. Signed-off-by: Alex Jivin <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Acked-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-07-02Merge tag 'amd-drm-next-5.9-2020-07-01' of ↵Dave Airlie95-942/+9832
git://people.freedesktop.org/~agd5f/linux into drm-next amd-drm-next-5.9-2020-07-01: amdgpu: - DC DMUB updates - HDCP fixes - Thermal interrupt fixes - Add initial support for Sienna Cichlid GPU - Add support for unique id on Arcturus - Major swSMU code cleanup - Skip BAR resizing if the bios already did id - Fixes for DCN bandwidth calculations - Runtime PM reference count fixes - Add initial UVD support for SI - Add support for ASSR on eDP links - Lots of misc fixes and cleanups - Enable runtime PM on vega10 boards that support BACO - RAS fixes - SR-IOV fixes - Use IP discovery table on renoir - DC stream synchronization fixes amdkfd: - Track SDMA usage per process - Fix GCC10 compiler warnings - Locking fix radeon: - Default to on chip GART for AGP boards on all arches - Runtime PM reference count fixes UAPI: - Update comments to clarify MTYPE From: Alex Deucher <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected] Signed-off-by: Dave Airlie <[email protected]>
2020-07-01drm/amdgpu: use %u rather than %d for sclk/mclkAlex Deucher1-2/+2
Large clock values may overflow and show up as negative. Reported by prOMiNd on IRC. Acked-by: Nirmoy Das <[email protected]> Signed-off-by: Alex Deucher <[email protected]> Cc: [email protected]
2020-07-01drm/amdgpu/atomfirmware: fix vram_info fetching for renoirAlex Deucher1-0/+1
Renoir uses integrated_system_info table v12. The table has the same layout as v11 with respect to this data. Just reuse the existing code for v12 for stable. Fixes incorrectly reported vram info in the driver output. Acked-by: Evan Quan <[email protected]> Signed-off-by: Alex Deucher <[email protected]> Cc: [email protected]
2020-07-01drm/amdgpu: enable runtime pm on vega10 when noretry=0Alex Deucher1-1/+5
The failures with ROCm only happen with noretry=1, so enable runtime pm when noretry=0 (the current default). Reviewed-by: Felix Kuehling <[email protected]> Acked-by: Rajneesh Bhardwaj <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
Powered by cgit, Gruvboxed by Blaster4385.