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path: root/drivers/gpu/drm/amd/amdgpu
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2019-06-21drm/amdgpu/psp: convert ucode id to psp ucode idJack Xiao1-0/+6
Convert ucode id to the corresponding psp ucode id. Signed-off-by: Jack Xiao <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-06-21drm/amdgpu: add corresponding vcn ram ucode idJack Xiao1-0/+2
Add VCN RAM ucode id in corresponding to psp ucode id. Signed-off-by: Jack Xiao <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-06-21drm/amdgpu/psp: add new VCN RAM ucode id to pspJack Xiao1-0/+2
PSP supports to program vcn sram by ucode loading interface. Signed-off-by: Jack Xiao <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-06-21drm/amdgpu: enable VCN2.0 DPG modeLeo Liu1-1/+2
It will be the default for VCN2.x family Signed-off-by: Leo Liu <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Reviewed-by: James Zhu <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-06-21drm/amdgpu/VCN2.0: add DPG pause modeLeo Liu1-0/+70
Pause the DPG when not doing decode Signed-off-by: Leo Liu <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-06-21drm/amdgpu/VCN2.0: add DPG mode start and stop (v2)Leo Liu1-3/+296
This is for using SRAM directly v2: rebase (Alex) Signed-off-by: Leo Liu <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Reviewed-by: James Zhu <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-06-21drm/amdgpu/VCN2.0: add direct SRAM read and writeLeo Liu1-0/+48
This will be the basic and used for DPG mode Signed-off-by: Leo Liu <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Reviewed-by: James Zhu <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-06-21drm/amdgpu/VCN2.0 remove unused Macro and declarationLeo Liu1-2/+0
Just for cleanup Signed-off-by: Leo Liu <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Reviewed-by: James Zhu <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-06-21drm/amd/powerplay: fix deadlock issue for smu_force_performance_levelKevin Wang1-9/+0
the smu->mutex is internal lock resource in sw-smu, some functions will use it at the same time, so it maybe will cause deadlock issue. this patch fix this issue in smu_force_performance_level function. Signed-off-by: Kevin Wang <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-06-21drm/amd: the data retured from PRT is expected to be 0Jack Xiao2-1/+4
The dummy page for returning from PRT resides inside system memory, need set system flag bit in VM_L2_CNTL. Signed-off-by: Jack Xiao <[email protected]> Reviewed-by: Hawking Zhang <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-06-21drm/amdgpu/gfx10: update gfx golden settingstiancyin1-2/+4
add new registers: mmPA_SC_ENHANCE_1, mmTCP_CNTL, update registers: mmDB_DEBUG4, mmUTCL1_CTRL Reviewed-by: Xiaojie Yuan <[email protected]> Signed-off-by: tiancyin <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-06-21drm/amd/powerplay: remove smu callback funciton get_mclk(get_sclk)Kevin Wang1-6/+24
remove smu callback: get_mclk, get_sclk. because the function smu_get_dpm_freq_range has the same function. Signed-off-by: Kevin Wang <[email protected]> Reviewed-by: Evan Quan <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-06-21drm/amdgpu: correct reference clock value on navi10Tao Zhou1-1/+1
remove the divisor 4 Signed-off-by: Tao Zhou <[email protected]> Acked-by: Jack Xiao <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-06-21drm/amd/powerplay: add function force_clk_levels for navi10Kevin Wang1-8/+8
add sysfs interface of force_clk_levels sysfs for navi10. Signed-off-by: Kevin Wang <[email protected]> Reviewed-by: Huang Rui <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-06-21drm/amd/powerplay: add function print_clk_levels for navi10Kevin Wang1-12/+12
add sysfs interface of print_clk_levels sysfs for navi10. Signed-off-by: Kevin Wang <[email protected]> Reviewed-by: Huang Rui <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-06-21drm/amdgpu/gfx10: require to pin/unpin CSIB BO when suspend/resumeJack Xiao1-0/+38
CSIB BO is required to be pinned down to guarantee bo is always valid when resume, and to be unpinned it so that its content can be saved during suspend. Signed-off-by: Jack Xiao <[email protected]> Reviewed-by: Hawking Zhang <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-06-21drm/amdgpu/gfx10: remove unnecessary waiting on gfx inactiveJack Xiao1-30/+5
The following KIQ ring test could guarantee the previous unmap has been done. Signed-off-by: Jack Xiao <[email protected]> Reviewed-by: Hawking Zhang <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-06-21drm/amdgpu: RLC must be disabled after SMU when S3 on naviJack Xiao1-3/+1
SMU requires to interact with RLC when disable all features, so RLC shouldn't be disabled ahead of SMU. Signed-off-by: Jack Xiao <[email protected]> Reviewed-by: Hawking Zhang <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-06-21drm/amdgpu/VCN2.0: remove powergating for UVDW tileLeo Liu2-11/+8
No UVDW tile any more from VCN2.0, so mark out related fields. It fixes error: "[drm] Register(0) [mmUVD_PGFSM_STATUS] failed to reach value 0x002aaaaa != 0x00aaaaaa" Signed-off-by: Leo Liu <[email protected]> Acked-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-06-21drm/amdgpu/gfx10: fix unbalanced MAP/UNMAP_QUEUES when async_gfx_ring is ↵Xiaojie Yuan1-3/+7
disabled gfx_v10_0_kiq_enable_kgq() is called only when async_gfx_ring is enabled, so should gfx_v10_0_kiq_disable_kgq(). Signed-off-by: Xiaojie Yuan <[email protected]> Acked-by: Alex Deucher <[email protected]> Reviewed-by: Jack Xiao <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-06-21drm/amdgpu/gfx10: drop redundant se/sh selectionXiaojie Yuan1-1/+0
we already selected se/sh at the beginning of the for loop Signed-off-by: Xiaojie Yuan <[email protected]> Reviewed-by: Jack Xiao <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-06-21drm/amdgpu/mes10.1: enable mes FW backdoor loadingJack Xiao1-0/+36
It enables MES FW backdoor loading in ip block functions. Signed-off-by: Jack Xiao <[email protected]> Reviewed-by: Hawking Zhang <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-06-21drm/amdgpu/mes10.1: implement mes enablement functionJack Xiao1-0/+33
After MES firmware gets loaded, it enables MES engine starting execution. Signed-off-by: Jack Xiao <[email protected]> Reviewed-by: Hawking Zhang <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-06-21drm/amdgpu/mes10.1: implement MES firmware backdoor loadingJack Xiao1-0/+67
It implements MES firmware backdoor loading. Signed-off-by: Jack Xiao <[email protected]> Reviewed-by: Hawking Zhang <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-06-21drm/amdgpu/mes10.1: implement ucode buffers destructionJack Xiao1-0/+11
Free ucode GPU buffers. Signed-off-by: Jack Xiao <[email protected]> Reviewed-by: Hawking Zhang <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-06-21drm/amdgpu/mes10.1: upload mes data ucode to gpu bufferJack Xiao1-0/+32
Allocate GPU buffer and upload mes data ucode to the buffer. Signed-off-by: Jack Xiao <[email protected]> Reviewed-by: Hawking Zhang <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-06-21drm/amdgpu/mes10.1: upload mes ucode to gpu bufferJack Xiao1-0/+34
Allocate GPU buffer and upload ucode firmware to the buffer. Signed-off-by: Jack Xiao <[email protected]> Reviewed-by: Hawking Zhang <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-06-21drm/amdgpu/mes10.1: implement ucode CPU buffer destructionJack Xiao1-0/+6
It implements the CPU buffer destruction of ucode. Signed-off-by: Jack Xiao <[email protected]> Reviewed-by: Hawking Zhang <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-06-21drm/amdgpu/mes10.1: load mes firmware file to CPU bufferJack Xiao1-0/+43
It requests MES firmware binary and uploads to CPU buffer. Signed-off-by: Jack Xiao <[email protected]> Reviewed-by: Hawking Zhang <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-06-21drm/amdgpu/mes10.1: add mes firmware info fieldsJack Xiao1-0/+16
The newly added fields is to store mes firmware related information. Signed-off-by: Jack Xiao <[email protected]> Reviewed-by: Hawking Zhang <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-06-21drm/amdgpu/ucode: add mes firmware file supportJack Xiao1-0/+15
The newly added firmware struct is for mes firmware file. Signed-off-by: Jack Xiao <[email protected]> Reviewed-by: Hawking Zhang <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-06-21drm/amdgpu/ucode: add the definitions of MES ucode and ucode dataJack Xiao1-0/+2
MES requires two seperate firmwares: ucode and ucode data. Signed-off-by: Jack Xiao <[email protected]> Reviewed-by: Hawking Zhang <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-06-21drm/amdgpu/sdma5: incorrect variable type for gpu addressJack Xiao1-1/+2
Incorrect programming with 64bit gpu address assignment for 32bit variable. Signed-off-by: Jack Xiao <[email protected]> Reviewed-by: Xiaojie Yuan <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-06-21drm/amdgpu/sdma5: fix a sdma potential hang in VK_Examples testtiancyin1-1/+2
[why] When page fault happens, it could lead to sdma hang is RESP_MODE = 0 for non-PRT case. [how] Setting SDMAx_UTCL1_CNTL.RESP_MODE to 0b011 to avoid SDMA halt. Reviewed-by: Jack Xiao <[email protected]> Signed-off-by: tiancyin <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-06-21drm/amdgpu/nv: set vcn pg flagJack Xiao1-1/+1
Enable VCN power gating by default. Signed-off-by: Jack Xiao <[email protected]> Reviewed-by: Huang Rui <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-06-21drm/amdgpu: enable vcn dpm scheme for naviJack Xiao1-2/+2
On navi1x, vcn dpm scheme was merged into powergating scheme. Signed-off-by: Jack Xiao <[email protected]> Acked-by: Alex Deucher <[email protected]> Reviewed-by: Huang Rui <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-06-21drm/amdgpu/vcn2: don't access register when power gatedJack Xiao1-1/+2
It will cause bus hang to access register UVD_STATUS when VCN is in the state of power gated. Signed-off-by: Jack Xiao <[email protected]> Acked-by: Alex Deucher <[email protected]> Reviewed-by: Huang Rui <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-06-21drm/amdgpu/vcn2: notify SMU power up/down VCNJack Xiao1-0/+7
For sw control power gating, it needs notify SMU to power up/down VCN when enter/exit working state. Signed-off-by: Jack Xiao <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Reviewed-by: Huang Rui <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-06-21drm/amdgpu/gfx10: fix issues for suspend/resumeJack Xiao1-5/+30
1). use PREEMPT_QUEUE instead of RESET_QUEUE for gfx ring disablement. 2). Need wait for unmapping queue done before continue execution. Signed-off-by: Jack Xiao <[email protected]> Reviewed-by: Tianci Yin <[email protected]> Reviewed-by: Xiaojie Yuan <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-06-21drm/amd/powerplay: set dpm_enabled flag but don't enable vcn dpmHuang Rui1-2/+2
This patch sets dpm_enabled flag but don't enable vcn dpm, because vcn dpm doesn't work so far and we needs to enable the sysfs interfaces. Signed-off-by: Huang Rui <[email protected]> Acked-by: Hawking Zhang <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-06-21drm/amdgpu/gfx10: fix resume failure when enabling async gfx ringXiaojie Yuan1-12/+14
'adev->in_suspend' code path is missing in gfx_v10_0_gfx_init_queue() Signed-off-by: Xiaojie Yuan <[email protected]> Reviewed-by: Hawking Zhang <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-06-21drm/amdgpu: disable some gfx light sleepTianci Yin1-4/+0
temporarily disable to avoid s3 test failure. s3 test failure log: "[drm:amdgpu_job_timedout [amdgpu]] *ERROR* ring sdma0 timeout, signaled seq=8278, emitted seq=8281" Reviewed-by: Jack Xiao <[email protected]> Signed-off-by: Tianci Yin <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-06-21drm/amdgpu/gfx10: update gfx golden settingsTianci Yin1-0/+3
add new registers: mmCGTT_SPI_CLK_CTRL, mmDB_DEBUG3 and mmGL2C_CGTT_SCLK_CTRL. Reviewed-by: Jack Xiao <[email protected]> Signed-off-by: Tianci Yin <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-06-21drm/amdgpu: enable sw smu driver for navi10 by defaultHawking Zhang1-1/+3
Navi10 will use sw smu driver for dynamic power managment, while vega20 could also use sw smu driver when amdgpu_dpm is set to 2 Signed-off-by: Hawking Zhang <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-06-21drm/amd: add gfxoff support on navi10Kenneth Feng3-5/+26
add the gfxoff interface to navi10,it's disabled by default. Signed-off-by: Kenneth Feng <[email protected]> Reviewed-by: Hawking Zhang <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-06-21drm/amd/powerplay: implement smc firmware v2.1 for smu11Kevin Wang1-0/+13
1.add smc_firmware_header_v2_1 hfirmware support, support more pptable in smc firmware. 2.optimization current pptable load framework. 3.rename read_pptable_from_vbios with setup_pptable. Signed-off-by: Kevin Wang <[email protected]> Reviewed-by: Huang Rui <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-06-21drm/amdgpu: bump smc firmware header version to v2 (v2)Huang Rui2-0/+16
This patch bumps smc firmware header version to v2 for storing soft pptable. v2: fix the typo, and add prints for v2 header Signed-off-by: Huang Rui <[email protected]> Reviewed-by: Hawking Zhang <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-06-21drm/amdgpu: add to set navi ip blocksHuang Rui1-0/+8
Set the IPs for navi10 in early_init like other asics. Signed-off-by: Huang Rui <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Reviewed-by: Hawking Zhang <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-06-21drm/amdgpu: add Navi10 pci idsAlex Deucher1-0/+6
Signed-off-by: Alex Deucher <[email protected]>
2019-06-21drm/amdkfd: Add navi10 support to amdkfd. (v3)Philip Cox1-0/+8
KFD (kernel fusion driver) is the kernel driver for the compute backend for usermode compute stack. v2: squash in updates (Alex) v3: squash in rebase fixes (Alex) Signed-off-by: Oak Zeng <[email protected]> Signed-off-by: Philip Cox <[email protected]> Acked-by: Alex Deucher <[email protected]> Signed-off-by: Hawking Zhang <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
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