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2020-01-14drm/amd/powerplay: cover the powerplay implementation details V3Evan Quan12-208/+212
This can save users much troubles. As they do not actually need to care whether swSMU or traditional powerplay routine should be used. V2: apply the fixes to vi.c and cik.c also V3: squash in oops fix Signed-off-by: Evan Quan <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-01-14drm/amdkfd: Improve function get_sdma_rlc_reg_offset() (v2)Yong Zhao1-22/+46
The SOC15_REG_OFFSET() macro needs to dereference adev->reg_offset[IP] pointer, which is sometimes NULL when there are fewer than 8 sdma engines. Avoid that by not initializing the array regardless. v2: squash in warning fixes Signed-off-by: Yong Zhao <[email protected]> Reviewed-by: Felix Kuehling <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-01-07Revert "drm/amdgpu: Set no-retry as default."Alex Deucher1-2/+2
This reverts commit 51bfac71cade386966791a8db87a5912781d249f. This causes stability issues on some raven boards. Revert for now until a proper fix is completed. Bug: https://gitlab.freedesktop.org/drm/amd/issues/934 Bug: https://bugzilla.kernel.org/show_bug.cgi?id=206017 Reviewed-by: Felix Kuehling <[email protected]> Reviewed-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-01-07drm/amdgpu/gfx: simplify old firmware warningAlex Deucher2-4/+2
Put it on one line to avoid whitespace issues when printing in the log. Reviewed-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-01-07drm/amdgpu/gmc10: use common invalidation engine helperAlex Deucher2-16/+5
Rather than open coding it. This also changes the free masks to better reflect the usage by other components. Acked-by: Felix Kuehling <[email protected]> Acked-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-01-07drm/amdgpu/gmc: move invaliation bitmap setup to common codeAlex Deucher4-41/+42
So it can be shared with newer GMC versions. Reviewed-by: Felix Kuehling <[email protected]> Reviewed-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-01-07drm/amdgpu: updated UMC error address record with correct channel indexJohn Clements1-33/+32
defined macros for repetitive for loops Reviewed-by: Guchun Chen <[email protected]> Signed-off-by: John Clements <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-01-07drm/amdgpu: resolved bug in UMC RAS CE queryJohn Clements1-12/+20
switch CE counter register access' to use SMN disable UMC indexing mode Reviewed-by: Tao Zhou <[email protected]> Signed-off-by: John Clements <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-01-07drm/amd/powerplay: cleanup the interfaces for powergate setting through SMUEvan Quan2-32/+34
Provided an unified entry point. And fixed the confusing that the API usage is conflict with what the naming implies. Signed-off-by: Evan Quan <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-01-07drm/amd/amdgpu: L1 Policy(5/5) - removed IH_CHICKEN from VFZhigang Luo1-10/+12
Signed-off-by: Zhigang Luo <[email protected]> Signed-off-by: Jane Jian <[email protected]> Reviewed-by: Emily Deng <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-01-07drm/amd/amdgpu: L1 Policy(3/5) - removed ECC interrupt from VFZhigang Luo1-7/+11
Signed-off-by: Zhigang Luo <[email protected]> Signed-off-by: Jane Jian <[email protected]> Reviewed-by: Emily Deng <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-01-07drm/amd/amdgpu: L1 Policy(2/5) - removed GC GRBM violations from gfxhubZhigang Luo2-37/+44
Signed-off-by: Zhigang Luo <[email protected]> Signed-off-by: Jane Jian <[email protected]> Reviewed-by: Emily Deng <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-01-07drm/amd/amdgpu: L1 Policy(1/5) - removed VM settings for mmhub and gfxhub ↵Zhigang Luo2-37/+48
from VF Signed-off-by: Zhigang Luo <[email protected]> Signed-off-by: Jane Jian <[email protected]> Reviewed-by: Emily Deng <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-01-07drm/amdgpu: removed GFX RAS support check in UMC ECC callbackJohn Clements1-7/+1
enable GPU recovery in event of uncorrectable UMC error Signed-off-by: John Clements <[email protected]> Reviewed-by: Hawking Zhang <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-01-07drm/amdgpu: added function to wait for PSP BL availabilityJohn Clements1-14/+28
reduced duplicate code increased wait time for PSP BL readiness Signed-off-by: John Clements <[email protected]> Reviewed-by: Guchun Chen <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-01-07drm/amdgpu: use linux size macro to simplify ONE_Kib & One_MibKevin Wang2-10/+3
replace internal size macro with linux size macro Signed-off-by: Kevin Wang <[email protected]> Reviewed-by: Tianci Yin <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-01-07drm/amdgpu: resolve bug in UMC 6 error counter queryJohn Clements2-90/+64
iterate over all error counter registers in SMN space removed support error counter access via MMIO Reviewed-by: Guchun Chen <[email protected]> Signed-off-by: John Clements <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-01-07amd/amdgpu/sriov tdr enablement with pp_onevf_modeJack Zhang1-1/+5
Under sriov and pp_onevf mode, 1.take resume instead of hw_init for smc recover to avoid potential memory leak. 2.add return condition inside smc resume function for sriov_pp_onevf_mode and pm_enabled param. Signed-off-by: Jack Zhang <[email protected]> Acked-by: Evan Quan <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-01-07amd/amdgpu/sriov enable onevf mode for ARCTURUS VFJack Zhang2-3/+3
Before, initialization of smu ip block would be skipped for sriov ASICs. But if there's only one VF being used, guest driver should be able to dump some HW info such as clks, temperature,etc. To solve this, now after onevf mode is enabled, host driver will notify guest. If it's onevf mode, guest will do smu hw_init and skip some steps in normal smu hw_init flow because host driver has already done it for smu. With this fix, guest app can talk with smu and dump hw information from smu. v2: refine the logic for pm_enabled.Skip hw_init by not changing pm_enabled. v3: refine is_support_sw_smu and fix some indentation issue. Signed-off-by: Jack Zhang <[email protected]> Acked-by: Evan Quan <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-01-07drm/amdgpu: update UMC 6.1 RAS error counter register access pathJohn Clements1-5/+5
use proper method for SMN register access Reviewed-by: Tao Zhou <[email protected]> Signed-off-by: John Clements <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-01-07drm/amdgpu: amalgamated PSP TA invoke functionsJohn Clements1-103/+34
reduce duplicate code Reviewed-by: Guchun Chen <[email protected]> Signed-off-by: John Clements <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-01-07drm/amdgpu: amalgamate PSP TA load/unload functionsJohn Clements1-99/+39
reduce duplicate code Reviewed-by: Guchun Chen <[email protected]> Signed-off-by: John Clements <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-01-07drm/amdgpu: by default output PSP ret status in event of cmd failureJohn Clements1-2/+2
update log level from DRM_DEBUG_DRIVER to DRM_WARN Reviewed-by: Guchun Chen <[email protected]> Signed-off-by: John Clements <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-01-07drm/amdgpu: correct RLC firmwares loading sequenceEvan Quan2-2/+2
Per confirmation with RLC firmware team, the RLC should be unhalted after all RLC related firmwares uploaded. However, in fact the RLC is unhalted immediately after RLCG firmware uploaded. And that may causes unexpected PSP hang on loading the succeeding RLC save restore list related firmwares. So, we correct the firmware loading sequence to load RLC save restore list related firmwares before RLCG ucode. That will help to get around this issue. Signed-off-by: Evan Quan <[email protected]> Reviewed-by: Hawking Zhang <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-01-07drm/amd/powerplay: add check for baco support on ArcturusEvan Quan1-0/+1
This is used to determine whether runtime pm can be supported or not. Signed-off-by: Evan Quan <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-01-07Revert "drm/amdgpu: simplify ATPX detection"Alex Deucher1-1/+11
This reverts commit f5fda6d89afe6e9cedaa1c3303903c905262f6e8. You can't use BASE_CLASS in pci_get_class. Bug: https://gitlab.freedesktop.org/drm/amd/issues/995 Acked-by: Evan Quan <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-01-07drm/amdgpu: simplify function return logicGuchun Chen1-6/+2
Former return logic is redundant. Signed-off-by: Guchun Chen <[email protected]> Reviewed-by: Le Ma <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-01-07drm/amdgpu: add DRIVER_SYNCOBJ_TIMELINE to amdgpuChunming Zhou1-1/+2
Can expose it now that the khronos has exposed the vlk extension. Signed-off-by: Chunming Zhou <[email protected]> Reviewed-by: Flora Cui <[email protected]> Reviewed-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-01-07drm/amdgpu: add DRIVER_SYNCOBJ_TIMELINE to amdgpuChunming Zhou1-1/+2
Can expose it now that the khronos has exposed the vlk extension. Signed-off-by: Chunming Zhou <[email protected]> Reviewed-by: Flora Cui <[email protected]> Reviewed-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]> Cc: [email protected]
2020-01-07Revert "drm/amdgpu: Set no-retry as default."Alex Deucher1-2/+2
This reverts commit 51bfac71cade386966791a8db87a5912781d249f. This causes stability issues on some raven boards. Revert for now until a proper fix is completed. Bug: https://gitlab.freedesktop.org/drm/amd/issues/934 Bug: https://bugzilla.kernel.org/show_bug.cgi?id=206017 Reviewed-by: Felix Kuehling <[email protected]> Reviewed-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]> Cc: [email protected]
2020-01-01drm/amdgpu: correct RLC firmwares loading sequenceEvan Quan2-2/+2
Per confirmation with RLC firmware team, the RLC should be unhalted after all RLC related firmwares uploaded. However, in fact the RLC is unhalted immediately after RLCG firmware uploaded. And that may causes unexpected PSP hang on loading the succeeding RLC save restore list related firmwares. So, we correct the firmware loading sequence to load RLC save restore list related firmwares before RLCG ucode. That will help to get around this issue. Signed-off-by: Evan Quan <[email protected]> Reviewed-by: Hawking Zhang <[email protected]> Signed-off-by: Alex Deucher <[email protected]> Cc: [email protected]
2019-12-29drm/amdgpu: enable gfxoff for raven1 refreshchangzhu1-11/+4
When smu version is larger than 0x41e2b, it will load raven_kicker_rlc.bin.To enable gfxoff for raven_kicker_rlc.bin,it needs to avoid adev->pm.pp_feature &= ~PP_GFXOFF_MASK when it loads raven_kicker_rlc.bin. Signed-off-by: changzhu <[email protected]> Reviewed-by: Huang Rui <[email protected]> Acked-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-12-29Revert "drm/amdgpu: simplify ATPX detection"Alex Deucher1-1/+11
This reverts commit f5fda6d89afe6e9cedaa1c3303903c905262f6e8. You can't use BASE_CLASS in pci_get_class. Bug: https://gitlab.freedesktop.org/drm/amd/issues/995 Acked-by: Evan Quan <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-12-23drm/amdgpu: use true, false for bool variable in amdgpu_psp.czhengbin1-6/+6
Fixes coccicheck warning: drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c:674:2-26: WARNING: Assignment of 0/1 to bool variable drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c:794:1-25: WARNING: Assignment of 0/1 to bool variable drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c:897:2-36: WARNING: Assignment of 0/1 to bool variable drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c:1016:1-35: WARNING: Assignment of 0/1 to bool variable drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c:1087:2-34: WARNING: Assignment of 0/1 to bool variable drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c:1177:1-33: WARNING: Assignment of 0/1 to bool variable Reported-by: Hulk Robot <[email protected]> Signed-off-by: zhengbin <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-12-23drm/amdgpu: use true, false for bool variable in amdgpu_debugfs.czhengbin1-3/+3
Fixes coccicheck warning: drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:132:2-10: WARNING: Assignment of 0/1 to bool variable drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:140:2-10: WARNING: Assignment of 0/1 to bool variable drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:142:13-21: WARNING: Assignment of 0/1 to bool variable Reported-by: Hulk Robot <[email protected]> Signed-off-by: zhengbin <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-12-23drm/amdgpu: use true, false for bool variable in amdgpu_device.czhengbin1-2/+2
Fixes coccicheck warning: drivers/gpu/drm/amd/amdgpu/amdgpu_device.c:3961:1-19: WARNING: Assignment of 0/1 to bool variable drivers/gpu/drm/amd/amdgpu/amdgpu_device.c:3981:1-19: WARNING: Assignment of 0/1 to bool variable Reported-by: Hulk Robot <[email protected]> Signed-off-by: zhengbin <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-12-23drm/amdgpu: use true, false for bool variable in mxgpu_nv.czhengbin1-2/+2
Fixes coccicheck warning: drivers/gpu/drm/amd/amdgpu/mxgpu_nv.c:255:2-20: WARNING: Assignment of 0/1 to bool variable drivers/gpu/drm/amd/amdgpu/mxgpu_nv.c:267:2-20: WARNING: Assignment of 0/1 to bool variable Reported-by: Hulk Robot <[email protected]> Signed-off-by: zhengbin <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-12-23drm/amdgpu: use true, false for bool variable in mxgpu_ai.czhengbin1-2/+2
Fixes coccicheck warning: drivers/gpu/drm/amd/amdgpu/mxgpu_ai.c:253:2-20: WARNING: Assignment of 0/1 to bool variable drivers/gpu/drm/amd/amdgpu/mxgpu_ai.c:265:2-20: WARNING: Assignment of 0/1 to bool variable Reported-by: Hulk Robot <[email protected]> Signed-off-by: zhengbin <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-12-23drm/amdgpu: add missed return value set for error caseGuchun Chen1-0/+1
Return value should be set when going to error handle tag for error case, this can avoid potential invalid array access by upper caller. Signed-off-by: Guchun Chen <[email protected]> Reviewed-by: Hawking Zhang <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-12-23drm/amdgpu: remove FB location config for sriovFrank.Min2-17/+1
FB location is already programmed by HV driver for arcutus so remove this part Signed-off-by: Frank.Min <[email protected]> Reviewed-by: Emily Deng <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-12-23drm/amdgpu: enable xgmi init for sriov use caseFrank.Min1-19/+7
1. enable xgmi ta initialization for sriov 2. enable xgmi initialization for sriov Signed-off-by: Frank.Min <[email protected]> Reviewed-by: Hawking Zhang <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-12-23drm/amdgpu: remove memory training p2c buffer reservation(V2)Tianci.Yin2-20/+2
IP discovery TMR(occupied the top VRAM with size DISCOVERY_TMR_SIZE) has been reserved, and the p2c buffer is in the range of this TMR, so the p2c buffer reservation is unnecessary. Reviewed-by: Alex Deucher <[email protected]> Reviewed-by: Kevin Wang <[email protected]> Reviewed-by: Xiaojie Yuan <[email protected]> Signed-off-by: Tianci.Yin <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-12-23drm/amdgpu: update the method to get fb_loc of memory training(V4)Tianci.Yin6-39/+23
The method of getting fb_loc changed from parsing VBIOS to taking certain offset from top of VRAM Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Tianci.Yin <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-12-23drm/amdgpu: Remove unneeded variable 'ret' in navi10_ih.cMa Feng1-2/+1
Fixes coccicheck warning: drivers/gpu/drm/amd/amdgpu/navi10_ih.c:113:5-8: Unneeded variable: "ret". Return "0" on line 182 Reported-by: Hulk Robot <[email protected]> Signed-off-by: Ma Feng <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-12-23drm/amdgpu: Remove unneeded variable 'ret' in amdgpu_device.cMa Feng1-3/+1
Fixes coccicheck warning: drivers/gpu/drm/amd/amdgpu/amdgpu_device.c:1036:5-8: Unneeded variable: "ret". Return "0" on line 1079 Reported-by: Hulk Robot <[email protected]> Signed-off-by: Ma Feng <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-12-23drm/amdgpu/gfx: Add mmSDMA2-7_EDC_COUNTER to support ArcturusJames Zhu1-4/+20
Add mmSDMA2-7_EDC_COUNTER to support Arcturus Signed-off-by: James Zhu <[email protected]> Reviewed-by: Yong Zhao <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-12-23drm/amdgpu/gfx: Add mmCOMPUTE_STATIC_THREAD_MGMT_SE4-7 to support ArcturusJames Zhu1-13/+25
Add mmCOMPUTE_STATIC_THREAD_MGMT_SE4-7 to support Arcturus Signed-off-by: James Zhu <[email protected]> Reviewed-by: Yong Zhao <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-12-23drm/amdgpu/gfx: Replace ARRAY_SIZE with size variableJames Zhu1-10/+17
Replace ARRAY_SIZE with size variables to support different ASICs. Signed-off-by: James Zhu <[email protected]> Reviewed-by: Yong Zhao <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-12-23drm/amdgpu: Added ASIC specific check in gmc v9.0 ECC interrupt programming ↵John Clements1-0/+5
sequence Devices newer then VEGA10/12 shall have these programming sequences performed by PSP BL Reviewed-by: Hawking Zhang <[email protected]> Signed-off-by: John Clements <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-12-23drm/amdgpu: enlarge agp_start address into 48bitFrank.Min1-1/+1
max range of the agp aperture is 48 bits, so enlarge agp_start address into 48bit with all bits set Signed-off-by: Frank.Min <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
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