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2022-06-20drm: Drop drm_framebuffer.h from drm_crtc.hVille Syrjälä1-0/+1
drm_crtc.h has no need for drm_frambuffer.h, so don't include it. Avoids useless rebuilds of the entire universe when touching drm_framebuffer.h. Quite a few placs do currently depend on drm_framebuffer.h without actually including it directly. All of those need to be fixed up. v2: Fix up msm some more v2: Deal with ingenic and shmobile as well Signed-off-by: Ville Syrjälä <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected] Acked-by: Sam Ravnborg <[email protected]> Acked-by: Jani Nikula <[email protected]>
2022-06-15Merge tag 'drm-misc-next-2022-06-08' of ↵Daniel Vetter2-35/+43
git://anongit.freedesktop.org/drm/drm-misc into drm-next drm-misc-next for 5.20: UAPI Changes: * connector: export bpc limits in debugfs * dma-buf: Print buffer name in debugfs Cross-subsystem Changes: * dma-buf: Improve dma-fence handling; Cleanups * fbdev: Device-unregistering fixes Core Changes: * client: Only use driver-validated modes to avoid blank screen * dp-aux: Make probing more reliable; Small fixes * edit: CEA data-block iterators; Introduce struct drm_edid; Many cleanups * gem: Don't use framebuffer format's non-exising color planes * probe-helper: Use 640x480 as DisplayPort fallback; Refactoring * scheduler: Don't kill jobs in interrupt context Driver Changes: * amdgpu: Use atomic fence helpers in DM; Fix VRAM address calculation; Export CRTC bpc settings via debugfs * bridge: Add TI-DLPC3433; anx7625: Fixes; fy07024di26a30d: Optional GPIO reset; icn6211: Cleanups; ldb: Add reg and reg-name properties to bindings, Kconfig fixes; lt9611: Fix display sensing; lt9611uxc: Fixes; nwl-dsi: Fixes; ps8640: Cleanups; st7735r: Fixes; tc358767: DSI/DPI refactoring and DSI-to-eDP support, Fixes; ti-sn65dsi83: Fixes; * gma500: Cleanup connector I2C handling * hyperv: Unify VRAM allocation of Gen1 and Gen2 * i915: export CRTC bpc settings via debugfs * meson: Support YUV422 output; Refcount fixes * mgag200: Support damage clipping; Support gamma handling; Protect concurrent HW access; Fixes to connector; Store model-specific limits in device-info structure; Cleanups * nouveau: Fixes and Cleanups * panel: Kconfig fixes * panfrost: Valhall support * r128: Fix bit-shift overflow * rockchip: Locking fixes in error path; Minor cleanups * ssd130x: Fix built-in linkage * ttm: Cleanups * udl; Always advertize VGA connector * fbdev/vesa: Support COMPILE_TEST Signed-off-by: Daniel Vetter <[email protected]> From: Thomas Zimmermann <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/YqBtumw05JZDEZE2@linux-uq9g
2022-06-14drm/amdgpu: remove redundant enable_mes and enable_mes_kiqYifan Zhang1-8/+0
enable_mes and enable_mes_kiq are set in both device init and MES IP init. Leave the ones in MES IP init, since it is a more accurate way to judge from GC IP version. Signed-off-by: Yifan Zhang <[email protected]> Acked-by: Alex Deucher <[email protected]> Reviewed-by: Jack Xiao <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2022-06-14drm/amdkfd: Add available memory ioctlDaniel Phillips2-4/+35
Add a new KFD ioctl to return the largest possible memory size that can be allocated as a buffer object using kfd_ioctl_alloc_memory_of_gpu. It attempts to use exactly the same accept/reject criteria as that function so that allocating a new buffer object of the size returned by this new ioctl is guaranteed to succeed, barring races with other allocating tasks. This IOCTL will be used by libhsakmt: https://www.mail-archive.com/[email protected]/msg75743.html Signed-off-by: Daniel Phillips <[email protected]> Signed-off-by: David Yat Sin <[email protected]> Reviewed-by: Felix Kuehling <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2022-06-14Revert "drm/amdgpu/gmc11: enable AGP aperture"Chengming Gui4-11/+9
This reverts commit 2cfe34e18970d26bff73c63f16c76dae22138d19. Enable AGP aperture cause SDMA page fault for gfx11.0.2, so temp disable AGP aperture until SDMA FW resolved this. Reviewed-by: Hawking Zhang <[email protected]> Signed-off-by: Jack Gui <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2022-06-14drm/amdgpu: Fix GTT size reporting in amdgpu_ioctlMichel Dänzer1-2/+0
The commit below changed the TTM manager size unit from pages to bytes, but failed to adjust the corresponding calculations in amdgpu_ioctl. Fixes: dfa714b88eb0 ("drm/amdgpu: remove GTT accounting v2") Bug: https://gitlab.freedesktop.org/drm/amd/-/issues/1930 Bug: https://gitlab.freedesktop.org/mesa/mesa/-/issues/6642 Tested-by: Martin Roukala <[email protected]> Tested-by: Mike Lothian <[email protected]> Reviewed-by: Christian König <[email protected]> Signed-off-by: Michel Dänzer <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2022-06-14drm/amd: disable GPA mode in backdoor loadYifan Zhang1-0/+3
GPA mode should be disabled in direct load. Signed-off-by: Yifan Zhang <[email protected]> Reviewed-by: Tim Huang <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2022-06-14drm/amdgpu/discovery: enable vcn/jpeg v4_0_2Yifan Zhang1-0/+1
Enable vcn/jpeg 4_0_2. Signed-off-by: Yifan Zhang <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Reviewed-by: Tim Huang <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2022-06-10drm/amdgpu: Stop any pending reset if another in progress.Andrey Grodzovsky1-0/+27
We skip rest requests if another one is already in progress. Signed-off-by: Andrey Grodzovsky <[email protected]> Reviewed-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2022-06-10drm/amdgpu: Rename amdgpu_device_gpu_recover_imp back to ↵Andrey Grodzovsky9-9/+9
amdgpu_device_gpu_recover We removed the wrapper that was queueing the recover function into reset domain queue who was using this name. Signed-off-by: Andrey Grodzovsky <[email protected]> Reviewed-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2022-06-10drm/amdgpu: Add work_struct for GPU reset from kfd.Andrey Grodzovsky3-32/+15
We need to have a work_struct to cancel this reset if another already in progress. Signed-off-by: Andrey Grodzovsky <[email protected]> Reviewed-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2022-06-10drm/amdgpu: Add work_struct for GPU reset from debugfsAndrey Grodzovsky2-2/+19
We need to have a work_struct to cancel this reset if another already in progress. Signed-off-by: Andrey Grodzovsky <[email protected]> Reviewed-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2022-06-10drm/admgpu: Serialize RAS recovery work directly into reset domain queue.Andrey Grodzovsky1-2/+4
Save the extra usless work schedule. Signed-off-by: Andrey Grodzovsky <[email protected]> Acked-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2022-06-10drm/amdgpu: Cache result of last reset at reset domain level.Andrey Grodzovsky3-2/+6
Will be read by executors of async reset like debugfs. Signed-off-by: Andrey Grodzovsky <[email protected]> Reviewed-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2022-06-09Merge tag 'amd-drm-fixes-5.19-2022-06-08' of ↵Dave Airlie14-115/+140
https://gitlab.freedesktop.org/agd5f/linux into drm-fixes amd-drm-fixes-5.19-2022-06-08: amdgpu: - DCN 3.1 golden settings fix - eDP fixes - DMCUB fixes - GFX11 fixes and cleanups - VCN fix for yellow carp - GMC11 fixes - RAS fixes - GPUVM TLB flush fixes - SMU13 fixes - VCN3 AV1 regression fix - VCN2 JPEG fix - Other misc fixes amdkfd: - MMU notifier fix - Support for more GC 10.3.x families - Pinned BO handling fix - Partial migration bug fix Signed-off-by: Dave Airlie <[email protected]> From: Alex Deucher <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2022-06-08drm/amdgpu/mes: only invalid/prime icache when finish loading both pipe MES FWs.Yifan Zhang1-16/+20
invalid/prime icahce operation takes effect both pipes cuconrrently, therefore CP_MES_IC_BASE_LO/HI and CP_MES_MDBASE_LO/HI both have to be set before prime icache. Otherwise MES hardware gets garbage data in above regsters and causes page fault [ 470.873200] amdgpu 0000:33:00.0: amdgpu: [gfxhub] page fault (src_id:0 ring:217 vmid:0 pasid:0, for process pid 0 thread pid 0) [ 470.873222] amdgpu 0000:33:00.0: amdgpu: in page starting at address 0x000092cb89b00000 from client 10 [ 470.873234] amdgpu 0000:33:00.0: amdgpu: GCVM_L2_PROTECTION_FAULT_STATUS:0x00000BB3 [ 470.873242] amdgpu 0000:33:00.0: amdgpu: Faulty UTCL2 client ID: CPC (0x5) [ 470.873247] amdgpu 0000:33:00.0: amdgpu: MORE_FAULTS: 0x1 [ 470.873251] amdgpu 0000:33:00.0: amdgpu: WALKER_ERROR: 0x1 [ 470.873256] amdgpu 0000:33:00.0: amdgpu: PERMISSION_FAULTS: 0xb [ 470.873260] amdgpu 0000:33:00.0: amdgpu: MAPPING_ERROR: 0x1 [ 470.873264] amdgpu 0000:33:00.0: amdgpu: RW: 0x0 Signed-off-by: Yifan Zhang <[email protected]> Acked-by: Alex Deucher <[email protected]> Reviewed-by: Tim Huang <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2022-06-08drm/amdgpu: always flush the TLB on gfx8Christian König1-0/+5
The TLB on GFX8 stores each block of 8 PTEs where any of the valid bits are set. Fixes: 5255e146c99a ("drm/amdgpu: rework TLB flushing") Reviewed-by: Alex Deucher <[email protected]> Tested-by: Michal Kubecek <[email protected]> Signed-off-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2022-06-08drm/amdgpu: fix limiting AV1 to the first instance on VCN3Christian König1-10/+7
The job is not yet initialized here. Bug: https://gitlab.freedesktop.org/drm/amd/-/issues/2037 Reviewed-by: Alex Deucher <[email protected]> Tested-by: Pierre-Eric Pelloux-Prayer <[email protected]> Signed-off-by: Christian König <[email protected]> Fixes: cdc7893fc93f ("drm/amdgpu: use job and ib structures directly in CS parsers") Signed-off-by: Alex Deucher <[email protected]>
2022-06-08drm/amdgpu/jpeg2: Add jpeg vmid update under IB submitMohammad Zafar Ziya2-1/+6
Add jpeg vmid update under IB submit Signed-off-by: Mohammad Zafar Ziya <[email protected]> Acked-by: Christian König <[email protected]> Reviewed-by: Lijo Lazar <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2022-06-08drm/amdgpu/mes: only invalid/prime icache when finish loading both pipe MES FWs.Yifan Zhang1-16/+20
invalid/prime icahce operation takes effect both pipes cuconrrently, therefore CP_MES_IC_BASE_LO/HI and CP_MES_MDBASE_LO/HI both have to be set before prime icache. Otherwise MES hardware gets garbage data in above regsters and causes page fault [ 470.873200] amdgpu 0000:33:00.0: amdgpu: [gfxhub] page fault (src_id:0 ring:217 vmid:0 pasid:0, for process pid 0 thread pid 0) [ 470.873222] amdgpu 0000:33:00.0: amdgpu: in page starting at address 0x000092cb89b00000 from client 10 [ 470.873234] amdgpu 0000:33:00.0: amdgpu: GCVM_L2_PROTECTION_FAULT_STATUS:0x00000BB3 [ 470.873242] amdgpu 0000:33:00.0: amdgpu: Faulty UTCL2 client ID: CPC (0x5) [ 470.873247] amdgpu 0000:33:00.0: amdgpu: MORE_FAULTS: 0x1 [ 470.873251] amdgpu 0000:33:00.0: amdgpu: WALKER_ERROR: 0x1 [ 470.873256] amdgpu 0000:33:00.0: amdgpu: PERMISSION_FAULTS: 0xb [ 470.873260] amdgpu 0000:33:00.0: amdgpu: MAPPING_ERROR: 0x1 [ 470.873264] amdgpu 0000:33:00.0: amdgpu: RW: 0x0 Signed-off-by: Yifan Zhang <[email protected]> Acked-by: Alex Deucher <[email protected]> Reviewed-by: Tim Huang <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2022-06-08drm/amdgpu: avoid to perform undesired clockgating operationEvan Quan1-2/+8
Make sure the clockgating feature is supported before action. Otherwise, the feature may be disabled unexpectedly on enablement request. Signed-off-by: Evan Quan <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2022-06-08drm/amdgpu: enable ASPM support for PCIE 7.4.0/7.6.0Evan Quan4-3/+122
Enable ASPM support for PCIE 7.4.0 and 7.6.0. Signed-off-by: Evan Quan <[email protected]> Reviewed-by: Lijo Lazar <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2022-06-08drm/amdgpu: fix scratch register access method in SRIOVZhenGuo Yin1-3/+4
The scratch register should be accessed through MMIO instead of RLCG in SRIOV, since it being used in RLCG register access function. Fixes: d54762cc3e6a ("drm/amdgpu: nuke dynamic gfx scratch reg allocation") Signed-off-by: ZhenGuo Yin <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2022-06-08drm/amdkfd: Document and fix GTT BO kmap APIFelix Kuehling2-8/+27
Removed an unused parameter from two functions and added kernel-doc comments. Signed-off-by: Felix Kuehling <[email protected]> Reviewed-by: Philip Yang <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2022-06-08drm/amdgpu: simplify amdgpu_ucode_get_load_type()Alex Deucher1-20/+0
This is the same as the default case, so drop the extra logic. Reviewed-by: Guchun Chen <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2022-06-08drm/amdgpu: Add peer-to-peer support among PCIe connected AMD GPUsRamesh Errabolu5-62/+283
Add support for peer-to-peer communication among AMD GPUs over PCIe bus. Support REQUIRES enablement of config HSA_AMD_P2P. Signed-off-by: Ramesh Errabolu <[email protected]> Reviewed-by: Felix Kuehling <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2022-06-08drm/amdgpu: Add MODE register to wave debug info in gfx11Joseph Greathouse1-0/+1
All other chips, from gfx6-gfx10, now include the MODE register at the end of the wave debug state. This appears to have been missed in gfx11, so this patch adds in MODE to the debug state for gfx11. Signed-off-by: Joseph Greathouse <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2022-06-08drm/amd/amdgpu: Fix alignment issueArunpravin Paneer Selvam2-3/+3
Fix alignment problems reported by zuul for the commit b07d1d73b09e ("drm/amd/amdgpu: Enable high priority gfx queue") Fixes: b07d1d73b09e ("drm/amd/amdgpu: Enable high priority gfx queue") Signed-off-by: Arunpravin Paneer Selvam <[email protected]> Reviewed-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2022-06-08drm/amdgpu/jpeg2: Add jpeg vmid update under IB submitMohammad Zafar Ziya2-1/+6
Add jpeg vmid update under IB submit Signed-off-by: Mohammad Zafar Ziya <[email protected]> Acked-by: Christian König <[email protected]> Reviewed-by: Lijo Lazar <[email protected]> Signed-off-by: Alex Deucher <[email protected]> Cc: [email protected]
2022-06-08drm/amdgpu: always flush the TLB on gfx8Christian König1-0/+5
The TLB on GFX8 stores each block of 8 PTEs where any of the valid bits are set. Fixes: 5255e146c99a ("drm/amdgpu: rework TLB flushing") Reviewed-by: Alex Deucher <[email protected]> Tested-by: Michal Kubecek <[email protected]> Signed-off-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2022-06-08drm/amdgpu: fix limiting AV1 to the first instance on VCN3Christian König1-10/+7
The job is not yet initialized here. Bug: https://gitlab.freedesktop.org/drm/amd/-/issues/2037 Reviewed-by: Alex Deucher <[email protected]> Tested-by: Pierre-Eric Pelloux-Prayer <[email protected]> Signed-off-by: Christian König <[email protected]> Fixes: cdc7893fc93f ("drm/amdgpu: use job and ib structures directly in CS parsers") Signed-off-by: Alex Deucher <[email protected]>
2022-06-07drm/amdgpu: Add MODE register to wave debug info in gfx11Joseph Greathouse1-0/+1
All other chips, from gfx6-gfx10, now include the MODE register at the end of the wave debug state. This appears to have been missed in gfx11, so this patch adds in MODE to the debug state for gfx11. Signed-off-by: Joseph Greathouse <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2022-06-07Revert "drm/amdgpu: Ensure the DMA engine is deactivated during set ups"Guchun Chen1-64/+45
This reverts commit b992a19085885c096b19625a85c674cb89829ca1. This causes regression in GPU reset related test. Cc: Alexander Deucher <[email protected]> Cc: [email protected] Signed-off-by: Guchun Chen <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2022-06-07Revert "drm/amdgpu: Ensure the DMA engine is deactivated during set ups"Guchun Chen1-64/+45
This reverts commit b992a19085885c096b19625a85c674cb89829ca1. This causes regression in GPU reset related test. Cc: Alexander Deucher <[email protected]> Cc: [email protected] Signed-off-by: Guchun Chen <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2022-06-06drm/amdgpu/soc21: add mode2 asic reset for SMU IP v13.0.4Alex Deucher1-0/+7
Set the default reset method to mode2 for SMU IP v13.0.4 Acked-by: Evan Quan <[email protected]> Reviewed-by: Tim Huang <[email protected]> Signed-off-by: Tim Huang <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2022-06-06drm/amdgpu/discovery: add comments about VCN instance handlingAlex Deucher1-0/+8
Add comments to clarify code that is safe, but triggers and smatch warning. Link: https://lists.freedesktop.org/archives/amd-gfx/2022-June/079905.html Signed-off-by: Alex Deucher <[email protected]> Cc: Dan Carpenter <[email protected]>
2022-06-06drm/amd/amdgpu: add pipe1 hardware supportArunpravin Paneer Selvam1-1/+1
Enable pipe1 support starting from SIENNA CICHLID asic Signed-off-by: Arunpravin Paneer Selvam <[email protected]> Acked-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2022-06-06drm/amd/amdgpu: Enable high priority gfx queueArunpravin Paneer Selvam5-27/+81
Starting from SIENNA CICHLID asic supports two gfx pipes, enabling two graphics queues, 1 on each pipe, pipe0 queue0 would be the normal piority queue and pipe1 queue0 would be the high priority queue Only one queue per pipe is visble to SPI, SPI looks at the priority value assigned to CP_GFX_HQD_QUEUE_PRIORITY from each of the queue's HQD/MQD. Create contexts applying AMDGPU_CTX_PRIORITY_HIGH which submits job to the high priority queue on GFX pipe1. There would be starvation of LP workload if HP workload is always available. v2: - remove unnecessary check(Nirmoy) - make pipe1 hardware support a separate patch(Nirmoy) - remove duplicate code(Shashank) - add CSA support for second gfx pipe(Alex) v3(Christian): - fix incorrect indentation - merge COMPUTE and GFX switch cases as both calls the same function. v4: - rebase w/ latest code base Signed-off-by: Arunpravin Paneer Selvam <[email protected]> Acked-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2022-06-06drm/amdgpu: adding device coredump supportSomalapuram Amaranath2-0/+69
Added device coredump information: - Kernel version - Module - Time - VRAM status - Guilty process name and PID - GPU register dumps v1 -> v2: Variable name change v1 -> v2: NULL check v1 -> v2: Code alignment v1 -> v2: Adding dummy amdgpu_devcoredump_free v1 -> v2: memset reset_task_info to zero v2 -> v3: add CONFIG_DEV_COREDUMP for variables v2 -> v3: remove NULL check on amdgpu_devcoredump_read Signed-off-by: Somalapuram Amaranath <[email protected]> Reviewed-by: Shashank Sharma <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2022-06-06drm/amdgpu: save the reset dump register value for devcoredumpSomalapuram Amaranath3-3/+11
Allocate memory for register value and use the same values for devcoredump. v1 -> v2: Change krealloc_array() to kmalloc_array() v2 -> v3: Fix alignment Signed-off-by: Somalapuram Amaranath <[email protected]> Reviewed-by: Shashank Sharma <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2022-06-03drm/amdgpu: fix up comment in amdgpu_device_asic_has_dc_support()Alex Deucher1-1/+1
LVDS support was implemented in DC a while ago. Just DAC support is left to do. Reviewed-by: Evan Quan <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2022-06-03drm/amdgpu: delete duplicate condition in gfx_v11_0_soft_reset()Dan Carpenter1-13/+11
We know that "grbm_soft_reset" is true because we're already inside an if (grbm_soft_reset) condition. No need to test again. Signed-off-by: Dan Carpenter <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2022-06-03drm/amdgpu/gmc11: enable AGP apertureAlex Deucher4-9/+11
Enable the AGP aperture on chips with GMC v11. Reviewed-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2022-06-03drm/amdgpu: convert nbio_v2_3_clear_doorbell_interrupt() to IP versionAlex Deucher1-1/+1
Check IP version rather than asic type. Reviewed-by: Guchun Chen <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2022-06-03drm/amdgpu: simplify the logic in amdgpu_device_parse_gpu_info_fw()Alex Deucher1-29/+0
Drop all of the extra cases in the default case. Reviewed-by: Guchun Chen <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2022-06-03drm/amdgpu: fix sdma doorbell issue on SDMA v6.0 and NBIO v7.7Xiaojian Du1-1/+7
This patch will fix sdma doorbell issue on SDMA v6.0 and NBIO v7.7.0. NBIO v7.7.0 uses a new reg function -- Common SDMA to allow a common doorbell range for all SDMA queues, this is different to the old NBIO version. This patch will add configuration for CSDMA and enable SDMA doorbell function. Signed-off-by: Xiaojian Du <[email protected]> Reviewed-by: Tim Huang <[email protected]> Reviewed-by: Huang Rui <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2022-06-03drm/amdgpu: add apu sequence in the imu v11Huang Rui2-4/+9
APU required to issue the enable GFX IMU message after IMU reset. Signed-off-by: Huang Rui <[email protected]> Reviewed-by: Tim Huang <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2022-06-03drm/amdgpu: add mmhub v3_0_1 ip blockHuang Rui4-1/+589
This adds mmhub v3_0_1 ip block support v2: rebase (Alex) Signed-off-by: Huang Rui <[email protected]> Reviewed-by: Tim Huang <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2022-06-03drm/amdgpu: use the callback function for reset status polling on IMUHuang Rui2-14/+24
Switch to use the callback function to poll the reset status on IMU. Because it will have different sequency on other ASICs. v2: drop unused variable (Alex) Acked-by: Alex Deucher <[email protected]> Signed-off-by: Huang Rui <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2022-06-03drm/amdgpu: print umc correctable error addressStanley.Yang2-2/+53
Signed-off-by: Stanley.Yang <[email protected]> Acked-by: Lijo Lazar <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
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