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Various bug fixes and improvements that accumulated over the last two
years.
Signed-off-by: Felix Kuehling <[email protected]>
Acked-by: Oded Gabbay <[email protected]>
Signed-off-by: Oded Gabbay <[email protected]>
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It's causing problems with user mode queues and the HIQ, and can
lead to hard hangs during boot after programming RLC_CP_SCHEDULERS.
Signed-off-by: Felix Kuehling <[email protected]>
Reviewed-by: Alex Deucher <[email protected]>
Signed-off-by: Oded Gabbay <[email protected]>
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Using checkpatch.pl -f <file> showed a number of style issues. This
patch addresses as many of them as possible. Some long lines have been
left for readability, but attempts to minimize them have been made.
v2: Broke long lines in gfx_v7 get_fw_version
Signed-off-by: Kent Russell <[email protected]>
Signed-off-by: Felix Kuehling <[email protected]>
Signed-off-by: Oded Gabbay <[email protected]>
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Remove hard-coded assumption that the first compute pipe is
reserved for amdgpu. Pipe 0 actually means pipe 0 now.
Signed-off-by: Felix Kuehling <[email protected]>
Reviewed-by: Oded Gabbay <[email protected]>
Signed-off-by: Oded Gabbay <[email protected]>
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Was using the wrong prefix (gmc rather than gfx). The function
is related to the gfx hw, not gmc. This also makes it consistent
with the naming in gfx8.
Reviewed-by: Harry Wentland <[email protected]>
Reviewed-by: Christian König <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>
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Power Gating is disabled in Stoney platform.
Reviewed-by: Alex Deucher <[email protected]>
Signed-off-by: Vijendar Mukunda <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>
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Added DW_I2S_QUIRK_16BIT_IDX_OVERRIDE quirk for Stoney.
Supported format and bus width for I2S controller read
from I2S Component Parameter registers.
These are ready only registers.
For Stoney, I2S Component Parameter registers are programmed
to support 32 bit format and 4 bytes bus width only.
By setting this quirk,It will override 32 bit format with
16 bit format and 2 bytes as bus width for Stoney.
Reviewed-by: Alex Deucher <[email protected]>
Signed-off-by: Vijendar Mukunda <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>
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Signed-off-by: Evan Quan <[email protected]>
Signed-off-by: Huang Rui <[email protected]>
Acked-by: Alex Deucher <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>
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Signed-off-by: Evan Quan <[email protected]>
Reviewed-by: Alex Deucher <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>
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digest_size has been retired from sdma v4 fw
Signed-off-by: Hawking Zhang <[email protected]>
Reviewed-by: Alex Deucher <[email protected]>
Reviewed-by: Evan Quan <[email protected]>
Reviewed-by: Junwei Zhang <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>
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My static checker complains that it's possible for "r" to be
uninitialized. It used to be set to zero so this returns it to the old
behavior.
Fixes: 98a7f88ce9a9 ("drm/amdgpu: bind BOs with GTT space allocated directly v2")
Reviewed-by: Christian König <[email protected]>
Reviewed-by: Michel Dänzer <[email protected]>
Signed-off-by: Dan Carpenter <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>
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If a ring is not initialized, it also should not be finished.
For example, in Vega10's SR-IOV environment, UVD's decode ring is not
initialized, but will be finnished in amdgpu_uvd_sw_fini, because UVD
driver put all the uvd decode ring's finish operation into
amdgpu_uvd_sw_fini function, while not uvd_vXXX_0_sw_fini. This will
lead to amdgpu module unloading failure.
Signed-off-by: Trigger Huang <[email protected]>
Reviewed-by: Monk Liu <[email protected]>
Reviewed-by: Christian König <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>
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Change "prefered" to "preferred"
Signed-off-by: Kent Russell <[email protected]>
Reviewed-by: Christian König <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>
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Change "stollen" to "stolen"
Signed-off-by: Kent Russell <[email protected]>
Reviewed-by: Christian König <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>
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We won't use this member in other files, so set it static.
Signed-off-by: Huang Rui <[email protected]>
Reviewed-by: Christian König <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>
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drm_*_reference() and drm_*_unreference() functions are just
compatibility alias for drm_*_get() and drm_*_put() and should not be
used by new code. So convert all users of compatibility functions to use
the new APIs.
Reviewed-by: Christian König <[email protected]>
Signed-off-by: Cihangir Akturk <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>
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May waste a bit of memory, but simplifies the interface
significantly.
v2: convert internal accounting to use 256bit slots
Reviewed-by: Christian König <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>
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There are no external users of function amdgpu_atif_handler so it can
be static.
Signed-off-by: Jean Delvare <[email protected]>
Cc: Alex Deucher <[email protected]>
Cc: "Christian König" <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>
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Include a missing header to get rid of the following warning:
drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c:65:6: warning: no previous prototype for ‘amdgpu_pm_acpi_event_handler’ [-Wmissing-prototypes]
void amdgpu_pm_acpi_event_handler(struct amdgpu_device *adev)
^
Signed-off-by: Jean Delvare <[email protected]>
Cc: Alex Deucher <[email protected]>
Cc: "Christian König" <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>
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Include a missing header to get rid of the following warning:
drivers/gpu/drm/amd/amdgpu/dce_v6_0.c:521:6: warning: no previous prototype for 'dce_v6_0_disable_dce' [-Wmissing-prototypes]
void dce_v6_0_disable_dce(struct amdgpu_device *adev)
^
Signed-off-by: Jean Delvare <[email protected]>
Cc: Alex Deucher <[email protected]>
Cc: "Christian König" <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>
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As I was staring at the si_init_golden_registers code, I noticed that
the Pitcairn initialization silently falls through the Cape Verde
initialization, and the Oland initialization falls through the Hainan
initialization. However there is no comment stating that this is
intentional, and the radeon driver doesn't have any such fallthrough,
so I suspect this is not supposed to happen.
Signed-off-by: Jean Delvare <[email protected]>
Fixes: 62a37553414a ("drm/amdgpu: add si implementation v10")
Cc: Ken Wang <[email protected]>
Cc: Alex Deucher <[email protected]>
Cc: "Marek Olšák" <[email protected]>
Cc: "Christian König" <[email protected]>
Cc: Flora Cui <[email protected]>
Reviewed-by: Marek Olšák <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>
Cc: [email protected]
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Move it up before ring enablement with all of the other
engine setup and explicitly disable it for bare metal.
Cc: Frank Min <[email protected]>
Reviewed-by: Christian König <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>
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We already allocate this as part of the ring structure,
use that instead.
Cc: Frank Min <[email protected]>
Reviewed-by: Christian König <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>
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The wb buffer is in system memory, not vram so the flush
is useless.
Cc: Frank Min <[email protected]>
Reviewed-by: Christian König <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>
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No functional change until wptr polling uses this
location (future patch).
v2: use WRITE_ONCE
Cc: Frank Min <[email protected]>
Reviewed-by: Christian König <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>
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kfd2kgd is device-specific, so it should not be a global variable.
Merge amdgpu_amdkfd_load_interface and amdgpu_amdkfd_device_probe
so that it's only needed as a local variable in one function.
Signed-off-by: Felix Kuehling <[email protected]>
Reviewed-by: Oded Gabbay <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>
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nbio registers are not used in this file.
Reviewed-by: Christian König <[email protected]>
Cc: Frank Min <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>
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The gfxhub and mmhub code are now helpers for gmc rather
than standalone IPs. When that changes these were left
over. Remove them.
Acked-by: Huang Rui <[email protected]>
Reviewed-by: Christian König <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>
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Use a lower case b to be consistent with the other wb functions.
Reviewed-by: Christian König <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>
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We achieved that by setting S(SYSTEM) and P(PDE as PTE) bit to 1 for
PDEs and setting S bit to 1 for PTEs when the corresponding addresses
are not occupied by gpu driver allocated buffers.
Signed-off-by: Yong Zhao <[email protected]>
Reviewed-by: Christian König <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>
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The parameter init_value contains the value to which we initialized
VRAM bo when AMDGPU_GEM_CREATE_VRAM_CLEARED flag is set.
Signed-off-by: Yong Zhao <[email protected]>
Reviewed-by: Christian König <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>
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Saves us even more loc.
Signed-off-by: Christian König <[email protected]>
Reviewed-by: Alex Deucher <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>
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Saves us quite a bunch of loc.
Signed-off-by: Christian König <[email protected]>
Reviewed-by: Alex Deucher <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>
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Same as amdgpu_bo_create_kernel, but keeps the BO reserved.
Signed-off-by: Christian König <[email protected]>
Reviewed-by: Alex Deucher <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>
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Make allocating the new BO optional.
Signed-off-by: Christian König <[email protected]>
Reviewed-by: Alex Deucher <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>
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Save some memory because only one of those is used at all times.
Signed-off-by: Christian König <[email protected]>
Reviewed-by: Alex Deucher <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>
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Move amdgpu_bo and related structures into amdgpu_object.h.
Move amdgpu_bo_list structures to the amdgpu_bo_list functions.
Signed-off-by: Christian König <[email protected]>
Reviewed-by: Alex Deucher <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>
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Instead of open coding the conversion from u64 to pointers.
Signed-off-by: Christian König <[email protected]>
Reviewed-by: Alex Deucher <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>
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Don't keep around the same pointer twice.
Signed-off-by: Christian König <[email protected]>
Reviewed-by: Alex Deucher <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>
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Signed-off-by: Evan Quan <[email protected]>
Reviewed-by: Ken Wang <[email protected]>
Reviewed-by: Huang Rui <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>
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While doing flr on VFs, there is possibility to lost the doorbell
writing for sdma, so enable poll mem for sdma, then sdma fw would
check the pollmem holding wptr.
Signed-off-by: Frank Min <[email protected]>
Signed-off-by: Xiangliang.Yu <[email protected]>
Acked-by: Alex Deucher <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>
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1.Since in sriov there is no need of decoding, so skip the related code;
2.Vcpu boot up and umc enable need to take at the end of the init sequence;
Signed-off-by: Frank Min <[email protected]>
Signed-off-by: Xiangliang.Yu <[email protected]>
Acked-by: Alex Deucher <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>
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Optimize init table sequence for sriov.
Signed-off-by: Frank Min <[email protected]>
Signed-off-by: Xiangliang.Yu <[email protected]>
Acked-by: Alex Deucher <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>
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Now uvd doorbell is from 0xf8-0xfb and vce doorbell is from 0xfc-0xff
Signed-off-by: Frank Min <[email protected]>
Signed-off-by: Xiangliang.Yu <[email protected]>
Acked-by: Alex Deucher <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>
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Since rptr would not be accessed on later secure asics in sriov, remove
the ring test.
Signed-off-by: Frank Min <[email protected]>
Signed-off-by: Xiangliang.Yu <[email protected]>
Acked-by: Alex Deucher <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>
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Interrupt enable is contained in vce init table and this register could
not be accessed in secure ASICs, so just remove it.
Signed-off-by: Frank Min <[email protected]>
Signed-off-by: Xiangliang.Yu <[email protected]>
Acked-by: Alex Deucher <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>
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Add uvd and vce re-init after gpu reset.
Signed-off-by: Frank Min <[email protected]>
Signed-off-by: Xiangliang.Yu <[email protected]>
Acked-by: Alex Deucher <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>
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MMSCH FW need to get the wptr from 0 after it get the mailbox request
from driver, since every time kick the mailbox, mmsch thinks that it
is the first time engine start to initialize.
Signed-off-by: Frank Min <[email protected]>
Signed-off-by: Xiangliang.Yu <[email protected]>
Acked-by: Alex Deucher <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>
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That function will be used later to support setting a page table
block with 64 bit value.
Signed-off-by: Yong Zhao <[email protected]>
Reviewed-by: Christian König <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>
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The dpm control for vcn has been moved to firmware, kernel always spins
"amdgpu: [powerplay] pp_dpm_powergate_uvd was not implemented", each
time when application runs, disable it for now till pg/cg. Also remove
clock manual setting when dpm disabled, which was inherited from uvd.
Signed-off-by: Leo Liu <[email protected]>
Reviewed-by: Alex Deucher <[email protected]>
Reviewed-by: Christian König <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>
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