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path: root/drivers/gpu/drm/amd/amdgpu/soc15_common.h
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2018-12-18drm/amdgpu:Improves robustness of SOC15_WAIT_ON_RREGJames Zhu1-2/+7
If register value is updating, reset timeout counter. It improves robustness of SOC15_WAIT_ON_RREG. Signed-off-by: James Zhu <[email protected]> Reviewed-by: Leo Liu <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2018-09-26drm/amdgpu/soc15: fix warnings in register macroAlex Deucher1-1/+1
expects argument of type ‘unsigned int’ has type ‘long int’ Fixes: 52e211c1f04 ("drm/amdgpu:Add error message when register failed to reach expected value") Reviewed-by: Christian König <[email protected]> Reviewed-by: James Zhu <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2018-09-26drm/amdgpu:Add DPG mode read/write macroJames Zhu1-0/+20
Some registers read/write needs program through SDRAM pool under DPG mode. Signed-off-by: James Zhu <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Reviewed-by: Huang Rui <[email protected]> Acked-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2018-09-13drm/amdgpu:Add error message when register failed to reach expected valueJames Zhu1-0/+2
Add error message when register failed to reach expected value, It will help discover potential issue. Signed-off-by: James Zhu <[email protected]> Acked-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2018-05-24drm/amdgpu: Add SOC15_WAIT_ON_RREG macro defineRex Zhu1-0/+15
Add new macro to wait on a register field to be a specific value. Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Rex Zhu <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-12-13drm/amdgpu: convert nbio to use callbacks (v2)Alex Deucher1-16/+0
Cleans up and consolidates all of the per-asic logic. v2: squash in "drm/amdgpu: fix NULL err for sriov detect" (Chunming) Acked-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-12-08drm/amdgpu: Change SOC15_REG_OFFSET to use dynamic register offsetShaoyun Liu1-5/+1
Acked-by: Christian Konig <[email protected]> Signed-off-by: Shaoyun Liu <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-12-08drm/amdgpu: Avoid use SOC15_REG_OFFSET in static const arrayShaoyun Liu1-6/+0
Handle dynamic offsets correctly in static arrays. Acked-by: Christian Konig <[email protected]> Signed-off-by: Shaoyun Liu <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-12-08drm/amdgpu: Use dynamic IP offset for register access on SOC15Shaoyun Liu1-26/+8
Update the register access macros and functions to take into account the new dynamic IP base offsets. Acked-by: Christian Konig <[email protected]> Signed-off-by: Shaoyun Liu <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-07-14drm/amdgpu: Add WREG32_SOC15_NO_KIQ macro defineShaoyun Liu1-0/+7
Signed-off-by: Shaoyun Liu <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-06-15drm/amd/amdgpu: Add offset variant to SOC15 macrosTom St Denis1-0/+14
Allows reading/writing via SOC15 macros with offset for various register banks. Signed-off-by: Tom St Denis <[email protected]> Acked-by: Christian König <[email protected]> Reviewed-by: Alex Deucher <[email protected]>
2017-04-28drm/amd/amdgpu: Introduce new read/write macros for SOC15Tom St Denis1-1/+19
Signed-off-by: Tom St Denis <[email protected]> Reviewed-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-03-29drm/amdgpu: add common soc15 headersKen Wang1-0/+57
These are used by various IP modules. Acked-by: Christian König <[email protected]> Signed-off-by: Ken Wang <[email protected]> Signed-off-by: Alex Deucher <[email protected]>