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path: root/drivers/gpu/drm/amd/amdgpu/soc15.c
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2024-04-26drm/amdgpu: update jpeg max decode resolutionSathishkumar S1-2/+2
jpeg ip version v2.1 and higher supports 16kx16k resolution decode Signed-off-by: Sathishkumar S <[email protected]> Acked-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2024-04-26drm/amdgpu: add protype for print ip stateSunil Khatri1-0/+1
Add the protoype for print ip state to be used to print the registers in devcoredump during a gpu reset. Signed-off-by: Sunil Khatri <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Reviewed-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2024-04-26drm/amdgpu: add prototype for ip dumpSunil Khatri1-0/+1
Add the prototype to dump ip registers for all ips of different asics and set them to NULL for now. Based on the requirement add a function pointer for each of them. Signed-off-by: Sunil Khatri <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Reviewed-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2024-04-09drm/amdgpu/pm: Add support for MACO flag checkingMa Jun1-5/+5
Add support for MACO flag checking. MACO mode only works if BACO is supported. Signed-off-by: Ma Jun <[email protected]> Reviewed-by: Lijo Lazar <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2024-02-26drm/amdgpu: Enable gpu reset for S3 abort cases on Raven seriesPrike Liang1-20/+25
Currently, GPU resets can now be performed successfully on the Raven series. While GPU reset is required for the S3 suspend abort case. So now can enable gpu reset for S3 abort cases on the Raven series. Signed-off-by: Prike Liang <[email protected]> Acked-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2024-02-22drm/amdgpu: Remove pcie bw sys entryAsad Kamal1-1/+0
Remove pcie bw sys entry for asics not supporting such function Signed-off-by: Asad Kamal <[email protected]> Reviewed-by: Lijo Lazar <[email protected]> Reviewed-by: Hawking Zhang <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2024-02-22Revert "drm/amdgpu: Add pci usage to nbio v7.9"Asad Kamal1-1/+1
Remove implementation to get pcie usage for nbio v7.9 as pcie usage is handled by fw This reverts commit 59070fd9ccea58c3363d39f69c25fa98c71eb02f. Signed-off-by: Asad Kamal <[email protected]> Reviewed-by: Lijo Lazar <[email protected]> Reviewed-by: Hawking Zhang <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2024-02-22drm/amdgpu: Do not toggle bif ras irq from guestHawking Zhang1-1/+2
Only do this from host side. Signed-off-by: Hawking Zhang <[email protected]> Reviewed-by: Tao Zhou <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2024-02-07drm/amdgpu: reset gpu for s3 suspend abort casePrike Liang1-0/+22
In the s3 suspend abort case some type of gfx9 power rail not turn off from FCH side and this will put the GPU in an unknown power status, so let's reset the gpu to a known good power state before reinitialize gpu device. Signed-off-by: Prike Liang <[email protected]> Acked-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-12-12Backmerge tag 'v6.7-rc5' into drm-nextDave Airlie1-5/+10
Linux 6.7-rc5 Alex requested this for some amdkfd work relying on the symbols exports. Signed-off-by: Dave Airlie <[email protected]>
2023-12-06drm/amdgpu: Avoid querying DRM MGCG statusLijo Lazar1-1/+2
MP0 v13.0.6 SOCs don't support DRM MGCG. Signed-off-by: Lijo Lazar <[email protected]> Reviewed-by: Hawking Zhang <[email protected]> Acked-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-12-06drm/amdgpu: Add NULL checks for function pointersLijo Lazar1-4/+8
Check if function is implemented before making the call. Signed-off-by: Lijo Lazar <[email protected]> Reviewed-by: Hawking Zhang <[email protected]> Acked-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-11-29drm/amdgpu: Use another offset for GC 9.4.3 remapLijo Lazar1-0/+5
The legacy region at 0x7F000 maps to valid registers in GC 9.4.3 SOCs. Use 0x1A000 offset instead as MMIO register remap region. Signed-off-by: Lijo Lazar <[email protected]> Reviewed-by: Hawking Zhang <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-11-29drm/amdgpu: Use another offset for GC 9.4.3 remapLijo Lazar1-0/+5
The legacy region at 0x7F000 maps to valid registers in GC 9.4.3 SOCs. Use 0x1A000 offset instead as MMIO register remap region. Signed-off-by: Lijo Lazar <[email protected]> Reviewed-by: Hawking Zhang <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-11-29drm/amdgpu: Read aquavanjaram PCIE register stateLijo Lazar1-0/+1
Add support to read aqua vanjaram PCIE register state Signed-off-by: Lijo Lazar <[email protected]> Reviewed-by: Hawking Zhang <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-10-26drm/amd: Move AMD_IS_APU check for ASPM into top level functionMario Limonciello1-2/+1
There is no need for every ASIC driver to perform the same check. Move the duplicated code into amdgpu_device_should_use_aspm(). Signed-off-by: Mario Limonciello <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-09-20drm/amdgpu: Use function for IP version checkLijo Lazar1-14/+13
Use an inline function for version check. Gives more flexibility to handle any format changes. Signed-off-by: Lijo Lazar <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-09-06drm/amdgpu: Fix refclk reporting for SMU v13.0.6Lijo Lazar1-1/+2
SMU v13.0.6 SOCs have 100MHz reference clock. Signed-off-by: Lijo Lazar <[email protected]> Reviewed-by: Hawking Zhang <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-09-06drm/amdgpu: Add RREG64_PCIE_EXT/WREG64_PCIE_EXT functionsCandice Li1-0/+2
Add 64bits register access support on register whose address is greater than 32bits. Signed-off-by: Candice Li <[email protected]> Reviewed-by: Tao Zhou <[email protected]> Reviewed-by: Hawking Zhang <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-08-30drm/amdgpu: Add SMU v13.0.6 default reset methodsLijo Lazar1-1/+3
For APUs with SMU v13.0.6, mode-2 reset is kept as default and for others mode-1 is the default reset method. Signed-off-by: Lijo Lazar <[email protected]> Reviewed-by: Hawking Zhang <[email protected]> Reviewed-by: Asad Kamal <[email protected]> Tested-by: Asad Kamal <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-08-09drm/amdgpu: Add pci usage to nbio v7.9Asad Kamal1-1/+1
Add implementation to get pcie usage for nbio v7.9. Signed-off-by: Asad Kamal <[email protected]> Reviewed-by: Lijo Lazar <[email protected]> Reviewed-by: Shiwu Zhang <[email protected]> Reviewed-by: Hawking Zhang <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-08-07drm/amdgpu: Add pci replay count to nbio v7.9Lijo Lazar1-1/+1
Add implementation to get pcie replay count for nbio v7.9. Signed-off-by: Lijo Lazar <[email protected]> Reviewed-by: Hawking Zhang <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-06-09Revert "drm/amdgpu: change the reference clock for raven/raven2"Alex Deucher1-3/+4
This reverts commit fbc24293ca16b3b9ef891fe32ccd04735a6f8dc1. This results in inconsistent timing reported via asynchronous GPU queries. Link: https://lists.freedesktop.org/archives/amd-gfx/2023-May/093731.html Cc: [email protected] Cc: [email protected] Reviewed-by: Michel Dänzer <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-06-09drm/amdgpu: retire set_vga_state for some ASICLikun Gao1-8/+0
set_vga_state operation only allowed on SI generation ASIC, retire the realted function on those ASIC which did not do anything. Signed-off-by: Likun Gao <[email protected]> Reviewed-by: Hawking Zhang <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-06-09drm/amdgpu: Add FGCG for GFX v9.4.3Lijo Lazar1-2/+3
It's not fine grain, behaves similar to MGCG. Signed-off-by: Lijo Lazar <[email protected]> Reviewed-by: Le Ma <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-06-09drm/amdgpu: Add mode-2 reset in SMU v13.0.6Lijo Lazar1-0/+9
Modifications to mode-2 reset flow for SMU v13.0.6 ASICs. Signed-off-by: Lijo Lazar <[email protected]> Reviewed-by: Le Ma <[email protected]> Reviewed-by: Asad Kamal <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-06-09drm/amdgpu: Enable CG for IH v4.4.2Asad kamal1-1/+2
Enable clock gating on IH v4.4.2 versions. Signed-off-by: Asad kamal <[email protected]> Reviewed-by: Lijo Lazar <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-06-09drm/amdgpu: Enable MGCG on SDMAv4.4.2Lijo Lazar1-2/+2
Enable clock gating on SDMAv4.4.2 versions. Leave memory light sleep to default. Signed-off-by: Lijo Lazar <[email protected]> Reviewed-by: Hawking Zhang <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-06-09drm/amdgpu: add vcn_4_0_3 codec querySonny Jiang1-0/+24
Add support for vcn_4_0_3 video codec query Signed-off-by: Sonny Jiang <[email protected]> Reviewed-by: James Zhu <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-06-09drm/amdgpu: Enable CGCG/LS for GC 9.4.3Lijo Lazar1-1/+2
Enable coarse grain clockgating/light sleep for GC v9.4.3. Remove programming that is not meant for GC 9.4.3. Signed-off-by: Lijo Lazar <[email protected]> Reviewed-by: Hawking Zhang <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-06-09drm/amdgpu: init gfx_v9_4_3 external_rev_idHawking Zhang1-0/+1
it is used for user space driver to identify gfx_v9_4_3 chip Signed-off-by: Hawking Zhang <[email protected]> Acked-by: Alex Deucher <[email protected]> Reviewed-by: Le Ma <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-06-09drm/amdgpu: add helpers to access registers on different AIDsLe Ma1-0/+1
SMN address which is larger than 32bit has different indications through bit[34:32] on different AIDs. v2: put smn addressing of different AIDs into asic specific place v3: change to ext_id/ext_offset naming Signed-off-by: Le Ma <[email protected]> Reviewed-by: Lijo Lazar <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-06-09drm/amdgpu: switch to aqua_vanjaram_doorbell_index_initLe Ma1-1/+23
New doorbell index assignment is used by aqua_vanjaram. Signed-off-by: Le Ma <[email protected]> Reviewed-by: Lijo Lazar <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-06-09drm/amdgpu: add indirect r/w interface for smn address greater than 32bitsLe Ma1-0/+2
On multiple AIDs platform, bit[34:32] in SMD address is leveraged to access nonAID0 register smn address and new PCI_INDEX_HI register is introduced to access the higher bits. v2: rebase on latest register accessors (Alex) Signed-off-by: Le Ma <[email protected]> Acked-by: Felix Kuehling <[email protected]> Reviewed-by: Lijo Lazar <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-06-09drm/amdgpu/vcn: enable vcn DPG mode for VCN4_0_3James Zhu1-0/+1
Enable vcn DPG mode for VCN4_0_3. Signed-off-by: James Zhu <[email protected]> Reviewed-by: Leo Liu <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-06-09drm/amdgpu/vcn: enable vcn pg for VCN4_0_3James Zhu1-0/+1
Enable vcn pg for VCN4_0_3. Signed-off-by: James Zhu <[email protected]> Reviewed-by: Leo Liu <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-06-09drm/amdgpu/vcn: enable vcn cg for VCN4_0_3James Zhu1-0/+1
Enable vcn cg for VCN4_0_3. Signed-off-by: James Zhu <[email protected]> Reviewed-by: Leo Liu <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-06-09drm/amdgpu/jpeg: enable jpeg pg for VCN4_0_3James Zhu1-1/+2
Enable jpeg pg for VCN4_0_3. Signed-off-by: James Zhu <[email protected]> Reviewed-by: Leo Liu <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-06-09drm/amdgpu/jpeg: enable jpeg cg for VCN4_0_3James Zhu1-1/+2
Enable jpeg cg for VCN4_0_3. Signed-off-by: James Zhu <[email protected]> Reviewed-by: Leo Liu <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-06-09drm/amdgpu: Enable doorbell selfring after resize FB BARShane Xiao1-10/+15
[Why] The selfring doorbell aperture will change when resize FB BAR successfully during gmc sw init, we should reorder the sequence of enabling doorbell selfring aperture. [How] Move enable_doorbell_selfring_aperture from *_common_hw_init to *_common_late_init. This fixes the potential issue that GPU ring its own doorbell when this device is in translated mode when iommu is on. v2: Remove *_enable_doorbell_aperture functions (Christian) v3: Add comments to note that why we need enable doorbell selfring late (Christian) Signed-off-by: Shane Xiao <[email protected]> Signed-off-by: Aaron Liu <[email protected]> Tested-by: Xiaomeng Hou <[email protected]> Reviewed-by: Christian K�nig <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-04-18drm/amdgpu: add xcc index argument to select_sh_se function v2Le Ma1-2/+2
v1: To support multiple XCD case (Le) v2: introduce xcc index to gfx_v11_0_select_sh_se (Hawking) Signed-off-by: Le Ma <[email protected]> Reviewed-by: Hawking Zhang <[email protected]> Signed-off-by: Hawking Zhang <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-04-18drm/amdgpu: add xcc index argument to soc15_grbm_selectLe Ma1-2/+2
To support grbm select for multiple XCD case. v2: unify naming style Signed-off-by: Le Ma <[email protected]> Reviewed-by: Hawking Zhang <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-04-14drm/amdgpu: add common early init support for GC 9.4.3Hawking Zhang1-0/+5
init asic funcs and cp/pg flags for GC 9.4.3 Signed-off-by: Hawking Zhang <[email protected]> Reviewed-by: Le Ma <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-04-14drm/amdgpu: change the reference clock for raven/raven2Jesse Zhang1-4/+3
Due to switch to golden tsc register to get clock counter for raven/ raven2. Chang the reference clock from 25MHZ to 100MHZ. Suggested-by: shanshengwang <[email protected]> Reviewed-by: Evan Quan <[email protected]> Signed-off-by: Jesse Zhang <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-03-15drm/amdgpu: Retire pcie_gen3_enable functionHawking Zhang1-20/+0
Not needed since from vi. drop the function so we don't duplicate code when introduce new asics. Signed-off-by: Hawking Zhang <[email protected]> Reviewed-by: Likun Gao <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-03-15drm/amdgpu: Move to common helper to query soc rev_idHawking Zhang1-6/+1
Replace soc15, nv, soc21 get_rev_id callback with common helper so we don't need to duplicate code when introduce new asics. Signed-off-by: Hawking Zhang <[email protected]> Reviewed-by: Likun Gao <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-03-15drm/amdgpu: Move to common indirect reg access helperHawking Zhang1-45/+4
Replace soc15, nv, soc21 specific callbacks with common one. so we don't need to duplicate code when introduce new asics. Signed-off-by: Hawking Zhang <[email protected]> Reviewed-by: Likun Gao <[email protected]> Acked-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-03-07drm/amdgpu: fix error checking in amdgpu_read_mm_registers for soc15Alex Deucher1-2/+3
Properly skip non-existent registers as well. Bug: https://gitlab.freedesktop.org/drm/amd/-/issues/2442 Reviewed-by: Hawking Zhang <[email protected]> Reviewed-by: Evan Quan <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2022-11-29amdgpu/nv.c: Corrected typo in the video capabilities resolutionVeerabadhran Gopalakrishnan1-12/+12
Corrected the typo in the 4K resolution parameters. Fixes: b3a24461f9fb15 ("amdgpu/nv.c - Added codec query for Beige Goby") Fixes: 9075096b09e590 ("amdgpu/nv.c - Optimize code for video codec support structure") Fixes: 9ac0edaa0f8323 ("drm/amdgpu: add vcn_4_0_0 video codec query") Signed-off-by: Veerabadhran Gopalakrishnan <[email protected]> Acked-by: Luben Tuikov <[email protected]> Reviewed-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2022-10-20drm/amdgpu: fix sdma doorbell init ordering on APUsAlex Deucher1-0/+21
Commit 8795e182b02d ("PCI/portdrv: Don't disable AER reporting in get_port_device_capability()") uncovered a bug in amdgpu that required a reordering of the driver init sequence to avoid accessing a special register on the GPU before it was properly set up leading to an PCI AER error. This reordering uncovered a different hw programming ordering dependency in some APUs where the SDMA doorbells need to be programmed before the GFX doorbells. To fix this, move the SDMA doorbell programming back into the soc15 common code, but use the actual doorbell range values directly rather than the values stored in the ring structure since those will not be initialized at this point. This is a partial revert, but with the doorbell assignment fixed so the proper doorbell index is set before it's used. Fixes: e3163bc8ffdfdb ("drm/amdgpu: move nbio sdma_doorbell_range() into sdma code for vega") Acked-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]> Cc: [email protected] Cc: [email protected]
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