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path: root/drivers/gpu/drm/amd/amdgpu/soc15.c
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2021-11-24drm/amdgpu: Fix MMIO HDP flush on SRIOVFelix Kuehling1-3/+5
Disable HDP register remapping on SRIOV and set rmmio_remap.reg_offset to the fixed address of the VF register for hdp_v*_flush_hdp. Signed-off-by: Felix Kuehling <[email protected]> Tested-by: Bokun Zhang <[email protected]> Reviewed-by: Lijo Lazar <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-10-20drm/amdgpu: drop soc15_set_ip_blocks()Alex Deucher1-179/+0
No longer used since IP enumeration is now driven by amdgpu IP discovery code. Acked-by: Evan Quan <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-10-04drm/amdgpu: convert IP version array to include instancesAlex Deucher1-12/+12
Allow us to query instances versions more cleanly. Instancing support is not consistent unfortunately. SDMA is a good example. Sienna cichlid has 4 total SDMA instances, each enumerated separately (HWIDs 42, 43, 68, 69). Arcturus has 8 total SDMA instances, but they are enumerated as multiple instances of the same HWIDs (4x HWID 42, 4x HWID 43). UMC is another example. On most chips there are multiple instances with the same HWID. This allows us to support both forms. v2: rebase v3: clarify instancing support Reviewed-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-10-04drm/amdgpu/soc15: convert to IP version checkingAlex Deucher1-71/+88
Use IP versions rather than asic_type to differentiate IP version specific features. Acked-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-10-04drm/amdgpu/soc15: get rev_id in soc15_common_early_initAlex Deucher1-1/+1
for consistency with other SoCs. Acked-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-10-04drm/amdgpu/soc15: export common IP functionsAlex Deucher1-1/+1
So they can be driven by IP discovery table. Acked-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-09-23drm/amdgpu: make soc15_common_ip_funcs staticAlex Deucher1-1/+3
It's not used outside of soc15.c Reviewed-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-08-26drm/amdgpu: disable GFX CGCG in aldebaranHawking Zhang1-2/+0
disable GFX CGCG and CGLS to workaround a hardware issue found in aldebaran. Signed-off-by: Hawking Zhang <[email protected]> Reviewed-by: John Clements <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-08-05drm/amdgpu: replace dce_virtual with amdgpu_vkms (v3)Ryan Taylor1-5/+5
Move dce_virtual into amdgpu_vkms and update all references to dce_virtual with amdgpu_vkms. v2: Removed more references to dce_virtual. v3: Restored display modes from previous implementation. Signed-off-by: Ryan Taylor <[email protected]> Reported-by: kernel test robot <[email protected]> Suggested-by: Alex Deucher <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-07-23drm/amd/amdgpu: add consistent PSP FW loading size checkingCandice Li1-2/+2
Signed-off-by: Candice Li <[email protected]> Reviewed-by: John Clements <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-07-16amdgpu/nv.c - Optimize code for video codec support structureVeerabadhran Gopalakrishnan1-154/+22
Optimized the code for codec info structure initialization Signed-off-by: Veerabadhran Gopalakrishnan <[email protected]> Reviewed-by: James Zhu <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-07-01drm/amdgpu: move apu flags initialization to the start of device initHuang Rui1-9/+1
In some asics, we need to adjust the behavior according to the apu flags at very early stage. Signed-off-by: Huang Rui <[email protected]> Reviewed-by: Aaron Liu <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-05-21drm/amdgpu: Modify GC register access from MMIO to RLCG in file soc15.cPeng Ju Zhou1-2/+5
In SRIOV environment, KMD should access GC registers with RLCG if GC indirect access flag enabled. Signed-off-by: Peng Ju Zhou <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-05-19drm/amdgpu: add video_codecs query support for aldebaranJames Zhu1-0/+1
Add video_codecs query support for aldebaran. Signed-off-by: James Zhu <[email protected]> Reviewed-by: Leo Liu <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-05-19drm/amdgpu: disable 3DCGCG on picasso/raven1 to avoid compute hangChangfeng1-2/+0
There is problem with 3DCGCG firmware and it will cause compute test hang on picasso/raven1. It needs to disable 3DCGCG in driver to avoid compute hang. Signed-off-by: Changfeng <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Reviewed-by: Huang Rui <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-05-19drm/amd/pm: enable ASPM by defaultKenneth Feng1-1/+1
Since ASPM function has been stable, we don't need to add the modprobe parameter and we can enable ASPM by default. Signed-off-by: Kenneth Feng <[email protected]> Reviewed-by: Jiansong Chen <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-05-10drm/amdgpu: Rename to ras_*_enabledLuben Tuikov1-3/+3
Rename, ras_hw_supported --> ras_hw_enabled, and ras_features --> ras_enabled, to show that ras_enabled is a subset of ras_hw_enabled, which itself is a subset of the ASIC capability. Cc: Alexander Deucher <[email protected]> Cc: John Clements <[email protected]> Cc: Hawking Zhang <[email protected]> Signed-off-by: Luben Tuikov <[email protected]> Acked-by: Christian König <[email protected]> Reviewed-by: John Clements <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-05-10drm/amdgpu: Remove redundant ras->supportedLuben Tuikov1-3/+4
Remove redundant ras->supported, as this value is also stored in adev->ras_features. Use adev->ras_features, as that supercedes "ras", since the latter is its member. The dependency goes like this: ras <== adev->ras_features <== hw_supported, and is read as "ras depends on ras_features, which depends on hw_supported." The arrows show the flow of information, i.e. the dependency update. "hw_supported" should also live in "adev". Cc: Alexander Deucher <[email protected]> Cc: John Clements <[email protected]> Cc: Hawking Zhang <[email protected]> Signed-off-by: Luben Tuikov <[email protected]> Acked-by: Christian König <[email protected]> Reviewed-by: John Clements <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-05-10drm/amdgpu: set vcn mgcg flag for picassoSathishkumar S1-1/+2
enable vcn mgcg flag for picasso. Signed-off-by: Sathishkumar S <[email protected]> Reviewed-by: Leo Liu <[email protected]> Acked-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-05-10drm/amdgpu: enable ras error count query and reset for HDPHawking Zhang1-3/+0
add hdp block ras error query and reset support in amdgpu ras error count query and reset interface Signed-off-by: Hawking Zhang <[email protected]> Reviewed-by: John Clements <[email protected]> Reviewed-by: Dennis Li <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-04-15drm/amd/amdgpu: enable ASPM on vegaKenneth Feng1-3/+4
enable ASPM on vega to save the power without the performance hurt. Signed-off-by: Kenneth Feng <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-04-09drm/amdgpu: split nbio callbacks into ras and non-ras onesHawking Zhang1-5/+10
nbio ras is not managed by gpu driver when gpu is connected to cpu through xgmi. split nbio callbacks into ras and non-ras ones so gpu driver only initializes nbio ras callbacks when it manages nbio ras. Signed-off-by: Hawking Zhang <[email protected]> Reviewed-by: Dennis Li <[email protected]> Reviewed-by: John Clements <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-04-09drm/amd/pm: label these APIs used internally as staticEvan Quan1-1/+0
Also drop unnecessary header file and declarations. Signed-off-by: Evan Quan <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-04-09drm/amdgpu: Enable VCN/JPEG CG on aldebaranLijo Lazar1-2/+2
Enable clockgating for VCN and JPEG blocks on aldebaran Signed-off-by: Lijo Lazar <[email protected]> Reviewed-by: Hawking Zhang <[email protected]> Acked-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-03-23drm/amdgpu: Add clock gating support for aldebaranLijo Lazar1-9/+22
Aldebaran clock gating support for GFX,SDMA,IH blocks VCN/JPEG blocks are excluded in this patch, to be enabled later Signed-off-by: Lijo Lazar <[email protected]> Acked-by: Feifei Xu <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-03-23drm/amdgpu: enable vcn dpg mode on aldebaranJames Zhu1-1/+1
Enable vcn dpg mode on aldebaran Signed-off-by: James Zhu <[email protected]> Reviewed-by: Leo Liu <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-03-23drm/amdgpu: enable vcn and jpeg on aldebaranJames Zhu1-2/+2
Enable vcn and jpeg 2.6 on aldebaran. Signed-off-by: James Zhu <[email protected]> Reviewed-by: Leo Liu <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-03-23drm/amdgpu: Enable swsmu block on aldebaranLijo Lazar1-0/+1
Enable smu13 block on aldebaran Signed-off-by: Lijo Lazar <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-03-23drm/amdgpu: switch to vega20 ih block for aldebaranHawking Zhang1-2/+2
replace vega10 ih block with vega20 ih block for aldebaran. Signed-off-by: Hawking Zhang <[email protected]> Acked-by: Christian König <[email protected]> Acked-by: Felix Kuehling <[email protected]> Reviewed-by: Dennis Li <[email protected]> Reviewed-by: Feifei Xu <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-03-23drm/amdgpu:add smu mode1/2 support for aldebaranFeifei Xu1-37/+19
Use MSG_GfxDriverReset for mode reset and retire MSG_Mode1Reset. Centralize soc15_asic_mode1_reset() and nv_asic_mode1_reset()functions. Add mode2_reset_is_support() for smu->ppt_funcs. Signed-off-by: Feifei Xu <[email protected]> Reviewed-by: Hawking Zhang <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-03-23drm/amdgpu: initialize external rev_id for aldebaranHawking Zhang1-0/+1
add exteranal rev_id for aldebaran Signed-off-by: Hawking Zhang <[email protected]> Reviewed-by: Kevin Wang <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-03-23drm/amdgpu: comments out vcn/jpeg ip blocks for aldebaranHawking Zhang1-2/+2
vcn fw front door loading is not functional. comments out vcn/jpeg ip blocks so people can load amdgpu driver without specify ip_mask module parameter. Signed-off-by: Hawking Zhang <[email protected]> Reviewed-by: Kevin Wang <[email protected]> Reviewed-by: James Zhu <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-03-23drm/amdgpu/jpeg: enable JPEG on aldebaranJames Zhu1-0/+1
enable JPEG on aldebaran Signed-off-by: James Zhu <[email protected]> Reviewed-by: Leo Liu <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-03-23drm/amdgpu/vcn: enable VCN on aldebaranJames Zhu1-0/+2
Enable VCN on aldebaran Signed-off-by: James Zhu <[email protected]> Reviewed-by: Leo Liu <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-03-23drm/amdgpu: define address map for host xgmi link (v3)Rajneesh Bhardwaj1-5/+0
This applies to AMD Accelerated Processing Platforms that support host gpu interconnect throguh a special link (xgmi). Aldebaran systems will support this special feature for utilizing the benefits of host-gpu cache coherence. This change outlines the basic framework for mapping the GPU VRAM (HBM) to system address space making it accesible to the host but managed by the amdgpu driver since this region is marked as reserved memory in host address space by the underlying system firmware. v2: switch to smuio callback function to check the type of host-gpu interface (Hawking) v3: use hub callbacks rather than direct function calls (Alex) Reviewed-by: Oak Zeng <[email protected]> Reviewed-by: Hawking Zhang <[email protected]> Signed-off-by: Rajneesh Bhardwaj <[email protected]> Signed-off-by: Hawking Zhang <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-03-23drm/amdgpu: enable xgmi support for AldebaranRajneesh Bhardwaj1-1/+3
Like its predecessors Aldebran also supports advanced high bandwidth GPU-GPU communication interface known as xgmi. This enables the basic xgmi support while refactoring the code slightly. Detection of xgmi link between host cpu and gpu will be introduced in a different patch. Reviewed-by: Oak Zeng <[email protected]> Reviewed-by: Christian König <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Reviewed-by: Hawking Zhang <[email protected]> Signed-off-by: Rajneesh Bhardwaj <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-03-23drm/amdgpu: initialize smuio callbacks for aldebaranHawking Zhang1-0/+3
initialize smuio v13_0 callbacks for aldebaran Signed-off-by: Hawking Zhang <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-03-23drm/amdgpu: enable psp v13 ip block for aldebaranHawking Zhang1-1/+11
Add psp v13 ip block to soc ip init list for aldebaran Signed-off-by: Hawking Zhang <[email protected]> Reviewed-by: Le Ma <[email protected]> Reviewed-by: Kevin Wang <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-03-10drm/amdgpu: add soc15 common ip block support for aldebaranLe Ma1-2/+17
Initialize aldebaran common ip block Signed-off-by: Le Ma <[email protected]> Reviewed-by: Hawking Zhang <[email protected]> Acked-by: Evan Quan <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-03-10drm/amdgpu: add register base init for aldebaran (v2)Le Ma1-0/+3
v1: add aldebaran_reg_base_init function to initialize register base for aldebaran (Le) v2: update VCN HWIP and initialize base offset (James) Signed-off-by: Le Ma <[email protected]> Signed-off-by: James Zhu <[email protected]> Reviewed-by: Hawking Zhang <[email protected]> Reviewed-by: Leo Liu <[email protected]> Acked-by: Evan Quan <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-02-26drm/amdgpu/codec: drop the internal codec indexAlex Deucher1-22/+24
And just use the ioctl index. They are the same. Reviewed-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-02-26drm/amdgpu: add video decode/encode cap tables and asic callbacks (v3)Alex Deucher1-0/+230
For each asic family. Will be used to populate tables for the new INFO ioctl query. v2: add max_pixels_per_frame to handle the portrait case v3: fix copy paste typos Reviewed-by: Christian König <[email protected]> Reviewed-by: Leo Liu <[email protected]> (v1) Signed-off-by: Alex Deucher <[email protected]>
2021-02-18drm/amdgpu: Set reference clock to 100Mhz on Renoir (v2)Alex Deucher1-0/+2
Fixes the rlc reference clock used for GPU timestamps. Value is 100Mhz. Confirmed with hardware team. v2: reword commit message. Bug: https://gitlab.freedesktop.org/drm/amd/-/issues/1480 Acked-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]> Cc: [email protected]
2021-02-09drm/amdgpu/soc15: add PCI reset supportAlex Deucher1-10/+14
Use generic PCI reset for GPU reset if the user specifies PCI reset as the reset mechanism. This should in general only be used for validation. Acked-by: Evan Quan <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-01-13drm/amdgpu: add new device id for Reniormengwang1-1/+2
add DID 0x164C into pciidlist under CHIP_RENOIR family. Signed-off-by: mengwang <[email protected]> Reviewed-by: Huang Rui <[email protected]> Signed-off-by: Alex Deucher <[email protected]> Cc: [email protected] # 5.10.x
2021-01-05drm/amdgpu: switch hdp callback functions for hdp v4Likun Gao1-83/+8
Switch to use the HDP functions which unified on hdp structure instead of the scattered hdp callback functions. V2: clean up hdp reset ras error count function. Signed-off-by: Likun Gao <[email protected]> Reviewed-by: Hawking Zhang <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-12-23drm/amdgpu: switch to vega20 ih block for vega20/arcturusHawking Zhang1-4/+5
replace navi10 ih block with vega20 ih block for vega20 and arcturus Signed-off-by: Hawking Zhang <[email protected]> Acked-by: Christian König <[email protected]> Acked-by: Felix Kuehling <[email protected]> Reviewed-by: Dennis Li <[email protected]> Reviewed-by: Feifei Xu <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-11-13drm/amdgpu: disable rom clock gating support for APUsHawking Zhang1-4/+0
ROM clock gating enable/disable is not supported on APU platform. (i.e. CGTT_ROM_CLK_CTRL0 register is not availabe on APU). SMUIO callbacks will check APU flag before enable/disable rom clock gating, and skip the programming. Accordingly, query clock gating status through CGTT_ROM_CLK_CTRL0 also doesn't support on APU platform. The change applies to RAVEN/RAVEN2/PICASSO/RENOIR. Signed-off-by: Hawking Zhang <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Reviewed-by: John Clements <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-11-13drm/amdgpu: switch to use smuio callbacks for AI familyHawking Zhang1-43/+14
Switch to smuio callbacks: use smuio v9_0 callbacks for Vega10/12, smuio v11_0 callbacks for Vega20/Arcturus. APUs don't support enable/disable rom clock gating and also don't support read bios from rom. So APU flag check is needed in clock gating callbacks and asic funciton for read bios from rom to prevent access unknown offset on APU. Signed-off-by: Hawking Zhang <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Reviewed-by: John Clements <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-11-02drm/amdgpu: improve code indentation and alignmentDeepak R Varma1-1/+1
General code indentation and alignment changes such as replace spaces by tabs or align function arguments as per the coding style guidelines. The patch covers various .c files for this driver. Issue reported by checkpatch script. Signed-off-by: Deepak R Varma <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
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