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The KFD VMID assignment was hard-coded in a few places. Consolidate that in
a single variable adev->vm_manager.first_kfd_vmid. The value is still
assigned in gmc-ip-version-specific code.
Signed-off-by: Felix Kuehling <[email protected]>
Reviewed-by: Christian König <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>
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Port functionality from the Radeon driver to support
VCE clock control.
Signed-off-by: Alex Jivin <[email protected]>
Reviewed-by: Alex Deucher <[email protected]>
Acked-by: Christian König <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>
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Port functionality from the Radeon driver to support
UVD clock control.
Signed-off-by: Alex Jivin <[email protected]>
Reviewed-by: Alex Deucher <[email protected]>
Acked-by: Christian König <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>
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Fix packet_type0 definition in sid.
Signed-off-by: Sonny Jiang <[email protected]>
Reviewed-by: Alex Deucher <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>
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drop the duplicate register macros from sid.h and use the
standard ones in the oss register headers.
Acked-by: Christian König <[email protected]>
Reviewed-by: Hawking Zhang <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>
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Add support for DRM_FORMAT_{A,X}BGR8888 in amdgpu with amd dc disabled
(v2) Crossbar registers are defined and used to swap red and blue channels,
keeping the existing coding style in each of the dce modules.
After setting crossbar bits in fb_swap, use bitwise OR for big endian
where required in DCE6 and DCE8 which do not rely on REG_SET_FIELD()
Signed-off-by: Mauro Rossi <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>
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Move these to the amdgpu directory to match what we
do for other asics.
Acked-by: Christian König <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>
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