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path: root/drivers/gpu/drm/amd/amdgpu/nv.c
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2021-12-01drm/amdgpu/sriov/vcn: add new vcn ip revision check case for SIENNA_CICHLIDJane Jian1-0/+1
[WHY] for sriov odd# vf will modify vcn0 engine ip revision(due to multimedia bandwidth feature), which will be mismatched with original vcn0 revision [HOW] add new version check for vcn0 disabled revision(3, 0, 192), typically modified under sriov mode Signed-off-by: Jane Jian <[email protected]> Reviewed-by: Guchun Chen <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-11-24drm/amdgpu: Fix MMIO HDP flush on SRIOVFelix Kuehling1-3/+5
Disable HDP register remapping on SRIOV and set rmmio_remap.reg_offset to the fixed address of the VF register for hdp_v*_flush_hdp. Signed-off-by: Felix Kuehling <[email protected]> Tested-by: Bokun Zhang <[email protected]> Reviewed-by: Lijo Lazar <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-11-10drm/amdgpu: add missed support for UVD IP_VERSION(3, 0, 64)Guchun Chen1-0/+1
Fixes: 96b8dd4423e74d ("drm/amdgpu/amdgpu_vcn: convert to IP version checking") Signed-off-by: Flora Cui <[email protected]> Signed-off-by: Guchun Chen <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-10-20drm/amdgpu: drop nv_set_ip_blocks()Alex Deucher1-293/+0
No longer used since IP enumeration is now driven by amdgpu IP discovery code. Acked-by: Evan Quan <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-10-20drm/amdgpu: support B0&B1 external revision id for yellow carpAaron Liu1-1/+1
B0 internal rev_id is 0x01, B1 internal rev_id is 0x02. The external rev_id for B0 and B1 is 0x20. The original expression is not suitable for B1. v2: squash in fix for display code (Alex) Signed-off-by: Aaron Liu <[email protected]> Reviewed-by: Huang Rui <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-10-04drm/amdgpu: convert IP version array to include instancesAlex Deucher1-4/+4
Allow us to query instances versions more cleanly. Instancing support is not consistent unfortunately. SDMA is a good example. Sienna cichlid has 4 total SDMA instances, each enumerated separately (HWIDs 42, 43, 68, 69). Arcturus has 8 total SDMA instances, but they are enumerated as multiple instances of the same HWIDs (4x HWID 42, 4x HWID 43). UMC is another example. On most chips there are multiple instances with the same HWID. This allows us to support both forms. v2: rebase v3: clarify instancing support Reviewed-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-10-04drm/amdgpu/nv: convert to IP version checkingAlex Deucher1-37/+38
Use IP versions rather than asic_type to differentiate IP version specific features. Acked-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-10-04drm/amdgpu/nv: export common IP functionsAlex Deucher1-1/+1
So they can be driven by IP dicovery table. Reviewed-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-10-04drm/amdgpu: move headless sku check into harvest functionAlex Deucher1-14/+0
Consolidate harvesting information. Reviewed-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-10-04drm/amd/display: add cyan_skillfish display supportZhan Liu1-0/+4
[Why] add display related cyan_skillfish files in. makefile controlled by CONFIG_DRM_AMD_DC_DCN201 flag. v2: squash in clang fixes from Harry, Nathan v3: squash in missing CONFIG_DRM_AMD_DC check (Alex) Signed-off-by: Charlene Liu <[email protected]> Signed-off-by: Zhan Liu <[email protected]> Reviewed-by: Charlene Liu <[email protected]> Acked-by: Jun Lei <[email protected]> Acked-by: Harry Wentland <[email protected]> Acked-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-08-05drm/amdgpu: replace dce_virtual with amdgpu_vkms (v3)Ryan Taylor1-11/+11
Move dce_virtual into amdgpu_vkms and update all references to dce_virtual with amdgpu_vkms. v2: Removed more references to dce_virtual. v3: Restored display modes from previous implementation. Signed-off-by: Ryan Taylor <[email protected]> Reported-by: kernel test robot <[email protected]> Suggested-by: Alex Deucher <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-07-23drm/amdgpu: enable SMU for cyan_skilfishLang Yu1-8/+9
Enable SMU support for cyan_skilfish. v2: Squash in fix (Alex) Signed-off-by: Lang Yu <[email protected]> Reviewed-by: Huang Rui <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-07-23drm/amdgpu: enable psp v11.0.8 for cyan_skillfishLang Yu1-0/+4
Add psp v11.0.8 to ip block initialization. v2: use APU flags (Alex) Signed-off-by: Lang Yu <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-07-23drm/amdgpu: add nbio support for cyan_skillfishTao Zhou1-1/+4
nbio version is 2.3. v2: Make it more explicit (Alex) Signed-off-by: Tao Zhou <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-07-23drm/amdgpu: add chip early init for cyan_skillfishTao Zhou1-0/+5
Set cg/pg flags and rev id for cyan_skillfish. Signed-off-by: Tao Zhou <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-07-23drm/amdgpu: set ip blocks for cyan_skillfishTao Zhou1-0/+9
Add ip blocks for cyan_skillfish. Signed-off-by: Tao Zhou <[email protected]> Reviewed-by: Hawking Zhang <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-07-23drm/amdgpu: dynamic initialize ip offset for cyan_skillfishTao Zhou1-0/+3
Add ip offset definition for cyan_skillfish and initialize it. v2: squash in ip_offset updates (Alex) Signed-off-by: Tao Zhou <[email protected]> Reviewed-by: Hawking Zhang <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-07-23drm/amdgpu: update yellow carp external rev_id handlingAaron Liu1-1/+4
0x1681 has a different external revision id. Signed-off-by: Aaron Liu <[email protected]> Reviewed-by: Huang Rui <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-07-23drm/amdgpu - Corrected the video codecs array name for yellow carpVeerabadhran Gopalakrishnan1-2/+2
Signed-off-by: Veerabadhran Gopalakrishnan <[email protected]> Reviewed-by: James Zhu <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-07-16amdgpu/nv.c - Optimize code for video codec support structureVeerabadhran Gopalakrishnan1-196/+27
Optimized the code for codec info structure initialization Signed-off-by: Veerabadhran Gopalakrishnan <[email protected]> Reviewed-by: James Zhu <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-07-16amdgpu/nv.c - Added video codec support for Yellow CarpVeerabadhran Gopalakrishnan1-1/+19
Added the supported codecs in the video capabilities query. Signed-off-by: Veerabadhran Gopalakrishnan <[email protected]> Reviewed-by: James Zhu <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-07-01drm/amdgpu: move apu flags initialization to the start of device initHuang Rui1-1/+0
In some asics, we need to adjust the behavior according to the apu flags at very early stage. Signed-off-by: Huang Rui <[email protected]> Reviewed-by: Aaron Liu <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-06-30amdgpu/nv.c - Added codec query for Beige GobyVeerabadhran Gopalakrishnan1-0/+30
Added the Beige Goby capabilities in codec query. v2: fix build error and indent (James) Signed-off-by: Veerabadhran Gopalakrishnan <[email protected]> Reviewed-by: James Zhu <[email protected]> Reviewed-by: Leo Liu <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-06-30drm/amdgpu: fix the hang caused by PCIe link width switchEvan Quan1-0/+3
SMU had set all the necessary fields for a link width switch but the width switch wasn't occurring because the link was idle in the L1 state. Setting LC_L1_RECONFIG_EN=0x1 will allow width switches to also be initiated while in L1 instead of waiting until the link is back in L0. Signed-off-by: Evan Quan <[email protected]> Reviewed-by: Lijo Lazar <[email protected]> Signed-off-by: Alex Deucher <[email protected]> Cc: [email protected]
2021-06-30drm/amdgpu: fix NAK-G generation during PCI-e link width switchEvan Quan1-0/+3
A lot of NAK-G being generated when link widht switching is happening. WA for this issue is to program the SPC to 4 symbols per clock during bootup when the native PCIE width is x4. Signed-off-by: Evan Quan <[email protected]> Reviewed-by: Lijo Lazar <[email protected]> Signed-off-by: Alex Deucher <[email protected]> Cc: [email protected]
2021-06-04drm/amdgpu: Add DC support and display block for Yellow CarpNicholas Kazlauskas1-1/+6
To enable output on real display instead of virtual. Acked-by: Huang Rui <[email protected]> Signed-off-by: Nicholas Kazlauskas <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-06-04drm/amdgpu: add video_codecs query support for yellow carpJames Zhu1-0/+1
Add video_codecs query support for yellow carp. Acked-by: Huang Rui <[email protected]> Signed-off-by: James Zhu <[email protected]> Acked-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-06-04drm/amdgpu: add mode2 reset support for yellow carpAaron Liu1-0/+1
This patch adds mode2 reset support for yellow carp. Signed-off-by: Aaron Liu <[email protected]> Reviewed-by: Huang Rui <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-06-04drm/amdgpu: enable VCN PG and CG for yellow carpAaron Liu1-2/+6
Enable VCN 3.0 PG and CG for Yellow Carp by setting up flags. Acked-by: Huang Rui <[email protected]> Signed-off-by: Aaron Liu <[email protected]> Reviewed-by: James Zhu <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-06-04drm/amdgpu: enable vcn dpg mode on yellow carpJames Zhu1-1/+2
Enable vcn dpg mode on yellow carp. Signed-off-by: James Zhu <[email protected]> Reviewed-by: Leo Liu <[email protected]> Reviewed-by: Aaron Liu <[email protected]> Acked-by: Huang Rui <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-06-04drm/amdgpu: enable vcn/jpeg on yellow carpJames Zhu1-0/+3
Enable vcn/jpeg IP on yellow carp. Signed-off-by: James Zhu <[email protected]> Reviewed-by: Leo Liu <[email protected]> Reviewed-by: Aaron Liu <[email protected]> Acked-by: Huang Rui <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-06-04drm/amdgpu: add IH Clock Gating support for yellow carpAaron Liu1-1/+2
IH CG need to be enabled by driver. Signed-off-by: Aaron Liu <[email protected]> Reviewed-by: Huang Rui <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-06-04drm/amdgpu: add ATHUB Clock Gating support for yellow carpAaron Liu1-1/+3
ATHUB MGCG/MGLS is enabled by default. Adding ATHUB MGCG/MGLS flag to ensure athub mgcg/ls enabled. Signed-off-by: Aaron Liu <[email protected]> Reviewed-by: Huang Rui <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-06-04drm/amdgpu: add HDP Clock Gating support for yellow carpAaron Liu1-1/+3
HDP MGCG is enabled by default. Adding AMD_CG_SUPPORT_HDP_MGCG to ensure hdp mgcg enabled. HDP MGLS need to be enabled by driver. Signed-off-by: Aaron Liu <[email protected]> Reviewed-by: Huang Rui <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-06-04drm/amdgpu: add SDMA Clock Gating support for yellow carpAaron Liu1-1/+2
Add AMD_CG_SUPPORT_SDMA_LS support. SDMA MGCG programming is migrated to RLC. Signed-off-by: Aaron Liu <[email protected]> Reviewed-by: Huang Rui <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-06-04drm/amdgpu: add GFX Power Gating support for yellow carpAaron Liu1-1/+1
Add GFX Power Gating support. Signed-off-by: Aaron Liu <[email protected]> Reviewed-by: Huang Rui <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-06-04drm/amdgpu: add MMHUB Clock Gating support for yellow carpAaron Liu1-1/+3
Add AMD_CG_SUPPORT_MC_MGCG/AMD_CG_SUPPORT_MC_LS support. Signed-off-by: Aaron Liu <[email protected]> Reviewed-by: Huang Rui <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-06-04drm/amdgpu: add GFX Clock Gating support for yellow carpAaron Liu1-1/+9
Add below supports: GFX Coarse Grain Clock Gating(CGCG) GFX Coarse grain light sleep/deep sleep(CGLS) GFX Medium Grain Clock Gating(MGCG) GFX Medium Grain light sleep/deep sleep(MGLS) GFX Fine Grain Clock Gating(FGCG) RLC MGLS CP MGLS Signed-off-by: Aaron Liu <[email protected]> Reviewed-by: Huang Rui <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-06-04drm/amdgpu: enable psp_v13 for yellow carpAaron Liu1-0/+2
This patch enables psp_v13 for yellow carp. Signed-off-by: Aaron Liu <[email protected]> Reviewed-by: Huang Rui <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-06-04drm/amdgpu: add smu ip block for yellow carp(V3)Aaron Liu1-0/+1
Yellow carp smu ip version: 13_0_1. V2: rename smu_v13_0 to smu_v13_0_1. V3: reuse smu_v13_0 with aldebaran. Signed-off-by: Aaron Liu <[email protected]> Acked-by: Alex Deucher <[email protected]> Reviewed-by: Huang Rui <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-06-04drm/amdgpu: set ip blocks for yellow carpAaron Liu1-0/+9
Enable ip blocks for yellow carp. Signed-off-by: Aaron Liu <[email protected]> Reviewed-by: Huang Rui <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-06-04drm/amdgpu: add nv common ip block support for yellow carpAaron Liu1-0/+8
This patch adds common ip support for yellow carp. Signed-off-by: Aaron Liu <[email protected]> Reviewed-by: Huang Rui <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-05-25drm/amdgpu: Change IP init sequence to support PSP program IH_RB_CNTL on ↵Peng Ju Zhou1-2/+7
NV12 SRIOV To enable PSP program IH_RB_CNTL, the PSP IP should be initialized before IH IP, otherwise, it will hit psp NULL pointer. Signed-off-by: Peng Ju Zhou <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-05-21drm/amdgpu: Modify GC register access from MMIO to RLCG in file nv.cPeng Ju Zhou1-1/+1
In SRIOV environment, KMD should access GC registers with RLCG if GC indirect access flag enabled. Signed-off-by: Peng Ju Zhou <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-05-19drm/amd/amdgpu: psp program IH_RB_CTRL on sienna_cichlidYuBiao Wang1-3/+9
[Why] IH_RB_CNTL is blocked by PSP so we need to ask psp to help config it. [How] Move psp ip block before ih, and use psp to program IH_RB_CNTL under sriov. Reviewed-by: Chen, Horace <[email protected]> Signed-off-by: YuBiao Wang <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-05-19drm/amd/amdgpu: Enable DCN IP init for Beige GobyAurabindo Pillai1-0/+4
[Why&How] Adds DCN IP block initialization for Beige Goby Signed-off-by: Aurabindo Pillai <[email protected]> Acked-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-05-19drm/amdgpu: add cgls for beige_gobyTao Zhou1-0/+1
Enable cgls to improve the runtime power efficiency. Signed-off-by: Tao Zhou <[email protected]> Reviewed-by: Jack Gui <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-05-19drm/amdgpu: enabled VCN3.0 CG for BEIGE GOBYVeerabadhran Gopalakrishnan1-1/+2
Enable VCN CG for BEIGE GOBY Signed-off-by: Veerabadhran Gopalakrishnan <[email protected]> Reviewed-by: Leo Liu <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-05-19drm/amdgpu: enable ih CG for beige_gobyTao Zhou1-1/+2
Enable ih clock gating for beige_goby. Signed-off-by: Tao Zhou <[email protected]> Reviewed-by: Jiansong Chen <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-05-19drm/amdgpu: enable hdp CG and LS for beige_gobyTao Zhou1-1/+3
Enable hdp MGCG and LS for beige_goby. Signed-off-by: Tao Zhou <[email protected]> Reviewed-by: Jiansong Chen <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
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