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path: root/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c
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2017-11-08drm/amdgpu: use irq-safe lock for kiq->ring_lockpding1-4/+6
This lock is used during register accessing in SRIOV guest. The register accessing could happen both in irq enabled and irq disabled cases. Always use irq-safe lock. Signed-off-by: Pixel Ding <[email protected]> Reviewed-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-11-03drm/amdgpu/virt: don't dereference undefined 'module' structArnd Bergmann1-0/+2
Accessing the THIS_MODULE directly is only possible when modules are enabled, otherwise we get a build failure: drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c: In function 'amdgpu_virt_init_data_exchange': drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c:331:20: error: dereferencing pointer to incomplete type 'struct module' Further, THIS_MODULE is NULL when the driver is built-in, so the code would likely cause a NULL pointer dereference. This adds an #ifdef check to avoid the compile-time error, plus a NULL pointer check before dereferencing THIS_MODULE. It might be better to find a way to avoid using the module version altogether. Fixes: 2dc8f81e4f82 ("drm/amdgpu: SR-IOV data exchange between PF&VF") Signed-off-by: Arnd Bergmann <[email protected]> Signed-off-by: Alex Deucher <[email protected]> Reviewed-by: Harry Wentland <[email protected]> Reviewed-By: Xiangliang Yu <[email protected]>
2017-10-19drm/amdgpu: busywait KIQ register accessing (v4)pding1-17/+13
Register accessing is performed when IRQ is disabled. Never sleep in this function. Known issue: dead sleep in many use cases of index/data registers. v2: - wrap polling fence functions. - don't trigger IRQ for polling in case of wrongly fence signal. v3: - handle wrap round gracefully. - add comments for polling function v4: - don't return negative timeout confused with error code Signed-off-by: pding <[email protected]> Reviewed-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-10-19drm/amdgpu: SR-IOV data exchange between PF&VFHorace Chen1-0/+75
SR-IOV need to exchange some data between PF&VF through shared VRAM PF will copy some necessary firmware and information to the shared VRAM. It also requires some information from VF. PF will send a key through mailbox2 to help guest calculate checksum so that it can verify whether the data is correct. So check the data on the specified offset of the shared VRAM, if the checksum is right, read values from it and write some VF information next to the data from PF. Signed-off-by: Horace Chen <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-08-17drm/amdgpu: separate bo_va structureChristian König1-1/+1
Split that into vm_bo_base and bo_va to allow other uses as well. Signed-off-by: Christian König <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-08-17drm/amdgpu: cleanup static CSA handlingChristian König1-13/+12
Move the CSA bo_va from the VM to the fpriv structure. Signed-off-by: Christian König <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-05-24drm/amdgpu:kiq reg access need timeout(v2)Monk Liu1-5/+8
this is to prevent fence forever waiting if FLR occured during register accessing. v2: use define instead of hardcode for the timeout msec Signed-off-by: Monk Liu <[email protected]> Reviewed-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-05-24drm/amdgpu: Move kiq ring lock out of virt structureShaoyun Liu1-5/+4
The usage of kiq should not depend on the virtualization. Signed-off-by: Shaoyun Liu <[email protected]> Reviewed-by:Andres Rodriquez <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-05-24drm/amdgpu/virt: bypass cg and pg setting for SRIOVXiangliang Yu1-0/+2
GPU hypervisor cover all settings of CG and PG, so guest doesn't need to do anything. Bypass it. Signed-off-by: Frank Min <[email protected]> Signed-off-by: Xiangliang Yu <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-04-28drm/amdgpu/virt: add two functions for MM tableXiangliang Yu1-0/+46
Add two functions to allocate & free MM table memory. Signed-off-by: Xiangliang Yu <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-04-06drm/amdgpu:no need to involv HDP in KIQMonk Liu1-4/+0
1,KIQ won't touch VRAM so no need to involv HDP flush/invalidate at all. 2,According to CP hw designer KIQ better not use any PM4 package lead to wait behave. Signed-off-by: Monk Liu <[email protected]> Reviewed-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-03-29drm/amdgpu: separate page table allocation from mappingChristian König1-0/+9
This makes it easier to implement a replace operation. Signed-off-by: Christian König <[email protected]> Reviewed-by: Junwei Zhang <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-03-29drm/amdgpu:add lock_reset for SRIOVMonk Liu1-0/+1
this lock is used for sriov_gpu_reset, only get this mutex can run into sriov_gpu_reset. we have couple source triggers gpu_reset for SRIOV: 1) submit timedout and trigger reset voluntarily 2) invalid instruction detected by ENGINE and trigger reset voluntarily 2) hypervisor found world switch hang and trigger flr and notify guest to do reset. all need take care and we need a mutex to protect the consistency of reset routine. Signed-off-by: Monk Liu <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-03-29drm/amdgpu:change kiq lock nameMonk Liu1-5/+5
Signed-off-by: Monk Liu <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-02-08drm/amdgpu/virt: fix double kfree on bo_vaColin Ian King1-1/+0
bo_va is being kfree'd twice, once in the call to amdgpu_vm_bo_rmv and then a short while later. Fix this double free by removing the 2nd kfree. Detected by CoverityScan, CID#1399524 ("Double Free") Reviewed-by: Monk Liu <[email protected]> Signed-off-by: Colin Ian King <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-01-27drm/amdgpu/virt: enable virtual displayXiangliang Yu1-0/+4
Virtual display is default setting for virtualization, enable it. Signed-off-by: Xiangliang Yu <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Acked-by: Christian König <[email protected]> Reviewed-by: Monk Liu <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-01-27drm/amdgpu/virt: add high level interfaces for virtXiangliang Yu1-0/+67
Add high level interfaces that is not relate to specific asic. So asic files just need to implement the interfaces to support virtualization. Signed-off-by: Xiangliang Yu <[email protected]> Signed-off-by: Monk Liu <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Reviewed-by: Christian König <[email protected]> Reviewed-by: Monk Liu <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-01-27drm/amdgpu/virt: use kiq to access registers (v2)Xiangliang Yu1-0/+58
For virtualization, it is must for driver to use KIQ to access registers when it is out of GPU full access mode. v2: agd: rebase Signed-off-by: Xiangliang Yu <[email protected]> Signed-off-by: Monk Liu <[email protected]> Reviewed-by: Monk Liu <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-01-27drm/amdgpu:add new file for SRIOVMonk Liu1-0/+93
for SRIOV usage, CSA is only used per device and each VM will map on it. Signed-off-by: Monk Liu <[email protected]> Reviewed-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
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