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In Tonga's virtualization environment, for firmware UCODE_ID_STORAGE,
there is no actual firmware data, but we still need alloc a BO and
tell the BO's mc address to HW, or world switch will hang on VFs.
v2: fix coding style (Alex)
Signed-off-by: Trigger Huang <[email protected]>
Reviewed-by: Xiangliang Yu <[email protected]>
Reviewed-by: Monk Liu <[email protected]>
Acked-by: Huang Rui <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>
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Handle ucode differences in vega10.
Acked-by: Christian König <[email protected]>
Signed-off-by: Huang Rui <[email protected]>
Reviewed-by: Alex Deucher <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>
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This patch introduces a new flag named "amdgpu_firmware_load_type" to
handle different firmware loading method. Since Vega10, there are
three ways to load firmware. It would be better to use a flag and a
fw_load_type kernel parameter to configure it.
Acked-by: Christian König <[email protected]>
Signed-off-by: Huang Rui <[email protected]>
Reviewed-by: Alex Deucher <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>
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This will be used for newer asics.
Acked-by: Christian König <[email protected]>
Signed-off-by: Huang Rui <[email protected]>
Reviewed-by: Alex Deucher <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>
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we found some MEC ucode leads to IB test fail or even
ring test fail if Jump Table of it is not start in
FW bo with page aligned address, fixed by always make
JT address page aligned.
we don't need to patch JT2 for MEC2, because for VI,
MEC2 is a copy of MEC1, thus when converting fw_type
for MEC_JT2 we just return MEC1,hw can use the same
JT for both MEC1 & MEC2.
above two change fixed some ring/ib test failure issue
for some version of MEC ucode.
Signed-off-by: Frank Min <[email protected]>
Signed-off-by: Monk Liu <[email protected]>
Reviewed-by: Alex Deucher <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>
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for sriov, SMC need MEC_STORAGE reserved in fw bo.
Signed-off-by: Monk Liu <[email protected]>
Signed-off-by: Frank Min <[email protected]>
Reviewed-by: Alex Deucher <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>
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for GTT memory SMC can only access it within PF space, which is not
used for SRIOV case, thus for SRIOV case, we let SMC use FB space for
ucode bo.
Signed-off-by: Frank Min <[email protected]>
Reviewed-by: Alex Deucher <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>
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Signed-off-by: Huang Rui <[email protected]>
Reviewed-by: Alex Deucher <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>
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Clean up the codes to move the release handles into fail labels.
v2: squash in Christian's regression fix
Signed-off-by: Huang Rui <[email protected]>
Reviewed-by: Chunming Zhou <[email protected]>
Reviewed-by: Christian König <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>
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Adds an extra argument to amdgpu_bo_create, which is only used in amdgpu_prime.c.
Port of radeon commit 831b6966a60fe72d85ae3576056b4e4e0775b112.
v2: fix up kfd.
Signed-off-by: Christian König <[email protected]>
Reviewed-by: Jammy Zhou <[email protected]>
Reviewed-by: Alex Deucher <[email protected]>
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This adds the non-asic specific core driver code.
v2: remove extra kconfig option
v3: implement minor fixes from Fengguang Wu
v4: fix cast in amdgpu_ucode.c
Acked-by: Christian König <[email protected]>
Acked-by: Jammy Zhou <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>
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