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Please revert this patch when psp load fw is enabled.
Acked-by: Christian König <[email protected]>
Signed-off-by: Feifei Xu <[email protected]>
Reviewed-by: Hawking Zhang <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>
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The same as vega10.
Reviewed-by: Christian König <[email protected]>
Signed-off-by: Feifei Xu <[email protected]>
Reviewed-by: Alex Deucher <[email protected]>
Reviewed-by: Hawking Zhang <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>
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into drm-next
Main changes for 4.18. I'd like to do a separate pull for vega20 later
this week or next. Highlights:
- Reserve pre-OS scanout buffer during init for seemless transition from
console to driver
- VEGAM support
- Improved GPU scheduler documentation
- Initial gfxoff support for raven
- SR-IOV fixes
- Default to non-AGP on PowerPC for radeon
- Fine grained clock voltage control for vega10
- Power profiles for vega10
- Further clean up of powerplay/driver interface
- Underlay fixes
- Display link bw updates
- Gamma fixes
- Scatter/Gather display support on CZ/ST
- Misc bug fixes and clean ups
[airlied: fixup v3d vs scheduler API change]
Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
Signed-off-by: Dave Airlie <[email protected]>
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Signed-off-by: Leo Liu <[email protected]>
Reviewed-by: Alex Deucher <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>
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RLC save/restore list cntl/gpm_mem/srm_mem ucodes are used for CGPG and gfxoff
function.
Signed-off-by: Huang Rui <[email protected]>
Acked-by: Alex Deucher <[email protected]>
Acked-by: Christian König <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>
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Signed-off-by: Huang Rui <[email protected]>
Acked-by: Alex Deucher <[email protected]>
Acked-by: Christian König <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>
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git://git.kernel.org/pub/scm/linux/kernel/git/jikos/trivial
Pull trivial tree updates from Jiri Kosina.
* 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/jikos/trivial:
kfifo: fix inaccurate comment
tools/thermal: tmon: fix for segfault
net: Spelling s/stucture/structure/
edd: don't spam log if no EDD information is present
Documentation: Fix early-microcode.txt references after file rename
tracing: Block comments should align the * on each line
treewide: Fix typos in printk
GenWQE: Fix a typo in two comments
treewide: Align function definition open/close braces
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This patch fixes spelling typos found in printk.
Signed-off-by: Masanari Iida <[email protected]>
Acked-by: Randy Dunlap <[email protected]>
Signed-off-by: Jiri Kosina <[email protected]>
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Same as vega10.
Acked-by: Christian König <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>
Reviewed-by: Feifei Xu <[email protected]>
Signed-off-by: Hawking Zhang <[email protected]>
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use bo_create/free_kernel instead of manually doing it
Signed-off-by: Monk Liu <[email protected]>
Reviewed-by: Christian König <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>
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1,no sriov check since gpu recover is unified
2,need CPU_ACCESS_REQUIRED flag for VRAM if SRIOV
because otherwise after following PIN the first allocated
VRAM bo is wasted due to some TTM mgr reason.
Signed-off-by: Monk Liu <[email protected]>
Reviewed-by: Christian König <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>
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since now gpu reset is unified with gpu_recover
for both bare-metal and SR-IOV:
1)rename in_sriov_reset to in_gpu_reset
2)move lock_reset from adev->virt to adev
Signed-off-by: Monk Liu <[email protected]>
Reviewed-by: Christian König <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>
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GPU reset will require all hw doing hw_init thus
ucode_init_bo will be invoked again, which lead to
memory leak
skip the fw_buf allocation during sriov gpu reset to avoid
memory leak.
Signed-off-by: Monk Liu <[email protected]>
Reviewed-by: Christian König <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>
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- v2: share code with CHIP_VEGA10 case
Signed-off-by: Evan Quan <[email protected]>
Reviewed-by: Junwei Zhang <[email protected]>
Acked-by: Christian König <[email protected]>
Reviewed-by: Huang Rui <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>
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Signed-off-by: Evan Quan <[email protected]>
Signed-off-by: Huang Rui <[email protected]>
Acked-by: Alex Deucher <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>
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The parameter init_value contains the value to which we initialized
VRAM bo when AMDGPU_GEM_CREATE_VRAM_CLEARED flag is set.
Signed-off-by: Yong Zhao <[email protected]>
Reviewed-by: Christian König <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>
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In previous case, driver can't enable psp via the kernel parameter for raven.
We should open this path and set it as direct by default till psp firmware
loading is workable.
Signed-off-by: Huang Rui <[email protected]>
Reviewed-by: Junwei Zhang <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>
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Signed-off-by: Huang Rui <[email protected]>
Reviewed-by: Alex Deucher <[email protected]>
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Under VF environment, the ucode would be settled to the visible VRAM,
As it would be pinned to the visible VRAM, it's better to add
contiguous flag,otherwise it need to move gpu address during the pin
process. This movement is not necessary.
Signed-off-by: horchen <[email protected]>
Reviewed-by: Huang Rui <[email protected]>
Reviewed-by: Christian König <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>
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Set the appropriate ucode loading mechanism. Set to
direct for now.
Signed-off-by: Chunming Zhou <[email protected]>
Reviewed-by: Hawking Zhang <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>
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Add a new gpu info firmware to store gpu specific configuration
data. This allows us to store hw constants in a unified place.
v2: adjust structure and elements
v3: further restructure
Reviewed-by: Junwei Zhang <[email protected]>
Tested-by: Junwei Zhang <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>
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In Tonga's virtualization environment, for firmware UCODE_ID_STORAGE,
there is no actual firmware data, but we still need alloc a BO and
tell the BO's mc address to HW, or world switch will hang on VFs.
v2: fix coding style (Alex)
Signed-off-by: Trigger Huang <[email protected]>
Reviewed-by: Xiangliang Yu <[email protected]>
Reviewed-by: Monk Liu <[email protected]>
Acked-by: Huang Rui <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>
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Handle ucode differences in vega10.
Acked-by: Christian König <[email protected]>
Signed-off-by: Huang Rui <[email protected]>
Reviewed-by: Alex Deucher <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>
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This patch introduces a new flag named "amdgpu_firmware_load_type" to
handle different firmware loading method. Since Vega10, there are
three ways to load firmware. It would be better to use a flag and a
fw_load_type kernel parameter to configure it.
Acked-by: Christian König <[email protected]>
Signed-off-by: Huang Rui <[email protected]>
Reviewed-by: Alex Deucher <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>
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This will be used for newer asics.
Acked-by: Christian König <[email protected]>
Signed-off-by: Huang Rui <[email protected]>
Reviewed-by: Alex Deucher <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>
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we found some MEC ucode leads to IB test fail or even
ring test fail if Jump Table of it is not start in
FW bo with page aligned address, fixed by always make
JT address page aligned.
we don't need to patch JT2 for MEC2, because for VI,
MEC2 is a copy of MEC1, thus when converting fw_type
for MEC_JT2 we just return MEC1,hw can use the same
JT for both MEC1 & MEC2.
above two change fixed some ring/ib test failure issue
for some version of MEC ucode.
Signed-off-by: Frank Min <[email protected]>
Signed-off-by: Monk Liu <[email protected]>
Reviewed-by: Alex Deucher <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>
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for sriov, SMC need MEC_STORAGE reserved in fw bo.
Signed-off-by: Monk Liu <[email protected]>
Signed-off-by: Frank Min <[email protected]>
Reviewed-by: Alex Deucher <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>
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for GTT memory SMC can only access it within PF space, which is not
used for SRIOV case, thus for SRIOV case, we let SMC use FB space for
ucode bo.
Signed-off-by: Frank Min <[email protected]>
Reviewed-by: Alex Deucher <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>
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Signed-off-by: Huang Rui <[email protected]>
Reviewed-by: Alex Deucher <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>
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Clean up the codes to move the release handles into fail labels.
v2: squash in Christian's regression fix
Signed-off-by: Huang Rui <[email protected]>
Reviewed-by: Chunming Zhou <[email protected]>
Reviewed-by: Christian König <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>
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Adds an extra argument to amdgpu_bo_create, which is only used in amdgpu_prime.c.
Port of radeon commit 831b6966a60fe72d85ae3576056b4e4e0775b112.
v2: fix up kfd.
Signed-off-by: Christian König <[email protected]>
Reviewed-by: Jammy Zhou <[email protected]>
Reviewed-by: Alex Deucher <[email protected]>
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This adds the non-asic specific core driver code.
v2: remove extra kconfig option
v3: implement minor fixes from Fengguang Wu
v4: fix cast in amdgpu_ucode.c
Acked-by: Christian König <[email protected]>
Acked-by: Jammy Zhou <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>
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