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path: root/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h
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2021-06-04drm/amdgpu: introduce a stolen reserved buffer to protect specific buffer ↵Huang Rui1-0/+1
region (v2) Some ASICs such as Yellow Carp needs to reserve a region of video memory to avoid access from driver. So this patch is to introduce a stolen reserved buffer to protect specific buffer region. v2: free this buffer in amdgpu_ttm_fini. Signed-off-by: Huang Rui <[email protected]> Acked-and-Tested-by: Aaron Liu <[email protected]> Acked-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-04-28drm/amdgpu: address remove from fault filterPhilip Yang1-2/+4
Add interface to remove address from fault filter ring by resetting fault ring entry key, then future vm fault on the address will be processed to recover. Define fault key as atomic64_t type to use atomic read/set/cmpxchg key to protect fault ring access by interrupt handler and interrupt deferred work for vg20. Change fault->timestamp to 48-bit to share same uint64_t with 8-bit fault->next, it is enough for 48bit IH timestamp. Signed-off-by: Philip Yang <[email protected]> Reviewed-by: Felix Kuehling <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-04-20Revert "drm/amdgpu: workaround the TMR MC address issue (v2)"Oak Zeng1-9/+0
This reverts commit 2f055097daef498da57552f422f49de50a1573e6. 2f055097daef498da57552f422f49de50a1573e6 was a driver workaround when PSP firmware was not ready. Now the PSP fw is ready so we revert this driver workaround. Signed-off-by: Oak Zeng <[email protected]> Reviewed-by: Harish Kasiviswanathan <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-04-15drm/amdgpu: Introduce functions for vram physical addr calculationOak Zeng1-0/+3
Add one function to calculate BO's GPU physical address. And another function to calculate BO's CPU physical address. v2: Use functions vs macros (Christian) Use more proper function names (Christian) Signed-off-by: Oak Zeng <[email protected]> Suggested-by: Lijo Lazar <[email protected]> Reviewed-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-04-09drm/amdgpu: move xgmi ras functions to xgmi_ras_funcsHawking Zhang1-0/+9
xgmi ras is not managed by gpu driver when gpu is connected to cpu through xgmi. move all xgmi ras functions to xgmi_ras_funcs so gpu driver only initializes xgmi ras functions when it manages xgmi ras. Signed-off-by: Hawking Zhang <[email protected]> Reviewed-by: Dennis Li <[email protected]> Reviewed-by: John Clements <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-03-23drm/amdgpu: Reset the devices in the XGMI hive duirng probeshaoyunl1-0/+1
In passthrough configuration, hypervisior will trigger the SBR(Secondary bus reset) to the devices without sync to each other. This could cause device hang since for XGMI configuration, all the devices within the hive need to be reset at a limit time slot. This serial of patches try to solve this issue by co-operate with new SMU which will only do minimum house keeping to response the SBR request but don't do the real reset job and leave it to driver. Driver need to do the whole sw init and minimum HW init to bring up the SMU and trigger the reset(possibly BACO) on all the ASICs at the same time Signed-off-by: shaoyunl <[email protected]> Acked-by: Andrey Grodzovsky [email protected] Signed-off-by: Alex Deucher <[email protected]>
2021-03-23drm/amdgpu: Fix the comment in amdgpu_gmc.hOak Zeng1-3/+3
More accurate words are used to address a code review feedback Signed-off-by: Oak Zeng <[email protected]> Reviewed-by: Felix Kuehling <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-03-23drm/amdgpu: workaround the TMR MC address issue (v2)Oak Zeng1-0/+9
With the 2-level gart page table, vram is squeezed into gart aperture and FB aperture is disabled. Therefore all VRAM virtual addresses are in the GART aperture. However currently PSP requires TMR addresses in FB aperture. So we need some design change at PSP FW level to support this 2-level gart table driver change. Right now this PSP FW support doesn't exist. To workaround this issue temporarily, FB aperture is added back and the gart aperture address is converted back to FB aperture for this PSP TMR address. Will revert it after we get a fix from PSP FW. v2: squash in tmr fix for other asics (Kevin) Signed-off-by: Oak Zeng <[email protected]> Reviewed-by: Felix Kuehling <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-03-23drm/amdgpu: Add function to allocate and fill PDB0Oak Zeng1-0/+5
Add functions to allocate PDB0, map it for CPU access, and fill it. Those functions are only used for 2-level vmid0 page table construction Signed-off-by: Oak Zeng <[email protected]> Reviewed-by: Felix Kuehling <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-03-23drm/amdgpu: Use different gart table parameters for 2-level gart tableOak Zeng1-0/+3
If use gart for FB translation, we will squeeze vram into sysvm aperture. This requires 2 level gart table. Add page table depth and page table block size parameters to gmc. This is prepare work to 2-level gart table construction Signed-off-by: Oak Zeng <[email protected]> Reviewed-by: Christian Konig <[email protected]> Reviewed-by: Felix Kuehling <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-03-23drm/amdgpu: Placement of gart and vram in sysvm apertureOak Zeng1-0/+1
If use GART for FB translation, place both vram and gart to sysvm aperture. AGP aperture is not set up in this case because it is not used Signed-off-by: Oak Zeng <[email protected]> Reviewed-by: Christian Konig <[email protected]> Reviewed-by: Felix Kuehling <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-03-23drm/amdgpu: Modify comments of vram_start/endOak Zeng1-4/+7
Modify the comment to reflect the fact that, if use GART for vram address translation for vmid0, [vram_start, vram_end] will be placed inside SYSVM aperture, together with GART. Signed-off-by: Oak Zeng <[email protected]> Reviewed-by: Christian Konig <[email protected]> Reviewed-by: Felix Kuehling <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-03-23drm/amdgpu: define address map for host xgmi link (v3)Rajneesh Bhardwaj1-0/+1
This applies to AMD Accelerated Processing Platforms that support host gpu interconnect throguh a special link (xgmi). Aldebaran systems will support this special feature for utilizing the benefits of host-gpu cache coherence. This change outlines the basic framework for mapping the GPU VRAM (HBM) to system address space making it accesible to the host but managed by the amdgpu driver since this region is marked as reserved memory in host address space by the underlying system firmware. v2: switch to smuio callback function to check the type of host-gpu interface (Hawking) v3: use hub callbacks rather than direct function calls (Alex) Reviewed-by: Oak Zeng <[email protected]> Reviewed-by: Hawking Zhang <[email protected]> Signed-off-by: Rajneesh Bhardwaj <[email protected]> Signed-off-by: Hawking Zhang <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-09-25drm/amdgpu: store noretry parameter per driver instanceAlex Deucher1-0/+2
This will allow us to have different defaults per asic in a future patch. Reviewed-by: Christian König <[email protected]> Reviewed-by: Luben Tuikov <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-08-04drm/amdgpu: move stolen memory from gmc to mmanAlex Deucher1-5/+0
It's more related to memory management than memory controller. Reviewed-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-08-04drm/amdgpu/gmc: add new helper to get the FB size used by pre-OS consoleAlex Deucher1-0/+5
This adds a new gmc callback to get the size reserved by the pre-OS console and provides a helper function for use by gmc IP drivers. Reviewed-by: Christian König <[email protected]> Reviewed-by: Felix Kuehling <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-08-04drm/amdgpu: add support for extended stolen vga memoryAlex Deucher1-0/+2
This will allow us to split the allocation for systems where we have to keep the stolen memory around to avoid S3 issues. This way we don't waste as much memory and still avoid any screen artifacts during the bios to driver transition. Reviewed-by: Christian König <[email protected]> Reviewed-by: Felix Kuehling <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-08-04drm/amdgpu: move keep stolen memory check into gmc coreAlex Deucher1-0/+1
Rather than leaving this as a gmc v9 specific hack. Reviewed-by: Christian König <[email protected]> Reviewed-by: Felix Kuehling <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-08-04drm/amdgpu: move stolen vga bo from amdgpu to amdgpu.gmcAlex Deucher1-1/+2
Since that is where we store the other data related to the stolen vga memory. Reviewed-by: Christian König <[email protected]> Reviewed-by: Felix Kuehling <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-07-22drm/amdgpu: move get_invalidate_req function into gfxhub/mmhub levelHuang Rui1-0/+1
This patch is to move get_invalidate_req into gfxhub/mmhub level. It will avoid mismatch of the different gfxhub/mmhub register offsets and fields in the same gmc block. Signed-off-by: Huang Rui <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-07-22drm/amdgpu: add vmhub funcs helper (v2)Huang Rui1-0/+7
This patch is to introduce vmhub funcs helper to add following callback (print_l2_protection_fault_status). Each GC/MMHUB register specific programming should be in gfxhub/mmhub level. v2: remove the condition of funcs assignment. Signed-off-by: Huang Rui <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-07-22drm/amdgpu: abstract set_vm_fault_masks function to refine the programmingHuang Rui1-0/+4
This patch is to add set_vm_fault_masks helper to amdgpu_gmc to refine the original programming. Signed-off-by: Huang Rui <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-07-22drm/amdgpu: add member to store vm fault interrupt masksHuang Rui1-0/+2
This patch adds a member in vmhub structure to store the vm fault interrupt masks for different version gfxhubs/mmhubs. Signed-off-by: Huang Rui <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-07-08drm/amdgpu: add register distance members into vmhub structureHuang Rui1-0/+9
This patch is to abstract register distances between two continuous context domains and invalidation engines. In different ip headers, these distances may be differences. Signed-off-by: Huang Rui <[email protected]> Tested-by: AnZhong Huang <[email protected]> Reviewed-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-04-28drm/amdgpu: implement TMZ accessor (v3)Luben Tuikov1-0/+4
Implement an accessor of adev->tmz.enabled. Let not code around access it as "if (adev->tmz.enabled)" as the organization may change. Instead... Recruit "bool amdgpu_is_tmz(adev)" to return exactly this Boolean value. That is, this function is now an accessor of an already initialized and set adev and adev->tmz. Add "void amdgpu_gmc_tmz_set(adev)" to check and set adev->gmc.tmz_enabled at initialization time. After which one uses "bool amdgpu_is_tmz(adev)" to query whether adev supports TMZ. Also, remove circular header file include. v2: Remove amdgpu_tmz.[ch] as requested. v3: Move TMZ into GMC. Signed-off-by: Luben Tuikov <[email protected]> Acked-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-02-25amdgpu/gmc_v9: save/restore sdpif regs during S3Shirish S1-0/+1
fixes S3 issue with IOMMU + S/G enabled @ 64M VRAM. Suggested-by: Alex Deucher <[email protected]> Signed-off-by: Shirish S <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-01-22Revert "drm/amdgpu: fix modprobe failure of the secondary GPU when GDDR6 ↵Tianci.Yin1-5/+0
training enabled(V5)" This reverts commit 9e441478623fd913d4340654682b19f0c24e629d. The patch will be replaced with a better solution, revert it. Reviewed-by: Christian König <[email protected]> Signed-off-by: Tianci.Yin <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-01-16drm/amdgpu: fix modprobe failure of the secondary GPU when GDDR6 training ↵Tianci.Yin1-0/+5
enabled(V5) [why] In dual GPUs scenario, stolen_size is assigned to zero on the secondary GPU, since there is no pre-OS console using that memory. Then the bottom region of VRAM was allocated as GTT, unfortunately a small region of bottom VRAM was encroached by UMC firmware during GDDR6 BIST training, this cause page fault. [how] Forcing stolen_size to 3MB, then the bottom region of VRAM was allocated as stolen memory, GTT corruption avoid. Reviewed-by: Christian König <[email protected]> Reviewed-by: Feifei Xu <[email protected]> Signed-off-by: Tianci.Yin <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-01-16drm/amdgpu: export function to flush TLB via pasidAlex Sierra1-0/+6
This can be used directly from amdgpu and amdkfd to invalidate TLB through pasid. It supports gmc v7, v8, v9 and v10. Signed-off-by: Alex Sierra <[email protected]> Reviewed-by: Felix Kuehling <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-01-07drm/amdgpu/gmc: move invaliation bitmap setup to common codeAlex Deucher1-0/+1
So it can be shared with newer GMC versions. Reviewed-by: Felix Kuehling <[email protected]> Reviewed-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-11-22drm/amdgpu: initialize vm_inv_eng0_sem for gfxhub and mmhubchangzhu1-0/+1
SW must acquire/release one of the vm_invalidate_eng*_sem around the invalidation req/ack. Through this way,it can avoid losing invalidate acknowledge state across power-gating off cycle. To use vm_invalidate_eng*_sem, it needs to initialize vm_invalidate_eng*_sem firstly. Signed-off-by: changzhu <[email protected]> Reviewed-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]> Cc: [email protected]
2019-11-07drm/amdgpu: Add comments to gmc structureOak Zeng1-0/+30
Explain fields like aper_base, agp_start etc. The definition of those fields are confusing as they are from different view (CPU or GPU). Add comments for easier understand. Signed-off-by: Oak Zeng <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Reviewed-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-10-07drm/amdgpu: Report vram vendor with sysfs (v3)Ori Messinger1-0/+1
The vram vendor can be found as a separate sysfs file at: /sys/class/drm/card[X]/device/mem_info_vram_vendor The vram vendor is displayed as a string value. v2: Use correct bit masking, and cache vram_vendor in gmc v3: Drop unused functions for vram width, type, and vendor Signed-off-by: Ori Messinger <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-10-03drm/amdgpu: implement common gmc_ras_late_initTao Zhou1-0/+1
common gmc_ecc_late_init can be shared among all generations of gmc v2: rename gmc_ecc_late_init to gmc_ras_late_init Signed-off-by: Tao Zhou <[email protected]> Reviewed-by: Guchun Chen <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-10-03drm/amdgpu: add common gmc_ras_fini functionTao Zhou1-0/+1
gmc_ras_fini can be shared among all generations of gmc Signed-off-by: Tao Zhou <[email protected]> Reviewed-by: Guchun Chen <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-10-03drm/amdgpu: move mmhub_ras_if from gmc to mmhub blockTao Zhou1-1/+0
mmhub_ras_if is relevant to mmhub Signed-off-by: Tao Zhou <[email protected]> Reviewed-by: Guchun Chen <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-10-03drm/amdgpu: move umc_ras_if from gmc to umc blockTao Zhou1-1/+0
umc_ras_if is relevant to umc Signed-off-by: Tao Zhou <[email protected]> Reviewed-by: Guchun Chen <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-09-16drm/amdgpu: initialize ras structures for xgmi block (v2)Hawking Zhang1-0/+1
init ras common interface and fs node for xgmi block v2: remove unnecessary physical node number check before invoking amdgpu_xgmi_ras_late_init Signed-off-by: Hawking Zhang <[email protected]> Reviewed-by: Guchun Chen <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-09-16drm/amdgpu: move umc late init from gmc to umc blockTao Zhou1-2/+0
umc late init is umc specific, it's more suitable to be put in umc block Signed-off-by: Tao Zhou <[email protected]> Reviewed-by: Guchun Chen <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-09-16drm/amdgpu: cleanup PTE flag generation v3Christian König1-0/+5
Move the ASIC specific code into a new callback function. v2: mask the flags for SI and CIK instead of a BUG_ON(). v3: remove last missed BUG_ON(). Signed-off-by: Christian König <[email protected]> Reviewed-by: Felix Kuehling <[email protected]> Reviewed-by: Huang Rui <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-09-16drm/amdgpu: cleanup mtype mappingChristian König1-4/+3
Unify how we map the UAPI flags to the PTE hardware flags for a mapping. Only the MTYPE is actually ASIC dependent, all other flags should be copied over 1 to 1 and ASIC differences are handled later on. Signed-off-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-09-13drm/amdgpu/gmc: switch to amdgpu_gmc_ras_late_init helper functionHawking Zhang1-0/+2
amdgpu_gmc_ras_late_init is used to init gmc specfic ras debugfs/sysfs node and gmc specific interrupt handler. It can be shared among gmc generations. Signed-off-by: Hawking Zhang <[email protected]> Reviewed-by: Tao Zhou <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-08-15drm/amdgpu: Export function to flush TLB of specific vm hubOak Zeng1-3/+3
This is for kfd to reuse amdgpu TLB invalidation function. On gfx10, kfd only needs to flush TLB on gfx hub but not on mm hub. So export a function for KFD flush TLB only on specific hub. Signed-off-by: Oak Zeng <[email protected]> Reviewed-by: Christian Konig <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-08-12drm/amdgpu: create mmhub ras frameworkTao Zhou1-1/+2
enable mmhub ras feature and create sysfs/debugfs node for mmhub Signed-off-by: Tao Zhou <[email protected]> Reviewed-by: Hawking Zhang <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-03-19drm/amdgpu: use ring/hash for fault handling on GMC9 v3Christian König1-0/+34
Further testing showed that the idea with the chash doesn't work as expected. Especially we can't predict when we can remove the entries from the hash again. So replace the chash with a ring buffer/hash mix where entries in the container age automatically based on their timestamp. v2: use ring buffer / hash mix v3: check the timeout to make sure all entries age Signed-off-by: Christian König <[email protected]> Reviewed-by: Felix Kuehling <[email protected]> (v2) Signed-off-by: Alex Deucher <[email protected]>
2019-03-19drm/amdgpu: enable ras on gmc9xinhui pan1-0/+2
Signed-off-by: xinhui pan <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-03-19drm/amdgpu: Eliminate the set_pde_pte function pointer in amdgpu_gmc_funcsYong Zhao1-7/+3
All the gmc_*_set_pde_pte functions are the same across different ASICs, so we can eliminate the set_pde_pte function pointer and instead use a generic function. Signed-off-by: Yong Zhao <[email protected]> Reviewed-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2018-12-03drm/amdgpu: add a xgmi supported flagAlex Deucher1-0/+1
Use this to track whether an asic supports xgmi rather than checking the asic type everywhere. Reviewed-by: Andrey Grodzovsky <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2018-11-06drm/amdgpu/psp: add get_node_id functionHawking Zhang1-1/+1
get_node_id function is used for driver to get node_id for current device from xgmi ta Signed-off-by: Hawking Zhang <[email protected]> Acked-by: Alex Deucher <[email protected]> Reviewed-by: Huang Rui <[email protected]> Reviewed-by: Shaoyun Liu <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2018-11-05drm/amdgpu: Reorganize amdgpu_gmc_flush_gpu_tlb() for kfd to useYong Zhao1-2/+2
Add a flush_type parameter to that series of functions. Signed-off-by: Yong Zhao <[email protected]> Reviewed-by: Felix Kuehling <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Reviewed-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
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