aboutsummaryrefslogtreecommitdiff
path: root/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c
AgeCommit message (Collapse)AuthorFilesLines
2021-12-01drm/amdgpu: fix the missed handling for SDMA2 and SDMA3Guchun Chen1-0/+2
There is no base reg offset or ip_version set for SDMA2 and SDMA3 on SIENNA_CICHLID, so add them. Signed-off-by: Guchun Chen <[email protected]> Reviewed-by: Kevin Wang <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-12-01drm/amdgpu/sriov/vcn: add new vcn ip revision check case for SIENNA_CICHLIDJane Jian1-0/+1
[WHY] for sriov odd# vf will modify vcn0 engine ip revision(due to multimedia bandwidth feature), which will be mismatched with original vcn0 revision [HOW] add new version check for vcn0 disabled revision(3, 0, 192), typically modified under sriov mode Signed-off-by: Jane Jian <[email protected]> Reviewed-by: Guchun Chen <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-11-24drm/amdgpu: fix byteorder error in amdgpu discoveryYang Wang1-6/+6
fix some byteorder issues about amdgpu discovery. This will result in running errors on the big end system. (e.g:MIPS) Signed-off-by: Yang Wang <[email protected]> Reviewed-by: Guchun Chen <[email protected]> Reviewed-by: Lijo Lazar <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-11-17drm/amdgpu: add error print when failing to add IP block(v2)Guchun Chen1-0/+36
Driver initialization is driven by IP version from IP discovery table. So add error print when failing to add ip block during driver initialization, this will be more friendly to user to know which IP version is not correct. [ 40.467361] [drm] host supports REQ_INIT_DATA handshake [ 40.474076] [drm] add ip block number 0 <nv_common> [ 40.474090] [drm] add ip block number 1 <gmc_v10_0> [ 40.474101] [drm] add ip block number 2 <psp> [ 40.474103] [drm] add ip block number 3 <navi10_ih> [ 40.474114] [drm] add ip block number 4 <smu> [ 40.474119] [drm] add ip block number 5 <amdgpu_vkms> [ 40.474134] [drm] add ip block number 6 <gfx_v10_0> [ 40.474143] [drm] add ip block number 7 <sdma_v5_2> [ 40.474147] amdgpu 0000:00:08.0: amdgpu: Fatal error during GPU init [ 40.474545] amdgpu 0000:00:08.0: amdgpu: amdgpu: finishing device. v2: use dev_err to multi-GPU system Signed-off-by: Guchun Chen <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-11-10drm/amdgpu: add missed support for UVD IP_VERSION(3, 0, 64)Guchun Chen1-0/+1
Fixes: 96b8dd4423e74d ("drm/amdgpu/amdgpu_vcn: convert to IP version checking") Signed-off-by: Flora Cui <[email protected]> Signed-off-by: Guchun Chen <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-11-10drm/amdgpu: drop jpeg IP initialization in SRIOV caseGuchun Chen1-1/+2
Fixes: b05b9c591f9ed6 ("drm/amdgpu: clean up set IP function") Signed-off-by: Guchun Chen <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-10-28drm/amdgpu/discovery: add SDMA IP instance info for soc15 partsAlex Deucher1-0/+14
Add secondary instance version info for soc15 parts. Reviewed-by: Luben Tuikov <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-10-28drm/amdgpu/discovery: add UVD/VCN IP instance info for soc15 partsAlex Deucher1-0/+3
Add secondary instance version info for vega20, arcturure, and aldebaran. Acked-by: Christian König <[email protected]> Reviewed-by: Luben Tuikov <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-10-22drm/amdgpu/nbio7.4: use original HDP_FLUSH bitsAlex Deucher1-1/+4
The extended bits were not available for use on vega20 and presumably arcturus as well. Fixes: a0f9f854666834 ("drm/amdgpu/nbio7.4: don't use GPU_HDP_FLUSH bit 12") Reviewed-and-tested-by: Guchun Chen <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-10-21drm/amdgpu: Workaround harvesting info for some navy flounder boardsAlex Deucher1-0/+4
Some navy flounder boards do not properly mark harvested VCN instances. Fix that here. v2: use IP versions Fixes: 1b592d00b4ac83 ("drm/amdgpu/vcn: remove manual instance setting") Bug: https://gitlab.freedesktop.org/drm/amd/-/issues/1743 Reviewed-and-tested-by: Guchun Chen <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-10-19drm/amdgpu/discovery: parse hw_id_name for SDMA instance 2 and 3Guchun Chen1-0/+2
Otherwise, hw_id_name string is NULL for SDMA 2 and 3 when dumping ip version from VBIOS. Signed-off-by: Guchun Chen <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-10-13drm/amdgpu: enable display for cyan skillfishLang Yu1-2/+1
Display support for cyan skillfish is ready now. Enable it! Signed-off-by: Lang Yu <[email protected]> Reviewed-by: Huang Rui <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-10-13drm/amdgpu/nbio2.3: don't use GPU_HDP_FLUSH bit 12Alex Deucher1-1/+4
It's used internally by firmware. Using it in the driver could conflict with firmware. v2: squash in fix for navi1x (Alex) Reviewed-by: James Zhu <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-10-08drm/amdgpu: add missing case for HDP for renoirAlex Deucher1-0/+1
Missing 4.1.2. Reviewed-by: Rodrigo Siqueira <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-10-08drm/amdgpu/discovery: add missing case for SMU 11.0.5Alex Deucher1-0/+1
Was missed when converting the driver over to IP based initialization. Tested-by: Harry Wentland <[email protected]> Reviewed-by: Guchun Chen <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-10-04drm/amdgpu: remove some repeated includingsGuo Zhengkui1-2/+0
Remove two repeated includings in line 46 and 47. Acked-by: Christian König <[email protected]> Signed-off-by: Guo Zhengkui <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-10-04drm/amdgpu: add an option to override IP discovery table from a fileAlex Deucher1-4/+20
If you set amdgpu.discovery=2 you can force the the driver to fetch the IP discovery table from a file rather than from the table shipped on the device. This is useful for debugging and for device bring up and emulation when the tables may be in flux. Reviewed-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-10-04drm/amdgpu: add support for SRIOV in IP discovery pathAlex Deucher1-9/+25
Handle SRIOV requirements when adding IP blocks. v2: add comment about UVD/VCE support on vega20 SR-IOV Acked-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-10-04drm/amdgpu: clean up set IP functionAlex Deucher1-335/+387
Split into several smaller per IP functions to make it easier to handle ordering issues for things like SR-IOV in a follow up patch. Acked-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-10-04drm/amdgpu: convert IP version array to include instancesAlex Deucher1-131/+140
Allow us to query instances versions more cleanly. Instancing support is not consistent unfortunately. SDMA is a good example. Sienna cichlid has 4 total SDMA instances, each enumerated separately (HWIDs 42, 43, 68, 69). Arcturus has 8 total SDMA instances, but they are enumerated as multiple instances of the same HWIDs (4x HWID 42, 4x HWID 43). UMC is another example. On most chips there are multiple instances with the same HWID. This allows us to support both forms. v2: rebase v3: clarify instancing support Reviewed-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-10-04drm/amdgpu: get VCN harvest information from IP discovery tableAlex Deucher1-0/+4
Use the table rather than asic specific harvest registers. v2: remove harvesting register checking Signed-off-by: Alex Deucher <[email protected]>
2021-10-04drm/amdgpu: get VCN and SDMA instances from IP discovery tableAlex Deucher1-0/+14
Rather than hardcoding it. We already have the number of VCN instances from a previous patch, so just update the VCN instances for chips with static tables. v2: squash in checks for SDMA3,4 (Guchun) v3: clarify VCN changes Reviewed-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-10-04drm/amdgpu: add initial IP discovery support for vega based partsAlex Deucher1-30/+387
Hardcode the IP versions for asics without IP discovery tables and then enumerate the asics based on the IP versions. TODO: fix SR-IOV support v2: Squash in HDP fix for Renoir Acked-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-10-04drm/amdgpu: add DCI HWIPAlex Deucher1-0/+1
So we can track grab the appropriate DCE info out of the IP discovery table. This is a separare IP from DCN. Acked-by: Harry Wentland <[email protected]> Acked-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-10-04drm/amdgpu: add initial IP enumeration via IP discovery tableAlex Deucher1-0/+333
Add initial support for all navi based parts. v2: rebase Acked-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-10-04drm/amdgpu: add XGMI HWIPAlex Deucher1-0/+1
So we can track grab the appropriate XGMI info out of the IP discovery table. Reviewed-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-10-04drm/amdgpu: fill in IP versions from IP discovery tableAlex Deucher1-1/+2
Prerequisite for using IP versions in the driver rather than asic type. v2: Use IP_VERSION() macro instead of new function Reviewed-by: Christian König <[email protected]> (v1) Signed-off-by: Alex Deucher <[email protected]>
2021-10-04drm/amdgpu: store HW IP versions in the driver structureAlex Deucher1-1/+0
So we can check the IP versions directly rather than using asic type. Reviewed-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-10-04drm/amdgpu: move headless sku check into harvest functionAlex Deucher1-0/+7
Consolidate harvesting information. Reviewed-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-09-29drm/amd/amdgpu: Validate ip discovery blobErnst Sjöstrand1-0/+21
We use the number_instance index that we get from the fw discovery blob to index into an array for example. Update error messages (Alex) Signed-off-by: Ernst Sjöstrand <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-08-10drm/amdgpu: handle VCN instances when harvesting (v2)Alex Deucher1-3/+9
There may be multiple instances and only one is harvested. v2: fix typo in commit message Fixes: 83a0b8639185 ("drm/amdgpu: add judgement when add ip blocks (v2)") Bug: https://gitlab.freedesktop.org/drm/amd/-/issues/1673 Reviewed-by: Guchun Chen <[email protected]> Reviewed-by: James Zhu <[email protected]> Signed-off-by: Alex Deucher <[email protected]> Cc: [email protected]
2021-06-18drm/amd/amdgpu: Use IP discovery data to determine VCN enablement instead of ↵Bokun Zhang1-0/+8
MMSCH In the past, we use MMSCH to determine whether a VCN is enabled or not. This is not reliable since after a FLR, MMSCH may report junk data. It is better to use IP discovery data. Signed-off-by: Bokun Zhang <[email protected]> Signed-off-by: Peng Ju Zhou <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-06-11drm/amd/amdgpu: add instance_number check in amdgpu_discovery_get_ip_versionPeng Ju Zhou1-2/+2
The original code returns IP version of instantce_0 for every IP. This implementation may be correct for most of IPs. However, for certain IP block (VCN for example), it may have 2 instances and both of them have the same hw_id, BUT they have different revision number (0 and 1). In this case, the original amdgpu_discovery_get_ip_version cannot correct reflects the result and returns false information Signed-off-by: Bokun Zhang <[email protected]> Signed-off-by: Peng Ju Zhou <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-05-13drm/amdgpu: add judgement when add ip blocks (v2)Likun GAO1-0/+28
Judgement whether to add an sw ip according to the harvest info. v2: fix indentation (Alex) Signed-off-by: Likun Gao <[email protected]> Reviewed-by: Guchun Chen <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-11-13drm/amdgpu: add UMC to ip discovery mapJohn Clements1-0/+1
resolve issue with UMC base offset not being set correctly in ip discovery sequence Reviewed-by: Hawking Zhang <[email protected]> Signed-off-by: John Clements <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-08-04drm/amdgpu: move IP discovery data to mmanAlex Deucher1-27/+27
It's related to the memory manager so move it there. Reviewed-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-07-02drm/amdgpu: reduce ip discovery data reading sizeWenhui Sheng1-1/+1
Only read first 4K data instead of whole TMR block, so we can reduce the time in full access mode. Signed-off-by: Wenhui Sheng <[email protected]> Reviewed-by: Hawking Zhang <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-07-01drm/amdgpu: label internally used symbols as staticNirmoy Das1-1/+1
Used sparse(make C=1) to find these loose ends. v2: removed unwanted extra line Signed-off-by: Nirmoy Das <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-05-01drm/amdgpu: re-structue members for ip discoveryHawking Zhang1-27/+29
This is to prepare for initializing discovery tmr size per ASIC type Signed-off-by: Hawking Zhang <[email protected]> Reviewed-by: Likun Gao <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-04-01drm/amdgpu: adjust sequence of ip_discovery init and timeout_settingMonk Liu1-4/+6
what: 1)move timtout setting before ip_early_init to reduce exclusive mode cost for SRIOV 2)move ip_discovery_init() to inside of amdgpu_discovery_reg_base_init() it is a prepare for the later upcoming patches. why: in later upcoming patches we would use a new mailbox event -- "req_gpu_init_data", which is a callback hooked in adev->virt.ops and this callback send a new event "REQ_GPU_INIT_DAT" to host to notify host to do some preparation like "IP discovery/vbios on the VF FB" and this callback must be: A) invoked after set_ip_block() because virt.ops is configured during set_ip_block() B) invoked before ip_discovery_init() becausen ip_discovery_init() need host side prepares everything in VF FB first. current place of ip_discovery_init() is before we can invoke callback of adev->virt.ops, thus we must move ip_discovery_init() to a place after the adev->virt.ops all settle done, and the perfect place is in amdgpu_discovery_reg_base_init() Signed-off-by: Monk Liu <[email protected]> Reviewed-by: Emily Deng <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-04-01drm/amdgpu: purge ip_discovery headersMonk Liu1-2/+0
those two headers are not needed for ip discovery Signed-off-by: Monk Liu <[email protected]> Reviewed-by: Emily Deng <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-02-25drm/amdgpu/discovery: make the discovery code less chattyAlex Deucher1-1/+1
Make the IP block base output debug only. Reviewed-by: Xiaojie Yuan <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-10-17drm/amdgpu: add a generic fb accessing helper function(v3)Tianci.Yin1-11/+1
add a generic helper function for accessing framebuffer via MMIO Reviewed-by: Alex Deucher <[email protected]> Reviewed-by: Luben Tuikov <[email protected]> Signed-off-by: Tianci.Yin <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-10-17drm/amdgpu: update amdgpu_discovery to handle revisionTianci.Yin1-1/+3
update amdgpu_discovery to get IP revision. Reviewed-by: Alex Deucher <[email protected]> Reviewed-by: Luben Tuikov <[email protected]> Signed-off-by: Tianci.Yin <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-10-15drm/amdgpu/discovery: reserve discovery data at the top of VRAMXiaojie Yuan1-2/+2
IP Discovery data is TMR fenced by the latest PSP BL, so we need to reserve this region. Tested on navi10/12/14 with VBIOS integrated with latest PSP BL. v2: use DISCOVERY_TMR_SIZE macro as bo size use amdgpu_bo_create_kernel_at() to allocate bo Signed-off-by: Xiaojie Yuan <[email protected]> Reviewed-by: Hawking Zhang <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-07-11drm/amdgpu/discovery: fix DCE_HWIP mapping error in hw_id_map arraytiancyin1-1/+1
ID of DCE_HWIP from vbios is DMU_HWID, mismatch cause null pointer crash in navi10 modprobe. Reviewed-by: Feifei Xu <[email protected]> Reviewed-by: Xiaojie Yuan <[email protected]> Signed-off-by: tiancyin <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-06-21drm/amdgpu/discovery: refactor ip list traversalXiaojie Yuan1-29/+42
for each ip, check whether it is needed by amdgpu driver, if yes, record its base addresses v2: change some DRM_INFO to DRM_DEBUG v3: remove unused variable (Alex) Signed-off-by: Xiaojie Yuan <[email protected]> Reviewed-by: Hawking Zhang <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-06-21drm/amdgpu/discovery: stop converting the units of base addressesXiaojie Yuan1-3/+3
the unit is already in dword Signed-off-by: Xiaojie Yuan <[email protected]> Reviewed-by: Hawking Zhang <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-06-21drm/amdgpu/discovery: stop taking psp header into accountXiaojie Yuan1-6/+5
psp will write a header to vram, but the value exposed in RCC_CONFIG_MEMSIZE does not include the memory that this header is written to. Therefore, the interpretation of the table does not need to take the psp header into account. Signed-off-by: Xiaojie Yuan <[email protected]> Reviewed-by: Hawking Zhang <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-06-21drm/amdgpu/discovery: fix hwid for nbioXiaojie Yuan1-1/+1
Properly set this. Signed-off-by: Xiaojie Yuan <[email protected]> Reviewed-by: Hawking Zhang <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
Powered by cgit, Gruvboxed by Blaster4385.