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2017-10-19drm/amdgpu: move the VRAM lost counter per contextChristian König1-0/+1
Instead of per device track the VRAM lost per context and return ECANCELED instead of ENODEV. Signed-off-by: Christian König <[email protected]> Reviewed-by: Nicolai Hähnle <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-10-19drm/amdgpu: Move old fence waiting before reservation lock is aquired v2Andrey Grodzovsky1-6/+24
Helps avoiding deadlock during GPU reset. Added mutex to amdgpu_ctx to preserve order of fences on a ring. v2: Put waiting logic in a function in a seperate function in amdgpu_ctx.c Signed-off-by: Andrey Grodzovsky <[email protected]> Reviewed-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-10-09drm/amdgpu: add interface for editing a foreign process's priority v3Andres Rodriguez1-20/+1
The AMDGPU_SCHED_OP_PROCESS_PRIORITY_OVERRIDE ioctls are used to set the priority of a different process in the current system. When a request is dropped, the process's contexts will be restored to the priority specified at context creation time. A request can be dropped by setting the override priority to AMDGPU_CTX_PRIORITY_UNSET. An fd is used to identify the remote process. This is simpler than passing a pid number, which is vulnerable to re-use, etc. This functionality is limited to DRM_MASTER since abuse of this interface can have a negative impact on the system's performance. v2: removed unused output structure v3: change refcounted interface for a regular set operation Signed-off-by: Andres Rodriguez <[email protected]> Acked-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-10-09drm/amdgpu: add plumbing for ctx priority changes v2Andres Rodriguez1-0/+29
Introduce amdgpu_ctx_priority_override(). A mechanism to override a context's priority. An override can be terminated by setting the override to AMD_SCHED_PRIORITY_UNSET. v2: change refcounted interface for a direct set Signed-off-by: Andres Rodriguez <[email protected]> Acked-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-10-09drm/amdgpu: introduce AMDGPU_CTX_PRIORITY_UNSETAndres Rodriguez1-0/+2
Use _INVALID to identify bad parameters and _UNSET to represent the lack of interest in a specific value. Signed-off-by: Andres Rodriguez <[email protected]> Acked-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-10-09drm/amdgpu: make amdgpu_to_sched_priority detect invalid parametersAndres Rodriguez1-3/+5
Returning invalid priorities as _NORMAL is a backwards compatibility quirk of amdgpu_ctx_ioctl(). Move this detail one layer up where it belongs. Signed-off-by: Andres Rodriguez <[email protected]> Acked-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-10-09drm/amdgpu: add parameter to allocate high priority contexts v11Andres Rodriguez1-4/+57
Add a new context creation parameter to express a global context priority. The priority ranking in descending order is as follows: * AMDGPU_CTX_PRIORITY_HIGH_HW * AMDGPU_CTX_PRIORITY_HIGH_SW * AMDGPU_CTX_PRIORITY_NORMAL * AMDGPU_CTX_PRIORITY_LOW_SW * AMDGPU_CTX_PRIORITY_LOW_HW The driver will attempt to schedule work to the hardware according to the priorities. No latency or throughput guarantees are provided by this patch. This interface intends to service the EGL_IMG_context_priority extension, and vulkan equivalents. Setting a priority above NORMAL requires CAP_SYS_NICE or DRM_MASTER. v2: Instead of using flags, repurpose __pad v3: Swap enum values of _NORMAL _HIGH for backwards compatibility v4: Validate usermode priority and store it v5: Move priority validation into amdgpu_ctx_ioctl(), headline reword v6: add UAPI note regarding priorities requiring CAP_SYS_ADMIN v7: remove ctx->priority v8: added AMDGPU_CTX_PRIORITY_LOW, s/CAP_SYS_ADMIN/CAP_SYS_NICE v9: change the priority parameter to __s32 v10: split priorities into _SW and _HW v11: Allow DRM_MASTER without CAP_SYS_NICE Reviewed-by: Emil Velikov <[email protected]> Reviewed-by: Christian König <[email protected]> Signed-off-by: Andres Rodriguez <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-09-26drm/amdgpu:make ctx_add_fence interruptible(v2)Monk Liu1-5/+7
otherwise a gpu hang will make application couldn't be killed under timedout=0 mode v2: Fix memoryleak job/job->s_fence issue unlock mn remove the ERROR msg after waiting being interrupted Signed-off-by: Monk Liu <[email protected]> Reviewed-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-05-31drm/amdgpu: untie user ring ids from kernel ring ids v6Andres Rodriguez1-0/+6
Add amdgpu_queue_mgr, a mechanism that allows disjointing usermode's ring ids from the kernel's ring ids. The queue manager maintains a per-file descriptor map of user ring ids to amdgpu_ring pointers. Once a map is created it is permanent (this is required to maintain FIFO execution guarantees for a context's ring). Different queue map policies can be configured for each HW IP. Currently all HW IPs use the identity mapper, i.e. kernel ring id is equal to the user ring id. The purpose of this mechanism is to distribute the load across multiple queues more effectively for HW IPs that support multiple rings. Userspace clients are unable to check whether a specific resource is in use by a different client. Therefore, it is up to the kernel driver to make the optimal choice. v2: remove amdgpu_queue_mapper_funcs v3: made amdgpu_queue_mgr per context instead of per-fd v4: add context_put on error paths v5: rebase and include new IPs UVD_ENC & VCN_* v6: drop unused amdgpu_ring_is_valid_index (Alex) Reviewed-by: Christian König <[email protected]> Signed-off-by: Andres Rodriguez <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-05-24drm/amdgpu:don't init entity for KIQMonk Liu1-0/+4
We don't need a scheduler for KIQ. Signed-off-by: Monk Liu <[email protected]> Reviewed-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-04-28drm/amdgpu:fix race conditionMonk Liu1-0/+3
sequence is protected by spinlock so don't access sequence in paramter seq when invoking this function. ~0 means to get the latest sequence number and 0 means none to get. Change-Id: Ib7a03f3cf5594deeb4ad333cc59b47a6bddfd1ad Signed-off-by: Monk Liu <[email protected]> Reviewed-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-02-13idr: Return the deleted entry from idr_removeMatthew Wilcox1-7/+3
It is a relatively common idiom (8 instances) to first look up an IDR entry, and then remove it from the tree if it is found, possibly doing further operations upon the entry afterwards. If we change idr_remove() to return the removed object, all of these users can save themselves a walk of the IDR tree. Signed-off-by: Matthew Wilcox <[email protected]>
2016-10-28Merge tag 'topic/drm-misc-2016-10-27' of ↵Dave Airlie1-11/+11
git://anongit.freedesktop.org/git/drm-intel into drm-next Pull request already again to get the s/fence/dma_fence/ stuff in and allow everyone to resync. Otherwise really just misc stuff all over, and a new bridge driver. * tag 'topic/drm-misc-2016-10-27' of git://anongit.freedesktop.org/git/drm-intel: drm/bridge: fix platform_no_drv_owner.cocci warnings drm/bridge: fix semicolon.cocci warnings drm: Print some debug/error info during DP dual mode detect drm: mark drm_of_component_match_add dummy inline drm/bridge: add Silicon Image SiI8620 driver dt-bindings: add Silicon Image SiI8620 bridge bindings video: add header file for Mobile High-Definition Link (MHL) interface drm: convert DT component matching to component_match_add_release() dma-buf: Rename struct fence to dma_fence dma-buf/fence: add an lockdep_assert_held() drm/dp: Factor out helper to distinguish between branch and sink devices drm/edid: Only print the bad edid when aborting drm/msm: add missing header dependencies drm/msm/adreno: move function declarations to header file drm/i2c/tda998x: mark symbol static where possible doc: add missing docbook parameter for fence-array drm: RIP mode_config->rotation_property drm/msm/mdp5: Advertize 180 degree rotation drm/msm/mdp5: Use per-plane rotation property
2016-10-27drm/amdgpu: use failed label to handle context init failureHuang Rui1-9/+9
Signed-off-by: Huang Rui <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2016-10-25dma-buf: Rename struct fence to dma_fenceChris Wilson1-11/+11
I plan to usurp the short name of struct fence for a core kernel struct, and so I need to rename the specialised fence/timeline for DMA operations to make room. A consensus was reached in https://lists.freedesktop.org/archives/dri-devel/2016-July/113083.html that making clear this fence applies to DMA operations was a good thing. Since then the patch has grown a bit as usage increases, so hopefully it remains a good thing! (v2...: rebase, rerun spatch) v3: Compile on msm, spotted a manual fixup that I broke. v4: Try again for msm, sorry Daniel coccinelle script: @@ @@ - struct fence + struct dma_fence @@ @@ - struct fence_ops + struct dma_fence_ops @@ @@ - struct fence_cb + struct dma_fence_cb @@ @@ - struct fence_array + struct dma_fence_array @@ @@ - enum fence_flag_bits + enum dma_fence_flag_bits @@ @@ ( - fence_init + dma_fence_init | - fence_release + dma_fence_release | - fence_free + dma_fence_free | - fence_get + dma_fence_get | - fence_get_rcu + dma_fence_get_rcu | - fence_put + dma_fence_put | - fence_signal + dma_fence_signal | - fence_signal_locked + dma_fence_signal_locked | - fence_default_wait + dma_fence_default_wait | - fence_add_callback + dma_fence_add_callback | - fence_remove_callback + dma_fence_remove_callback | - fence_enable_sw_signaling + dma_fence_enable_sw_signaling | - fence_is_signaled_locked + dma_fence_is_signaled_locked | - fence_is_signaled + dma_fence_is_signaled | - fence_is_later + dma_fence_is_later | - fence_later + dma_fence_later | - fence_wait_timeout + dma_fence_wait_timeout | - fence_wait_any_timeout + dma_fence_wait_any_timeout | - fence_wait + dma_fence_wait | - fence_context_alloc + dma_fence_context_alloc | - fence_array_create + dma_fence_array_create | - to_fence_array + to_dma_fence_array | - fence_is_array + dma_fence_is_array | - trace_fence_emit + trace_dma_fence_emit | - FENCE_TRACE + DMA_FENCE_TRACE | - FENCE_WARN + DMA_FENCE_WARN | - FENCE_ERR + DMA_FENCE_ERR ) ( ... ) Signed-off-by: Chris Wilson <[email protected]> Reviewed-by: Gustavo Padovan <[email protected]> Acked-by: Sumit Semwal <[email protected]> Acked-by: Christian König <[email protected]> Signed-off-by: Daniel Vetter <[email protected]> Link: http://patchwork.freedesktop.org/patch/msgid/[email protected]
2016-10-12drm/amdgpu: initialize the context reset_counter in amdgpu_ctx_initNicolai Hähnle1-0/+3
Ensure that we really only report a GPU reset if one has happened since the creation of the context. Signed-off-by: Nicolai Hähnle <[email protected]> Reviewed-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]> Cc: [email protected] Signed-off-by: Alex Deucher <[email protected]>
2016-09-27drm/amdgpu: don't leave dangling pointers aroundGrazvydas Ignotas1-0/+2
Right now it's possible to trigger fence_drv.fences[] dereference after the array has been freed. While the real problem is elsewhere, this still results in confusing errors that depend on how the freed memory was reused (I've seen "kernel tried to execute NX-protected page"), it's better to clear them and get NULL dereference so that it's obvious what's going wrong. Signed-off-by: Grazvydas Ignotas <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2016-02-12drm/amdgpu: fix coding style in amdgpu_ctx.cChristian König1-16/+15
Don't use pointer arithmetic and fix the indentation. Signed-off-by: Christian König <[email protected]> Reviewed-by: Alex Deucher <[email protected]>
2016-02-12drm/amdgpu: nuke the kernel contextChristian König1-11/+7
Not used any more. Signed-off-by: Christian König <[email protected]> Reviewed-by: Alex Deucher <[email protected]>
2016-02-10drm/amdgpu: clean up non-scheduler code path (v2)Chunming Zhou1-26/+22
Non-scheduler code is longer supported. v2: agd: rebased on upstream Signed-off-by: Chunming Zhou <[email protected]> Reviewed-by: Ken Wang <[email protected]> Reviewed-by: Monk Liu <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2015-12-18drm/amdgpu: restrict the sched jobs number to power of twoChunming Zhou1-2/+2
Signed-off-by: Chunming Zhou <[email protected]> Reviewed-by: Christian König <[email protected]> CC: [email protected]
2015-12-14drm/amdgpu: unify AMDGPU_CTX_MAX_CS_PENDING and amdgpu_sched_jobsChunming Zhou1-7/+18
Signed-off-by: Chunming Zhou <[email protected]> Reviewed-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2015-12-14drm/amdgpu: handle error case for ctxChunming Zhou1-2/+5
Properly handle ctx init failure. Signed-off-by: Chunming Zhou <[email protected]> Reviewed-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2015-12-02drm/amd: abstract kernel rq and normal rq to priority of run queueChunming Zhou1-6/+5
Allows us to set priorities in the scheduler. Signed-off-by: Chunming Zhou <[email protected]> Reviewed-by: Christian König <[email protected]> Reviewed-by: Junwei Zhang <[email protected]>
2015-11-03drm/amdgpu: don't oops on failure to load (v2)Dave Airlie1-0/+3
In two places amdgpu tries to tear down something it hasn't initalised when failing. This is what happens when you enable experimental support on topaz which then fails in ring init. This patch allows it to fail cleanly. v2 (agd): split out scheduler change into a separate patch Reviewed-by: Chunming Zhou <[email protected]> Reviewed-by: Christian König <[email protected]> Signed-off-by: Dave Airlie <[email protected]> Signed-off-by: Alex Deucher <[email protected]> Cc: [email protected]
2015-09-23drm/amdgpu: more scheduler cleanups v2Christian König1-5/+5
Embed the scheduler into the ring structure instead of allocating it. Use the ring name directly instead of the id. v2: rebased, whitespace cleanup Signed-off-by: Christian König <[email protected]> Reviewed-by: Junwei Zhang <[email protected]> Reviewed-by: Chunming Zhou<[email protected]>
2015-09-23drm/amdgpu: rename fence->scheduler to sched v2Christian König1-5/+5
Just to be consistent with the other members. v2: rename the ring member as well. Signed-off-by: Christian König <[email protected]> Reviewed-by: Junwei Zhang <[email protected]> (v1) Reviewed-by: Chunming Zhou<[email protected]>
2015-08-25drm/amdgpu: remove the context from amdgpu_jobChristian König1-7/+0
Signed-off-by: Christian König <[email protected]> Reviewed-by: Chunming Zhou <[email protected]>
2015-08-25drm/amdgpu: remove v_seq handling from the scheduler v2Christian König1-15/+5
Simply not used any more. Only keep 32bit atomic for fence sequence numbering. v2: trivial rebase Signed-off-by: Christian König <[email protected]> Reviewed-by: Alex Deucher <[email protected]> (v1) Reviewed-by: Jammy Zhou <[email protected]> (v1) Reviewed-by: Chunming Zhou <[email protected]> (v1)
2015-08-20drm/amdgpu: abstract amdgpu_job for schedulerChunming Zhou1-0/+7
Signed-off-by: Chunming Zhou <[email protected]> Reviewed-by: Christian K?nig <[email protected]>
2015-08-17drm/amdgpu: cleanup sheduler rq handling v2Christian König1-1/+1
Rework run queue implementation, especially remove the odd list handling. v2: cleanup the code only, no algorithem change. Signed-off-by: Christian König <[email protected]> Reviewed-by: Chunming Zhou <[email protected]>
2015-08-17drm/amd: add scheduler fence implementation (v2)Chunming Zhou1-10/+0
scheduler fence is based on kernel fence framework. v2: squash in Christian's build fix Signed-off-by: Chunming Zhou <[email protected]> Reviewed-by: Christian K?nig <[email protected]>
2015-08-17drm/amdgpu: merge amd_sched_entity and amd_context_entity v2Christian König1-9/+9
Avoiding a couple of casts. v2: rename c_entity to entity as well Signed-off-by: Christian König <[email protected]> Reviewed-by: Chunming Zhou <[email protected]>
2015-08-17drm/amdgpu: remove unused parent entityChristian König1-1/+1
Signed-off-by: Christian König <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Reviewed-by: Chunming Zhou <[email protected]>
2015-08-17drm/amdgpu: cleanup amdgpu_ctx inti/fini v2Christian König1-77/+68
Cleanup the kernel context handling. v2: rebased Signed-off-by: Christian König <[email protected]> Reviewed-by: Chunming Zhou <[email protected]> (v1)
2015-08-17drm/amdgpu: stop leaking the ctx id into the scheduler v2Christian König1-7/+4
Id's are for the IOCTL ABI only. v2: remove tgid as well Signed-off-by: Christian König <[email protected]> Reviewed-by: Chunming Zhou <[email protected]>
2015-08-17drm/amdgpu: cleanup ctx_mgr init/finiChristian König1-17/+23
Signed-off-by: Christian König <[email protected]> Reviewed-by: Chunming Zhou <[email protected]>
2015-08-17drm/amdgpu: add amd_sched_next_queued_seq functionJammy Zhou1-1/+1
This function is used to get the next queued sequence number Signed-off-by: Jammy Zhou <[email protected]> Reviewed-by: Christian König <[email protected]> Reviewed-by: Alex Deucher <[email protected]>
2015-08-17drm/amdgpu: fix seq in ctx_add_fenceChunming Zhou1-2/+2
if enabling scheduler, then the queued seq is assigned when pushing job before emitting job. Signed-off-by: Chunming Zhou <[email protected]> Reviewed-by: Christian K?nig <[email protected]>
2015-08-17drm/amdgpu: wait forever for wait emitChunming Zhou1-2/+2
the job must be emitted by scheduler, otherwise scheduler is abnormal. Signed-off-by: Chunming Zhou <[email protected]> Reviewed-by: Christian K?nig <[email protected]>
2015-08-17drm/amdgpu: add amdgpu.sched_jobs optionJammy Zhou1-1/+2
This option can be used to specify the max job number in the job queue, and it is 16 by default. Signed-off-by: Jammy Zhou <[email protected]> Reviewed-by: Chunming Zhou <[email protected]>
2015-08-17drm/amdgpu: add kernel ctx support (v2)Chunming Zhou1-24/+59
v2: rebase against kfd changes Signed-off-by: Chunming Zhou <[email protected]> Acked-by: Christian K?nig <[email protected]> Reviewed-by: Jammy Zhou <[email protected]>
2015-08-17drm/amdgpu: make sure the fence is emitted before ring to get it.Chunming Zhou1-0/+10
Signed-off-by: Chunming Zhou <[email protected]> Acked-by: Christian K?nig <[email protected]> Reviewed-by: Jammy Zhou <[email protected]>
2015-08-17drm/amdgpu: use scheduler user seq instead of previous user seqChunming Zhou1-6/+20
Signed-off-by: Chunming Zhou <[email protected]> Acked-by: Christian K?nig <[email protected]> Reviewed-by: Jammy Zhou <[email protected]>
2015-08-17drm/amdgpu: add context entity initChunming Zhou1-1/+35
Signed-off-by: Chunming Zhou <[email protected]> Acked-by: Christian K?nig <[email protected]> Reviewed-by: Jammy Zhou <[email protected]>
2015-08-17drm/amdgpu: fix signed overrun in amdgpu_ctx_get_fenceChristian König1-1/+1
Otherwise the first 16 fences of a context will always signal immediately. Signed-off-by: Christian König <[email protected]> Reviewed-by: Jammy Zhou <[email protected]>
2015-08-17drm/amdgpu: fix context memory leakChristian König1-0/+1
Signed-off-by: Christian König <[email protected]> Reviewed-by: Jammy Zhou <[email protected]>
2015-08-17drm/amdgpu: add user fence context map v2Christian König1-1/+59
This is a prerequisite for the GPU scheduler to make the order of submission independent from the order of execution. v2: properly implement the locking Signed-off-by: Christian König <[email protected]> Reviewed-by: Jammy Zhou <[email protected]> Reviewed-by: Chunming Zhou <[email protected]>
2015-08-17drm/amdgpu: cleanup context structure v2Alex Deucher1-21/+7
The comment is misleading and incorrect, remove it. Printing the id is completely meaningless and this practice can cause a race conditions on command submission. The flags and hangs fields are completely unused. Give all fields a common indentation. v2: remove fpriv reference and unused flags as well, fix debug message. Signed-off-by: Christian König <[email protected]> Reviewed-by: Jammy Zhou <[email protected]> Reviewed-by: Chunming Zhou <[email protected]>
2015-06-03drm/amdgpu: add and implement the GPU reset status queryMarek Olšák1-13/+23
Signed-off-by: Marek Olšák <[email protected]> Reviewed-by: Christian König <[email protected]> Reviewed-by: Jammy Zhou <[email protected]>
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