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path: root/drivers/gpio/gpio-crystalcove.c
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2020-08-04gpio: crystalcove: Free IRQ on error pathAndy Shevchenko1-15/+3
It appears that all, but request_irq(), calls in the driver are device managed. In unlikely case of devm_gpiochip_add_data() failure the IRQ left requested. Free IRQ on error path by switching to devm_request_threaded_irq() API. Byproduct of this change is a drop of ->remove() callback completely. Fixes: 945e72db36bd ("gpio: crystalcove: Use irqchip template") Signed-off-by: Andy Shevchenko <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Linus Walleij <[email protected]>
2020-07-22gpio: crystalcove: Use irqchip templateLinus Walleij1-9/+15
This makes the driver use the irqchip template to assign properties to the gpio_irq_chip instead of using the explicit calls to gpiochip_irqchip_add_nested() and gpiochip_set_nested_irqchip(). The irqchip is instead added while adding the gpiochip. Cc: Andy Shevchenko <[email protected]> Cc: Kuppuswamy Sathyanarayanan <[email protected]> Cc: Hans de Goede <[email protected]> Signed-off-by: Linus Walleij <[email protected]> Reviewed-by: Kuppuswamy Sathyanarayanan <[email protected]> Tested-by: Hans de Goede <[email protected]> Signed-off-by: Andy Shevchenko <[email protected]>
2020-07-21gpio: crystalcove: changed every 'unsigned' to 'unsigned int'Abanoub Sameh1-5/+5
Changed 'unsigned' to 'unsigned int'. This makes the code more uniform, and compliant with the kernel coding style. Signed-off-by: Abanoub Sameh <[email protected]> Signed-off-by: Andy Shevchenko <[email protected]>
2019-02-08gpio: crystalcove: Convert to use SPDX identifierAndy Shevchenko1-10/+2
Reduce size of duplicated comments by switching to use SPDX identifier. No functional change. Signed-off-by: Andy Shevchenko <[email protected]> Reviewed-by: Kuppuswamy Sathyanarayanan <[email protected]>
2019-02-08gpio: crystalcove: Sort headers alphabeticallyAndy Shevchenko1-4/+4
Sort header block alphabetically for easy maintenance. Signed-off-by: Andy Shevchenko <[email protected]> Reviewed-by: Kuppuswamy Sathyanarayanan <[email protected]>
2019-02-08gpio: crystalcove: Use for_each_set_bit() in IRQ handlerAndy Shevchenko1-6/+4
This simplifies and standardizes the AB IRQ handler by using the for_each_set_bit() library function. Signed-off-by: Andy Shevchenko <[email protected]> Reviewed-by: Kuppuswamy Sathyanarayanan <[email protected]>
2018-01-14gpio: crystalcove: Include proper headerLinus Walleij1-1/+1
This driver has no business including <linux/gpio.h>, it is a driver so include <linux/gpio/driver.h>. Signed-off-by: Linus Walleij <[email protected]>
2017-11-08gpio: Move irqdomain into struct gpio_irq_chipThierry Reding1-1/+1
In order to consolidate the multiple ways to associate an IRQ chip with a GPIO chip, move more fields into the new struct gpio_irq_chip. Signed-off-by: Thierry Reding <[email protected]> Acked-by: Grygorii Strashko <[email protected]> Signed-off-by: Linus Walleij <[email protected]>
2017-05-23gpio: crystalcove: Do not write regular gpio registers for virtual GPIOsHans de Goede1-18/+36
The Crystal Cove PMIC has 16 real GPIOs but the ACPI code for devices with this PMIC may address up to 95 GPIOs, these extra GPIOs are called virtual GPIOs and are used by the ACPI code as a method of accessing various non GPIO bits of PMIC. Commit dcdc3018d635 ("gpio: crystalcove: support virtual GPIO") added dummy support for these to avoid a bunch of ACPI errors, but instead of ignoring writes / reads to them by doing: if (gpio >= CRYSTALCOVE_GPIO_NUM) return 0; It accidentally introduced the following wrong check: if (gpio > CRYSTALCOVE_VGPIO_NUM) return 0; Which means that attempts by the ACPI code to access these gpios causes some arbitrary gpio to get touched through for example GPIO1P0CTLO + gpionr % 8. Since we do support input/output (but not interrupts) on the 0x5e virtual GPIO, this commit makes to_reg return -ENOTSUPP for unsupported virtual GPIOs so as to not have to check for (gpio >= CRYSTALCOVE_GPIO_NUM && gpio != 0x5e) everywhere and to make it easier to add support for more virtual GPIOs in the future. It then adds a check for to_reg returning an error to all callers where this may happen fixing the ACPI code accessing virtual GPIOs accidentally causing changes to real GPIOs. Fixes: dcdc3018d635 ("gpio: crystalcove: support virtual GPIO") Cc: Aaron Lu <[email protected]> Signed-off-by: Hans de Goede <[email protected]> Reviewed-by: Andy Shevchenko <[email protected]> Signed-off-by: Linus Walleij <[email protected]>
2016-11-25gpio: set explicit nesting on driversLinus Walleij1-0/+2
The ADNP, CrystalCove and WhiskeyCove are all nested GPIO irqchips, but were avoiding to connect the parent IRQ to the gpiochip. This works, but is kind of sloppy as the child IRQs are not marked as having the parent IRQ as parent. Cc: Mika Westerberg <[email protected]> Cc: Ajay Thomas <[email protected]> Cc: Bin Gao <[email protected]> Signed-off-by: Linus Walleij <[email protected]>
2016-11-25gpio: simplify adding threaded interruptsLinus Walleij1-2/+2
This tries to simplify the use of CONFIG_GPIOLIB_IRQCHIP when using threaded interrupts: add a new call gpiochip_irqchip_add_nested() to indicate that we're dealing with a nested rather than a chained irqchip, then create a separate gpiochip_set_nested_irqchip() to mirror the gpiochip_set_chained_irqchip() call to connect the parent and child interrupts. In the nested case gpiochip_set_nested_irqchip() does nothing more than call irq_set_parent() on each valid child interrupt, which has little semantic effect in the kernel, but this is probably still formally correct. Update all drivers using nested interrupts to use gpiochip_irqchip_add_nested() so we can now see clearly which these users are. The DLN2 driver can drop its specific hack with .irq_not_threaded as we now recognize whether a chip is threaded or not from its use of gpiochip_irqchip_add_nested() signature rather than from inspecting .can_sleep. We rename the .irq_parent to .irq_chained_parent since this parent IRQ is only really kept around for the chained interrupt handlers. Cc: Lars Poeschel <[email protected]> Cc: Octavian Purdila <[email protected]> Cc: Daniel Baluta <[email protected]> Cc: Bin Gao <[email protected]> Cc: Mika Westerberg <[email protected]> Cc: Ajay Thomas <[email protected]> Cc: Semen Protsenko <[email protected]> Cc: Alexander Stein <[email protected]> Cc: Phil Reid <[email protected]> Cc: Bartosz Golaszewski <[email protected]> Cc: Patrice Chotard <[email protected]> Signed-off-by: Linus Walleij <[email protected]>
2016-02-23gpio: crystalcove: Use devm_gpiochip_add_data() for gpio registrationLaxman Dewangan1-7/+2
Use devm_gpiochip_add_data() for GPIO registration and remove the call of gpiochip_remove() from error path. Signed-off-by: Laxman Dewangan <[email protected]>
2016-01-05gpio: crystalcove: use gpiochip data pointerLinus Walleij1-16/+16
This makes the driver use the data pointer added to the gpio_chip to store a pointer to the state container instead of relying on container_of(). Cc: Shobhit Kumar <[email protected]> Cc: Zhu, Lejun <[email protected]> Signed-off-by: Linus Walleij <[email protected]>
2015-11-19gpio: change member .dev to .parentLinus Walleij1-1/+1
The name .dev in a struct is normally reserved for a struct device that is let us say a superclass to the thing described by the struct. struct gpio_chip stands out by confusingly using a struct device *dev to point to the parent device (such as a platform_device) that represents the hardware. As we want to give gpio_chip:s real devices, this is not working. We need to rename this member to parent. This was done by two coccinelle scripts, I guess it is possible to combine them into one, but I don't know such stuff. They look like this: @@ struct gpio_chip *var; @@ -var->dev +var->parent and: @@ struct gpio_chip var; @@ -var.dev +var.parent and: @@ struct bgpio_chip *var; @@ -var->gc.dev +var->gc.parent Plus a few instances of bgpio that I couldn't figure out how to teach Coccinelle to rewrite. This patch hits all over the place, but I *strongly* prefer this solution to any piecemal approaches that just exercise patch mechanics all over the place. It mainly hits drivers/gpio and drivers/pinctrl which is my own backyard anyway. Cc: Haavard Skinnemoen <[email protected]> Cc: Rafał Miłecki <[email protected]> Cc: Richard Purdie <[email protected]> Cc: Mauro Carvalho Chehab <[email protected]> Cc: Alek Du <[email protected]> Cc: Jaroslav Kysela <[email protected]> Cc: Takashi Iwai <[email protected]> Acked-by: Dmitry Torokhov <[email protected]> Acked-by: Greg Kroah-Hartman <[email protected]> Acked-by: Lee Jones <[email protected]> Acked-by: Jiri Kosina <[email protected]> Acked-by: Hans-Christian Egtvedt <[email protected]> Acked-by: Jacek Anaszewski <[email protected]> Signed-off-by: Linus Walleij <[email protected]>
2015-06-16gpio: Fix checkpatch.pl issuesDaniel Lockyer1-2/+1
This patch fixes some issues given by checkpatch. Fixes include bracket placement, spacing and indenting. Signed-off-by: Daniel Lockyer <[email protected]> Reviewed-by: Alexandre Courbot <[email protected]> Signed-off-by: Linus Walleij <[email protected]>
2015-06-02gpio: crystalcove: set IRQCHIP_SKIP_SET_WAKE for the irqchipAaron Lu1-0/+1
The CrystalCove GPIO irqchip doesn't have irq_set_wake callback defined so we should set IRQCHIP_SKIP_SET_WAKE for it or it would cause an irq desc's wake_depth unbalanced warning during system resume phase from the gpio_keys driver, which is the driver for the power button of the ASUS T100 laptop. Signed-off-by: Aaron Lu <[email protected]> Cc: <[email protected]> Signed-off-by: Linus Walleij <[email protected]>
2015-05-12drivers/gpio: include <module.h> for modular crystalcove codePaul Gortmaker1-0/+1
This file is built off of a tristate Kconfig option and also contains modular function calls so it should explicitly include module.h to avoid compile breakage during header shuffles done in the future. Cc: Linus Walleij <[email protected]> Cc: Alexandre Courbot <[email protected]> Cc: [email protected] Signed-off-by: Paul Gortmaker <[email protected]> Signed-off-by: Linus Walleij <[email protected]>
2015-03-26gpio/crystalcove: Add additional GPIO for Panel controlShobhit Kumar1-1/+6
Export PANEL_EN/DISABLE (offset 0x52) as additional GPIO. Needed by display driver to enable the DSI panel on BYT platform where the Panel EN/Disable control is routed thorugh CRC PMIC CC: Samuel Ortiz <[email protected]> Cc: Linus Walleij <[email protected]> Cc: Alexandre Courbot <[email protected]> Cc: Thierry Reding <[email protected]> Acked-by: Daniel Vetter <[email protected]> Signed-off-by: Shobhit Kumar <[email protected]> Signed-off-by: Linus Walleij <[email protected]>
2015-01-14gpio: crystalcove: use handle_nested_irqAaron Lu1-1/+1
The CrystalCove GPIO chip has can_sleep set so its demultiplexed irqs will have IRQ_NESTED_THREAD flag set, thus we should use the nested version handle_nested_irq in CrystalCove's irq handler instead of handle_generic_irq, or the following warning will be hit and the functionality is lost: [ 4089.639554] Hardware name: ASUSTeK COMPUTER INC. T100TA/T100TA, BIOS T100TA.313 08/13/2014 [ 4089.639564] 00000002 00000000 c24fbdf4 c16e0257 c24fbe38 c24fbe28 c105390c c18ec480 [ 4089.639596] c24fbe54 00000048 c18f8e3b 00000295 c10a60fc 00000295 c10a60fc f4464540 [ 4089.639626] f446459c c278ad40 c24fbe40 c1053974 00000009 c24fbe38 c18ec480 c24fbe54 [ 4089.639656] Call Trace: [ 4089.639685] [<c16e0257>] dump_stack+0x41/0x52 [ 4089.639707] [<c105390c>] warn_slowpath_common+0x8c/0xc0 [ 4089.639727] [<c10a60fc>] ? irq_nested_primary_handler+0x2c/0x30 [ 4089.639744] [<c10a60fc>] ? irq_nested_primary_handler+0x2c/0x30 [ 4089.639763] [<c1053974>] warn_slowpath_fmt+0x34/0x40 [ 4089.639781] [<c10a60fc>] irq_nested_primary_handler+0x2c/0x30 [ 4089.639800] [<c10a5c56>] handle_irq_event_percpu+0x76/0x190 [ 4089.639818] [<c1461570>] ? regmap_format_10_14_write+0x30/0x30 [ 4089.639836] [<c1464f4c>] ? _regmap_bus_raw_write+0x4c/0x70 [ 4089.639854] [<c10a5da1>] handle_irq_event+0x31/0x50 [ 4089.639872] [<c10a83eb>] handle_simple_irq+0x4b/0x70 [ 4089.639889] [<c10a5384>] generic_handle_irq+0x24/0x40 [ 4089.639908] [<c1366d87>] crystalcove_gpio_irq_handler+0xa7/0xc0 [ 4089.639927] [<c10a85a7>] handle_nested_irq+0x77/0x190 [ 4089.639947] [<c1469801>] regmap_irq_thread+0x1b1/0x360 [ 4089.639966] [<c10a6ae8>] irq_thread_fn+0x18/0x30 [ 4089.639983] [<c10a6906>] irq_thread+0xf6/0x110 [ 4089.640001] [<c10a6ad0>] ? irq_finalize_oneshot.part.30+0x1b0/0x1b0 [ 4089.640019] [<c10a6b50>] ? irq_forced_thread_fn+0x50/0x50 [ 4089.640037] [<c10a6810>] ? irq_thread_check_affinity+0xc0/0xc0 [ 4089.640054] [<c106f389>] kthread+0xa9/0xc0 [ 4089.640074] [<c16e6401>] ret_from_kernel_thread+0x21/0x30 [ 4089.640091] [<c106f2e0>] ? kthread_create_on_node+0x110/0x110 [ 4089.640105] ---[ end trace dca7946ad31eba7d ]--- Buglink: https://bugzilla.kernel.org/show_bug.cgi?id=90521 Reported-and-tested-by: Brian Loften <[email protected]> Cc: Stable <[email protected]> Signed-off-by: Aaron Lu <[email protected]> Signed-off-by: Linus Walleij <[email protected]>
2014-10-20gpio: drop owner assignment from platform_driversWolfram Sang1-1/+0
A platform_driver does not need to set an owner, it will be populated by the driver core. Signed-off-by: Wolfram Sang <[email protected]>
2014-09-25gpio: crystalcove: support virtual GPIOAaron Lu1-3/+16
The virtual GPIO introduced in ACPI table of Baytrail-T based system is used to solve a problem under Windows. We do not have such problems under Linux so we do not actually need them. But we have to tell GPIO library that the Crystal Cove GPIO chip has this many GPIO pins or the common GPIO handler will refuse any access to those high number GPIO pins, which will resulted in a failure evaluation of every ACPI control method that is used to turn on/off power resource and/or report sensor temperatures. Signed-off-by: Aaron Lu <[email protected]> Reviewed-by: Mika Westerberg <[email protected]> [changed vgpio number from 0x5e to 94] Signed-off-by: Linus Walleij <[email protected]>
2014-09-23gpio: remove remaining users of gpiochip_remove() retvalLinus Walleij1-6/+3
Some drivers accidentally still use the return value from gpiochip_remove(). Get rid of them so we can simplify this function and get rid of the return value. Cc: Abdoulaye Berthe <[email protected]> Acked-by: Alexandre Courbot <[email protected]> Acked-by: Javier Martinez Canillas <[email protected]> Signed-off-by: Linus Walleij <[email protected]>
2014-06-19gpio: crystalcove: Fix implicit declaration of function 'seq_printf' errorLee Jones1-0/+1
drivers/gpio/gpio-crystalcove.c: In function 'crystalcove_gpio_dbg_show': drivers/gpio/gpio-crystalcove.c:286:3: error: implicit declaration of function 'seq_printf' seq_printf(s, " gpio-%-2d %s %s %s %s ctlo=%2x,%s %s %s\n", Reported-by: Stephen Rothwell <[email protected]> Acked-by: Alexandre Courbot <[email protected]> Signed-off-by: Lee Jones <[email protected]>
2014-06-17gpio: Add support for Intel Crystal Cove PMICZhu, Lejun1-0/+379
Devices based on Intel SoC products such as Baytrail have a Power Management IC. In the PMIC there are subsystems for voltage regulation, A/D conversion, GPIO and PWMs. The PMIC in Baytrail-T platform is called Crystal Cove. This patch adds support for the GPIO function in Crystal Cove. Signed-off-by: Yang, Bin <[email protected]> Signed-off-by: Zhu, Lejun <[email protected]> Reviewed-by: Mika Westerberg <[email protected]> Reviewed-by: Alexandre Courbot <[email protected]> Reviewed-by: Linus Walleij <[email protected]> Signed-off-by: Lee Jones <[email protected]>
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