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2017-07-17fpga manager: Add Altera CvP driverAnatolij Gustschin3-0/+508
Add FPGA manager driver for loading Arria-V/Cyclone-V/Stratix-V and Arria-10 FPGAs via CvP. Signed-off-by: Anatolij Gustschin <[email protected]> Reviewed-by: Andy Shevchenko <[email protected]> Signed-off-by: Alan Tull <[email protected]> Signed-off-by: Greg Kroah-Hartman <[email protected]>
2017-07-17fpga-manager: altera-ps-spi: use bitrev8x4Joshua Clayton1-4/+15
Speed up bit reversal by using hardware bit reversal Add extra code to handle less than 4byte remnants, if any Signed-off-by: Joshua Clayton <[email protected]> Signed-off-by: Alan Tull <[email protected]> Signed-off-by: Greg Kroah-Hartman <[email protected]>
2017-07-17fpga manager: Add altera-ps-spi driver for Altera FPGAsJoshua Clayton3-0/+305
altera-ps-spi loads FPGA firmware over SPI, using the "passive serial" interface on Altera Arria 10, Cyclone V or Stratix V FPGAs. This is one of the simpler ways to set up an FPGA at runtime. The signal interface is close to unidirectional SPI with lsb first. Signed-off-by: Joshua Clayton <[email protected]> Signed-off-by: Anatolij Gustschin <[email protected]> Signed-off-by: Alan Tull <[email protected]> Signed-off-by: Greg Kroah-Hartman <[email protected]>
2017-07-17Make FPGA a menuconfig to ease disabling it allVincent Legoll1-5/+1
No need to get into the submenu to disable all FPGA-related config entries Signed-off-by: Vincent Legoll <[email protected]> Acked-by: Moritz Fischer <[email protected]> Signed-off-by: Alan Tull <[email protected]> Signed-off-by: Greg Kroah-Hartman <[email protected]>
2017-04-26fpga fr br: update supported version numbersMatthew Gerlach1-11/+19
The value in the version register of the altera freeze bridge controller changed from the beta value of 2 to the value of 0xad000003 in the official release of the IP. This patch supports the old and new version numbers, and the driver's probe function will fail if neither of the supported versions is found. Signed-off-by: Matthew Gerlach <[email protected]> Reviewed-by: Moritz Fischer <[email protected]> Signed-off-by: Alan Tull <[email protected]> Signed-off-by: Greg Kroah-Hartman <[email protected]>
2017-04-26fpga: region: release FPGA region reference in error pathTobias Klauser1-1/+3
If fpga_region_get_manager() fails in fpga_region_program_fpga(), a reference to the fpga_manager instance previously acquired through fpga_region_get() is retained. Make sure to properly release it in the error case by using a separate jump label which will call fpga_region_put() in before returning. Signed-off-by: Tobias Klauser <[email protected]> Acked-by: Moritz Fischer <[email protected]> Signed-off-by: Alan Tull <[email protected]> Signed-off-by: Greg Kroah-Hartman <[email protected]>
2017-04-26fpga altera-hps2fpga: disable/unprepare clock on error in ↵Tobias Klauser1-6/+9
alt_fpga_bridge_probe() If either _alt_hps2fpga_enable_set() or fpga_bridge_register() fail in alt_fpga_bridge_probe(), the clock remains enabled and prepared. Also, in the error path for _alt_hps2fpga_enable_set() a call to fpga_bridge_unregister() is made even though the bridge was not registered yet. Remove the unnecessary call to fpga_bridge_unregister() and call clk_disable_unprepare() in both error paths in order to make sure the clock gets properly disabled and unprepared. Signed-off-by: Tobias Klauser <[email protected]> Acked-by: Moritz Fischer <[email protected]> Signed-off-by: Alan Tull <[email protected]> Signed-off-by: Greg Kroah-Hartman <[email protected]>
2017-04-08fpga: Add support for Xilinx LogiCORE PR DecouplerMoritz Fischer3-0/+172
This adds support for the Xilinx LogiCORE PR Decoupler soft-ip that does decoupling of PR regions in the FPGA fabric during partial reconfiguration. Signed-off-by: Moritz Fischer <[email protected]> Signed-off-by: Michal Simek <[email protected]> Cc: Sören Brinkmann <[email protected]> Cc: [email protected] Cc: [email protected] Acked-by: Alan Tull <[email protected]> Signed-off-by: Greg Kroah-Hartman <[email protected]>
2017-04-08fpga pr ip: Platform driver for Altera Partial Reconfiguration IP.Matthew Gerlach3-0/+76
This adds a platform bus driver for a fpga-mgr driver that uses the Altera Partial Reconfiguration IP component. Signed-off-by: Matthew Gerlach <[email protected]> Acked-by: Alan Tull <[email protected]> Signed-off-by: Greg Kroah-Hartman <[email protected]>
2017-04-08fpga pr ip: Core driver support for Altera Partial Reconfiguration IP.Matthew Gerlach3-0/+226
Adding the core functions necessary for a fpga-mgr driver for the Altera Partial IP component. It is intended for these functions to be used by the various bus implementations like the platform bus or the PCIe bus. Signed-off-by: Matthew Gerlach <[email protected]> Acked-by: Alan Tull <[email protected]> Signed-off-by: Greg Kroah-Hartman <[email protected]>
2017-04-08fpga: add config complete timeoutAlan Tull1-0/+3
Adding timeout for maximum allowed time for FPGA to go to operating mode after a FPGA region has been programmed. Signed-off-by: Alan Tull <[email protected]> Signed-off-by: Greg Kroah-Hartman <[email protected]>
2017-04-08fpga manager: Add Xilinx slave serial SPI driverAnatolij Gustschin3-0/+206
The driver loads FPGA firmware over SPI, using the "slave serial" configuration interface on Xilinx FPGAs. Signed-off-by: Anatolij Gustschin <[email protected]> Acked-by: Michal Simek <[email protected]> Reviewed-by: Moritz Fischer <[email protected]> Acked-by: Alan Tull <[email protected]> Signed-off-by: Greg Kroah-Hartman <[email protected]>
2017-04-08fpga: altera_freeze_bridge: Constify opsMoritz Fischer1-1/+1
The ops are not changing, make them const. Signed-off-by: Moritz Fischer <[email protected]> Cc: Alan Tull <[email protected]> Cc: [email protected] Cc: [email protected] Acked-by: Alan Tull <[email protected]> Signed-off-by: Greg Kroah-Hartman <[email protected]>
2017-03-17fpga: bridge: Replace open-coded list_for_each + list_entryMoritz Fischer1-11/+4
Replaces open-coded list_for_each() + list_entry() with macro list_for_each_entry() Signed-off-by: Moritz Fischer <[email protected]> Cc: [email protected] Cc: [email protected] Acked-by: Alan Tull <[email protected]> Signed-off-by: Greg Kroah-Hartman <[email protected]>
2017-03-17fpga: Add support for Lattice iCE40 FPGAsJoel Holdsworth3-0/+214
This patch adds support to the FPGA manager for configuring the SRAM of iCE40LM, iCE40LP, iCE40HX, iCE40 Ultra, iCE40 UltraLite and iCE40 UltraPlus devices, through slave SPI. Signed-off-by: Joel Holdsworth <[email protected]> Reviewed-by: Marek Vasut <[email protected]> Reviewed-by: Moritz Fischer <[email protected]> Acked-by: Alan Tull <[email protected]> Signed-off-by: Greg Kroah-Hartman <[email protected]>
2017-03-17FPGA: Add TS-7300 FPGA managerFlorian Fainelli3-0/+164
Add support for loading bitstreams on the Altera Cyclone II FPGA populated on the TS-7300 board. This is done through the configuration and data registers offered through a memory interface between the EP93xx SoC and the FPGA via an intermediate CPLD device. The EP93xx SoC on the TS-7300 does not have direct means of configuring the on-board FPGA other than by using the special memory mapped interface to the CPLD. No other entity on the system can control the FPGA bitstream. Signed-off-by: Florian Fainelli <[email protected]> Acked-by: Alan Tull <[email protected]> Acked-by: Moritz Fischer <[email protected]> Signed-off-by: Greg Kroah-Hartman <[email protected]>
2017-03-17fpga: region: Add fpga-region property 'encrypted-fpga-config'Moritz Fischer1-2/+6
Add fpga-region property to allow passing the fact that the bitstream is encrypted to the fpga-region and ultimately to the low-level driver. Signed-off-by: Moritz Fischer <[email protected]> Acked-by: Michal Simek <[email protected]> Signed-off-by: Alan Tull <[email protected]> Signed-off-by: Greg Kroah-Hartman <[email protected]>
2017-03-17fpga: zynq: Add support for encrypted bitstreamsMoritz Fischer1-3/+25
Add support for encrypted bitstreams. For this to work the system must be booted in secure mode. In order for on-the-fly decryption to work, the PCAP clock rate needs to be lowered via the PCAP_RATE_EN bit. Signed-off-by: Moritz Fischer <[email protected]> Acked-by: Michal Simek <[email protected]> Signed-off-by: Alan Tull <[email protected]> Signed-off-by: Greg Kroah-Hartman <[email protected]>
2017-03-17fpga: fix sparse warnings in fpga-mgr and fpga-bridgeDinh Nguyen2-2/+2
Fix up these sparse warnings: drivers/fpga/fpga-mgr.c:189:21: warning: symbol '__fpga_mgr_get' was not declared. Should it be static? drivers/fpga/fpga-bridge.c:30:12: warning: symbol 'bridge_list_lock' was not declared. Should it be static? Signed-off-by: Dinh Nguyen <[email protected]> Acked-by: Moritz Fischer <[email protected]> Signed-off-by: Alan Tull <[email protected]> Signed-off-by: Greg Kroah-Hartman <[email protected]>
2017-02-10fpga zynq: Use the scatterlist interfaceJason Gunthorpe1-39/+135
This allows the driver to avoid a high order coherent DMA allocation and memory copy. With this patch it can DMA directly from the kernel pages that the bitfile is stored in. Since this is now a gather DMA operation the driver uses the ISR to feed the chips DMA queue with each entry from the SGL. Signed-off-by: Jason Gunthorpe <[email protected]> Acked-by: Moritz Fischer <[email protected]> Signed-off-by: Greg Kroah-Hartman <[email protected]>
2017-02-10fpga: Add scatterlist based programmingJason Gunthorpe1-30/+206
Requiring contiguous kernel memory is not a good idea, this is a limited resource and allocation can fail under normal work loads. This introduces a .write_sg op that supporting drivers can provide to DMA directly from dis-contiguous memory and a new entry point fpga_mgr_buf_load_sg that users can call to directly provide page lists. The full matrix of compatibility is provided, either the linear or sg interface can be used by the user with a driver supporting either interface. A notable change for drivers is that the .write op can now be called multiple times. Signed-off-by: Jason Gunthorpe <[email protected]> Acked-by: Alan Tull <[email protected]> Acked-by: Moritz Fischer <[email protected]> Signed-off-by: Greg Kroah-Hartman <[email protected]>
2017-02-10fpga zynq: Check the bitstream for validityJason Gunthorpe1-0/+21
There is no sense in sending a bitstream we know will not work, and with the variety of options for bitstream generation in Xilinx tools it is not terribly clear what the correct input should be. This is particularly important for Zynq since auto-correction was removed from the driver and the Zynq hardware only accepts a bitstream format that is different from what the Xilinx tools typically produce. Worse, the hardware provides no indication why the bitstream fails, it simply times out if the input is wrong. The best option here is to have the kernel print a message informing the user they are using a malformed bistream and programming failure isn't for any of the myriad of other reasons. Signed-off-by: Jason Gunthorpe <[email protected]> Acked-by: Moritz Fischer <[email protected]> Acked-by: Alan Tull <[email protected]> Signed-off-by: Greg Kroah-Hartman <[email protected]>
2017-02-10fpga zynq: Check for errors after completing DMAJason Gunthorpe1-22/+32
The completion did not check the interrupt status to see if any error bits were asserted, check error bits and dump some registers if things went wrong. A few fixes are needed to make this work, the IXR_ERROR_FLAGS_MASK was wrong, it included the done bits, which shows a bug in mask/unmask_irqs which were using the wrong bits, simplify all of this stuff. Signed-off-by: Jason Gunthorpe <[email protected]> Reviewed-by: Moritz Fischer <[email protected]> Acked-by: Alan Tull <[email protected]> Signed-off-by: Greg Kroah-Hartman <[email protected]>
2016-11-29fpga: Clarify how write_init works streaming modesJason Gunthorpe2-2/+5
This interface was designed for streaming, but write_init's buf argument has an unclear purpose. Define it to be the first bytes of the bitstream. Each driver gets to set how many bytes (at most) it wants to see. Short bitstreams will be passed through as-is, while long ones will be truncated. The intent is to allow drivers to peek at the header before the transfer actually starts. Signed-off-by: Jason Gunthorpe <[email protected]> Acked-by: Alan Tull <[email protected]>
2016-11-29fpga zynq: Fix incorrect ISR state on bootupJason Gunthorpe1-7/+10
It is best practice to clear and mask all interrupts before associating the IRQ, and this should be done after the clock is enabled. This corrects a bad result from zynq_fpga_ops_state on bootup where left over latched values in INT_STS_OFFSET caused it to report an unconfigured FPGA as configured. After this change the boot up operating state for an unconfigured FPGA reports 'unknown'. Signed-off-by: Jason Gunthorpe <[email protected]> Acked-by: Alan Tull <[email protected]> Acked-by: Moritz Fischer <[email protected]>
2016-11-29fpga zynq: Remove priv->devJason Gunthorpe1-11/+8
socfpga uses mgr->dev for debug prints, there should be consistency here, so standardize on that. The only other use was for dma which can be replaced with mgr->dev.parent. Signed-off-by: Jason Gunthorpe <[email protected]> Acked-by: Alan Tull <[email protected]> Acked-by: Moritz Fischer <[email protected]>
2016-11-29fpga zynq: Add missing \n to messagesJason Gunthorpe1-11/+11
Function dev_err doesn't add a newline at the end of the string. This will lead to a hard to read kernel log. Signed-off-by: Jason Gunthorpe <[email protected]> Reviewed-by: Moritz Fischer <[email protected]> Reviewed-by: Matthias Brugger <[email protected]> Acked-by: Alan Tull <[email protected]>
2016-11-29fpga: Add COMPILE_TEST to all driversJason Gunthorpe1-2/+3
Like Zynq the Altera drivers compile fine on x86 and others too, so make it easier to compile test this stuff. A10 requires REGMAP_MMIO to compile, so be explicit rather than relying on it via ARCH_SOCFPGA. Signed-off-by: Jason Gunthorpe <[email protected]> Acked-by: Alan Tull <[email protected]>
2016-11-17ARM: socfpga: checking the wrong variableDan Carpenter1-1/+1
This is a cut and paste bug. We had intended to check "sysmgr". Fixes: e5f8efa5c8bf ("ARM: socfpga: fpga bridge driver support") Signed-off-by: Dan Carpenter <[email protected]> Acked-by: Moritz Fischer <[email protected]> Acked-by: Alan Tull <[email protected]> Signed-off-by: Greg Kroah-Hartman <[email protected]>
2016-11-10fpga-manager: Add Socfpga Arria10 supportAlan Tull3-0/+563
Add low level driver to support reprogramming FPGAs for Altera SoCFPGA Arria10. Signed-off-by: Alan Tull <[email protected]> Reviewed-by: Moritz Fischer <[email protected]> Signed-off-by: Greg Kroah-Hartman <[email protected]>
2016-11-10fpga: add altera freeze bridge supportAlan Tull3-0/+283
Add a low level driver for Altera Freeze Bridges to the FPGA Bridge framework. A freeze bridge is a bridge that exists in the FPGA fabric to isolate one region of the FPGA from the busses while that one region is being reprogrammed. Signed-off-by: Alan Tull <[email protected]> Signed-off-by: Matthew Gerlach <[email protected]> Signed-off-by: Greg Kroah-Hartman <[email protected]>
2016-11-10ARM: socfpga: fpga bridge driver supportAlan Tull4-0/+410
Supports Altera SOCFPGA bridges: * fpga2sdram * fpga2hps * hps2fpga * lwhps2fpga Allows enabling/disabling the bridges through the FPGA Bridge Framework API functions. The fpga2sdram driver only supports enabling and disabling of the ports that been configured early on. This is due to a hardware limitation where the read, write, and command ports on the fpga2sdram bridge can only be reconfigured while there are no transactions to the sdram, i.e. when running out of OCRAM before the kernel boots. Device tree property 'init-val' configures the driver to enable or disable the bridge during probe. If the property does not exist, the driver will leave the bridge in its current state. Signed-off-by: Alan Tull <[email protected]> Signed-off-by: Matthew Gerlach <[email protected]> Signed-off-by: Dinh Nguyen <[email protected]> Signed-off-by: Greg Kroah-Hartman <[email protected]>
2016-11-10fpga: fpga-region: device tree control for FPGAAlan Tull3-0/+613
FPGA Regions support programming FPGA under control of the Device Tree. Signed-off-by: Alan Tull <[email protected]> Signed-off-by: Greg Kroah-Hartman <[email protected]>
2016-11-10fpga: add fpga bridge frameworkAlan Tull3-0/+405
This framework adds API functions for enabling/ disabling FPGA bridges under kernel control. This allows the Linux kernel to disable FPGA bridges during FPGA reprogramming and to enable FPGA bridges when FPGA reprogramming is done. This framework is be manufacturer-agnostic, allowing it to be used in interfaces that use the FPGA Manager Framework to reprogram FPGA's. The functions are: * of_fpga_bridge_get * fpga_bridge_put Get/put an exclusive reference to a FPGA bridge. * fpga_bridge_enable * fpga_bridge_disable Enable/Disable traffic through a bridge. * fpga_bridge_register * fpga_bridge_unregister Register/unregister a device-specific low level FPGA Bridge driver. Get an exclusive reference to a bridge and add it to a list: * fpga_bridge_get_to_list To enable/disable/put a set of bridges that are on a list: * fpga_bridges_enable * fpga_bridges_disable * fpga_bridges_put Signed-off-by: Alan Tull <[email protected]> Signed-off-by: Greg Kroah-Hartman <[email protected]>
2016-11-10fpga-mgr: add fpga image information structAlan Tull3-15/+19
This patch adds a minor change in the FPGA Manager API to hold information that is specific to an FPGA image file. This change is expected to bring little, if any, pain. The socfpga and zynq drivers are fixed up in this patch. An FPGA image file will have particulars that affect how the image is programmed to the FPGA. One example is that current 'flags' currently has one bit which shows whether the FPGA image was built for full reconfiguration or partial reconfiguration. Another example is timeout values for enabling or disabling the bridges in the FPGA. As the complexity of the FPGA design increases, the bridges in the FPGA may take longer times to enable or disable. This patch adds a new 'struct fpga_image_info', moves the current 'u32 flags' to it. Two other image-specific u32's are added for the bridge enable/disable timeouts. The FPGA Manager API functions are changed, replacing the 'u32 flag' parameter with a pointer to struct fpga_image_info. Subsequent patches fix the existing low level FPGA manager drivers. Signed-off-by: Alan Tull <[email protected]> Acked-by: Moritz Fischer <[email protected]> Signed-off-by: Greg Kroah-Hartman <[email protected]>
2016-11-10fpga: add method to get fpga manager from deviceAlan Tull1-22/+54
The intent is to provide a non-DT method of getting ahold of a FPGA manager to do some FPGA programming. This patch refactors of_fpga_mgr_get() to reuse most of it while adding a new method fpga_mgr_get() for getting a pointer to a fpga manager struct, given the device. Signed-off-by: Alan Tull <[email protected]> Signed-off-by: Greg Kroah-Hartman <[email protected]>
2016-09-08fpga manager: Add hardware dependency to Zynq driverJean Delvare1-0/+1
The Zynq FPGA manager driver serves no purpose on other architectures so hide it unless build-testing. Signed-off-by: Jean Delvare <[email protected]> Acked-by: Moritz Fischer <[email protected]> Acked-by: Alan Tull <[email protected]> Acked-by: Michal Simek <[email protected]> Cc: "Sören Brinkmann" <[email protected]> Signed-off-by: Greg Kroah-Hartman <[email protected]>
2016-08-04drivers/fpga/Kconfig: fix build failureSudip Mukherjee1-0/+1
While building m32r allmodconfig the build is failing with the error: ERROR: "bad_dma_ops" [drivers/fpga/zynq-fpga.ko] undefined! Xilinx Zynq FPGA is using DMA but there was no dependency while building. Link: http://lkml.kernel.org/r/[email protected] Signed-off-by: Sudip Mukherjee <[email protected]> Acked-by: Moritz Fischer <[email protected]> Cc: Alan Tull <[email protected]> Signed-off-by: Andrew Morton <[email protected]> Signed-off-by: Linus Torvalds <[email protected]>
2015-11-24fpga manager: Fix firmware resource leak on errorTobias Klauser1-3/+1
If fpga_mgr_buf_load() fails, the firmware resource previously allocated by request_firmware() is leaked. Fix it by calling release_firmware() regardless of the return value of fpga_mgr_buf_load(). Found by the Coverity scanner (CID 1339653). Fixes: 6a8c3be7ec8e ("add FPGA manager core") Signed-off-by: Tobias Klauser <[email protected]> Acked-by: Alan Tull <[email protected]> Signed-off-by: Greg Kroah-Hartman <[email protected]>
2015-11-24fpga manager: remove labelAlan Tull1-6/+3
Remove implementation of 'label' DT binding. Signed-off-by: Alan Tull <[email protected]> Reviewed-by: Moritz Fischer <[email protected]> Signed-off-by: Greg Kroah-Hartman <[email protected]>
2015-10-29fpga: socfpga: Fix check of return value of devm_request_irqMoritz Fischer1-1/+1
The return value should be checked for non-zero, instead of checking it being IS_ERR_VALUE(). Acked-by: Alan Tull <[email protected]> Reviewed-by: Josh Cartwright <[email protected]> Signed-off-by: Moritz Fischer <[email protected]> Signed-off-by: Greg Kroah-Hartman <[email protected]>
2015-10-23fpga: zynq-fpga: Fix issue with drvdata being overwritten.Moritz Fischer1-3/+4
Upon registering a FPGA Manager low level driver, FPGA Manager core overwrites the platform drvdata pointer. Prior to this commit zynq-fpga falsely relied on this pointer to still be valid at remove() time. Reported-by: Alan Tull <[email protected]> Signed-off-by: Moritz Fischer <[email protected]> Acked-by: Alan Tull <[email protected]> Signed-off-by: Greg Kroah-Hartman <[email protected]>
2015-10-23fpga manager: remove unnecessary null pointer checksAlan Tull1-8/+4
Remove unnecessary null pointer checks. We want the caller of these functions to do their own pointer checks. Add some comments to document this. Signed-off-by: Alan Tull <[email protected]> Reviewed-by: Moritz Fischer <[email protected]> Signed-off-by: Greg Kroah-Hartman <[email protected]>
2015-10-23fpga manager: ensure lifetime with of_fpga_mgr_getAlan Tull1-15/+17
Ensure device and driver lifetime from of_fpga_mgr_get() to fpga_mgr_put(). * Don't put_device() in of_fpga_mgr_get, do it in fpga_mgr_put(). (still do put_device if there is an error). * Do module_get on the low level driver. * Don't need to module_get(THIS_MODULE) since we won't be allowed to unload the fpga manager core without unloading low level driver first. * Remove unnedessary null check for node pointer. Signed-off-by: Alan Tull <[email protected]> Signed-off-by: Greg Kroah-Hartman <[email protected]>
2015-10-23fpga: zynq-fpga: Change fw format to handle bin instead of bit.Moritz Fischer1-22/+2
This gets rid of the code to strip away the header and byteswap, as well as the check for the sync word. Signed-off-by: Moritz Fischer <[email protected]> Reviewed-by: Josh Cartwright <[email protected]> Acked-by: Michal Simek <[email protected]> Signed-off-by: Greg Kroah-Hartman <[email protected]>
2015-10-23fpga: zynq-fpga: Fix unbalanced clock handlingMoritz Fischer1-2/+2
This commit fixes the unbalanced clock handling, where a failed probe would leave the clock with an enable count of -1. Reported-by: Josh Cartwright <[email protected]> Signed-off-by: Moritz Fischer <[email protected]> Signed-off-by: Greg Kroah-Hartman <[email protected]>
2015-10-17fpga manager: Adding FPGA Manager support for Xilinx Zynq 7000Moritz Fischer3-0/+539
This commit adds FPGA Manager support for the Xilinx Zynq chip. The code borrows some from the xdevcfg driver in Xilinx' vendor tree. Signed-off-by: Moritz Fischer <[email protected]> Signed-off-by: Greg Kroah-Hartman <[email protected]>
2015-10-07fpga manager: add driver for socfpga fpga managerAlan Tull3-0/+627
Add driver to fpga manager framework to allow configuration of FPGA in Altera SoCFPGA parts. Signed-off-by: Alan Tull <[email protected]> Acked-by: Michal Simek <[email protected]> Acked-by: Moritz Fischer <[email protected]> Signed-off-by: Greg Kroah-Hartman <[email protected]>
2015-10-07add FPGA manager coreAlan Tull3-0/+404
API to support programming FPGA's. The following functions are exported as GPL: * fpga_mgr_buf_load Load fpga from image in buffer * fpga_mgr_firmware_load Request firmware and load it to the FPGA. * fpga_mgr_register * fpga_mgr_unregister FPGA device drivers can be added by calling fpga_mgr_register() to register a set of fpga_manager_ops to do device specific stuff. * of_fpga_mgr_get * fpga_mgr_put Get/put a reference to a fpga manager. The following sysfs files are created: * /sys/class/fpga_manager/<fpga>/name Name of low level driver. * /sys/class/fpga_manager/<fpga>/state State of fpga manager Signed-off-by: Alan Tull <[email protected]> Acked-by: Michal Simek <[email protected]> Signed-off-by: Greg Kroah-Hartman <[email protected]>
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