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This gets rid of the code to strip away the header and byteswap,
as well as the check for the sync word.
Signed-off-by: Moritz Fischer <[email protected]>
Reviewed-by: Josh Cartwright <[email protected]>
Acked-by: Michal Simek <[email protected]>
Signed-off-by: Greg Kroah-Hartman <[email protected]>
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This commit fixes the unbalanced clock handling, where
a failed probe would leave the clock with an enable count of -1.
Reported-by: Josh Cartwright <[email protected]>
Signed-off-by: Moritz Fischer <[email protected]>
Signed-off-by: Greg Kroah-Hartman <[email protected]>
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This commit adds FPGA Manager support for the Xilinx Zynq chip.
The code borrows some from the xdevcfg driver in Xilinx'
vendor tree.
Signed-off-by: Moritz Fischer <[email protected]>
Signed-off-by: Greg Kroah-Hartman <[email protected]>
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Add driver to fpga manager framework to allow configuration
of FPGA in Altera SoCFPGA parts.
Signed-off-by: Alan Tull <[email protected]>
Acked-by: Michal Simek <[email protected]>
Acked-by: Moritz Fischer <[email protected]>
Signed-off-by: Greg Kroah-Hartman <[email protected]>
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API to support programming FPGA's.
The following functions are exported as GPL:
* fpga_mgr_buf_load
Load fpga from image in buffer
* fpga_mgr_firmware_load
Request firmware and load it to the FPGA.
* fpga_mgr_register
* fpga_mgr_unregister
FPGA device drivers can be added by calling
fpga_mgr_register() to register a set of
fpga_manager_ops to do device specific stuff.
* of_fpga_mgr_get
* fpga_mgr_put
Get/put a reference to a fpga manager.
The following sysfs files are created:
* /sys/class/fpga_manager/<fpga>/name
Name of low level driver.
* /sys/class/fpga_manager/<fpga>/state
State of fpga manager
Signed-off-by: Alan Tull <[email protected]>
Acked-by: Michal Simek <[email protected]>
Signed-off-by: Greg Kroah-Hartman <[email protected]>
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