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path: root/drivers/fpga/xilinx-spi.c
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2020-12-01fpga: fpga-mgr: xilinx-spi: Simplify registrationMoritz Fischer1-13/+1
Simplify registration using new devm_fpga_mgr_register() API. Reviewed-by: Tom Rix <[email protected]> Signed-off-by: Moritz Fischer <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Greg Kroah-Hartman <[email protected]>
2020-08-30fpga manager: xilinx-spi: provide better diagnostics on programming failureLuca Ceresoli1-1/+15
When the DONE pin does not go high after programming to confirm programming success, the INIT_B pin provides some info on the reason. Use it if available to provide a more explanatory error message. Reviewed-by: Tom Rix <[email protected]> Signed-off-by: Luca Ceresoli <[email protected]> Signed-off-by: Moritz Fischer <[email protected]>
2020-08-30fpga manager: xilinx-spi: add error checking after gpiod_get_value()Luca Ceresoli1-8/+27
Current code calls gpiod_get_value() without error checking. Should the GPIO controller fail, execution would continue without any error message. Fix by checking for negative error values. Reported-by: Tom Rix <[email protected]> Reviewed-by: Tom Rix <[email protected]> Signed-off-by: Luca Ceresoli <[email protected]> Signed-off-by: Moritz Fischer <[email protected]>
2020-08-30fpga manager: xilinx-spi: fix write_complete timeout handlingLuca Ceresoli1-8/+15
If this routine sleeps because it was scheduled out, it might miss DONE going asserted and consider it a timeout. This would potentially make the code return an error even when programming succeeded. Rewrite the loop to always check DONE after checking if timeout expired so this cannot happen anymore. While there, also add error checking for gpiod_get_value(). Also avoid checking the DONE GPIO in two places, which would make the error-checking code duplicated and more annoying. The new loop it written to still guarantee that we apply 8 extra CCLK cycles after DONE has gone asserted, which is required by the hardware. Reported-by: Tom Rix <[email protected]> Reviewed-by: Tom Rix <[email protected]> Signed-off-by: Luca Ceresoli <[email protected]> Signed-off-by: Moritz Fischer <[email protected]>
2020-08-30fpga manager: xilinx-spi: remove final dot from dev_err() stringsLuca Ceresoli1-2/+2
Most dev_err messages in this file have no final dot. Remove the only two exceptions to make them consistent. Reviewed-by: Tom Rix <[email protected]> Signed-off-by: Luca Ceresoli <[email protected]> Signed-off-by: Moritz Fischer <[email protected]>
2020-08-19fpga manager: xilinx-spi: remove stray commentLuca Ceresoli1-1/+0
Remove comment committed by mistake. Fixes: dd2784c01d93 ("fpga manager: xilinx-spi: check INIT_B pin during write_init") Signed-off-by: Luca Ceresoli <[email protected]> Signed-off-by: Moritz Fischer <[email protected]>
2020-06-26fpga manager: xilinx-spi: check INIT_B pin during write_initLuca Ceresoli1-1/+54
The INIT_B pin reports the status during startup and after the end of the programming process. However the current driver completely ignores it. Check the pin status during startup to make sure programming is never started too early and also to detect any hardware issues in the FPGA connection. This is optional for backward compatibility. If INIT_B is not passed by device tree, just fallback to the old udelays. Signed-off-by: Luca Ceresoli <[email protected]> Signed-off-by: Moritz Fischer <[email protected]>
2020-06-18fpga manager: xilinx-spi: remove unneeded, mistyped variablesLuca Ceresoli1-4/+2
Using variables does not add readability here: parameters passed to udelay*() are obviously in microseconds and their meaning is clear from the context. The type is also wrong, udelay expects an unsigned long. Signed-off-by: Luca Ceresoli <[email protected]> Signed-off-by: Moritz Fischer <[email protected]>
2020-06-18fpga manager: xilinx-spi: valid for the 7 Series tooLuca Ceresoli1-1/+1
The Xilinx 7-series uses the same protocol, mention that. Signed-off-by: Luca Ceresoli <[email protected]> Signed-off-by: Moritz Fischer <[email protected]>
2019-06-05treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 422Thomas Gleixner1-4/+1
Based on 1 normalized pattern(s): this program is free software you can redistribute it and or modify it under the terms and conditions of the gnu general public license version 2 as published by the free software foundation extracted by the scancode license scanner the SPDX license identifier GPL-2.0-only has been chosen to replace the boilerplate/reference in 101 file(s). Signed-off-by: Thomas Gleixner <[email protected]> Reviewed-by: Allison Randal <[email protected]> Cc: [email protected] Link: https://lkml.kernel.org/r/[email protected] Signed-off-by: Greg Kroah-Hartman <[email protected]>
2018-10-16fpga: mgr: add devm_fpga_mgr_createAlan Tull1-8/+4
Add devm_fpga_mgr_create() which is the managed version of fpga_mgr_create(). Change current FPGA manager drivers to use devm_fpga_mgr_create() Signed-off-by: Alan Tull <[email protected]> Suggested-by: Federico Vaga <[email protected]> Acked-by: Moritz Fischer <[email protected]> Signed-off-by: Greg Kroah-Hartman <[email protected]>
2018-05-25fpga: manager: change api, don't use drvdataAlan Tull1-3/+17
Change fpga_mgr_register to not set or use drvdata. This supports the case where a PCIe device has more than one manager. Add fpga_mgr_create/free functions. Change fpga_mgr_register and fpga_mgr_unregister functions to take the mgr struct as their only parameter. struct fpga_manager *fpga_mgr_create(struct device *dev, const char *name, const struct fpga_manager_ops *mops, void *priv); void fpga_mgr_free(struct fpga_manager *mgr); int fpga_mgr_register(struct fpga_manager *mgr); void fpga_mgr_unregister(struct fpga_manager *mgr); Update the drivers that call fpga_mgr_register with the new API. Signed-off-by: Alan Tull <[email protected]> [Moritz: Fixup whitespace issue] Reported-by: Jiuyue Ma <[email protected]> Signed-off-by: Moritz Fischer <[email protected]> Signed-off-by: Greg Kroah-Hartman <[email protected]>
2017-04-08fpga manager: Add Xilinx slave serial SPI driverAnatolij Gustschin1-0/+198
The driver loads FPGA firmware over SPI, using the "slave serial" configuration interface on Xilinx FPGAs. Signed-off-by: Anatolij Gustschin <[email protected]> Acked-by: Michal Simek <[email protected]> Reviewed-by: Moritz Fischer <[email protected]> Acked-by: Alan Tull <[email protected]> Signed-off-by: Greg Kroah-Hartman <[email protected]>
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