| Age | Commit message (Collapse) | Author | Files | Lines |
|---|
|
Add devm_fpga_mgr_create() which is the managed
version of fpga_mgr_create().
Change current FPGA manager drivers to use
devm_fpga_mgr_create()
Signed-off-by: Alan Tull <[email protected]>
Suggested-by: Federico Vaga <[email protected]>
Acked-by: Moritz Fischer <[email protected]>
Signed-off-by: Greg Kroah-Hartman <[email protected]>
|
|
Change fpga_mgr_register to not set or use drvdata. This supports
the case where a PCIe device has more than one manager.
Add fpga_mgr_create/free functions. Change fpga_mgr_register and
fpga_mgr_unregister functions to take the mgr struct as their only
parameter.
struct fpga_manager *fpga_mgr_create(struct device *dev,
const char *name,
const struct fpga_manager_ops *mops,
void *priv);
void fpga_mgr_free(struct fpga_manager *mgr);
int fpga_mgr_register(struct fpga_manager *mgr);
void fpga_mgr_unregister(struct fpga_manager *mgr);
Update the drivers that call fpga_mgr_register with the new API.
Signed-off-by: Alan Tull <[email protected]>
[Moritz: Fixup whitespace issue]
Reported-by: Jiuyue Ma <[email protected]>
Signed-off-by: Moritz Fischer <[email protected]>
Signed-off-by: Greg Kroah-Hartman <[email protected]>
|
|
If the driver module is loaded when FPGA is configured, the FPGA
is reset because nconfig is pulled low (low-active gpio inited
with GPIOD_OUT_HIGH activates the signal which means setting its
value to low). Init nconfig with GPIOD_OUT_LOW to prevent this.
Signed-off-by: Anatolij Gustschin <[email protected]>
Acked-by: Alan Tull <[email protected]>
Signed-off-by: Moritz Fischer <[email protected]>
Cc: stable <[email protected]> # 4.14+
Signed-off-by: Greg Kroah-Hartman <[email protected]>
|
|
Speed up bit reversal by using hardware bit reversal
Add extra code to handle less than 4byte remnants, if any
Signed-off-by: Joshua Clayton <[email protected]>
Signed-off-by: Alan Tull <[email protected]>
Signed-off-by: Greg Kroah-Hartman <[email protected]>
|
|
altera-ps-spi loads FPGA firmware over SPI, using the "passive serial"
interface on Altera Arria 10, Cyclone V or Stratix V FPGAs.
This is one of the simpler ways to set up an FPGA at runtime.
The signal interface is close to unidirectional SPI with lsb first.
Signed-off-by: Joshua Clayton <[email protected]>
Signed-off-by: Anatolij Gustschin <[email protected]>
Signed-off-by: Alan Tull <[email protected]>
Signed-off-by: Greg Kroah-Hartman <[email protected]>
|