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2013-02-14dma: of-dma: protect list write operation by spin_lockAndy Shevchenko1-0/+2
It's possible to have an inconsistency in the list due to unprotected operation on it. The patch adds a proper locking on the list operation. Signed-off-by: Andy Shevchenko <[email protected]> Acked-by: Rob Herring <[email protected]> Acked-by: Viresh Kumar <[email protected]> Signed-off-by: Vinod Koul <[email protected]>
2013-02-14dmaengine: ste_dma40: do not remove descriptors for cyclic transfersFabio Baltieri1-3/+3
Fix dma_tc_handle() to call d40_desc_remove() and d40_desc_done() only for non-cyclic transfers, as this was breaking ux500_pcm since introduced in: d49278e dmaengine: dma40: Add support to split up large elements Reported-by: Shreshtha Kumar Sahu <[email protected]> Acked-by: Linus Walleij <[email protected]> Signed-off-by: Fabio Baltieri <[email protected]> Signed-off-by: Vinod Koul <[email protected]>
2013-02-14dma: of-dma.c: fix memory leakageCong Ding1-0/+1
The memory allocated to ofdma might be a leakage when error occurs. Signed-off-by: Cong Ding <[email protected]> Signed-off-by: Vinod Koul <[email protected]>
2013-02-14dw_dmac: apply default dma_mask if neededAndy Shevchenko1-0/+6
In some cases we got the device without dma_mask configured. We have to apply the default value to avoid crashes during memory mapping. Signed-off-by: Andy Shevchenko <[email protected]> Acked-by: Viresh Kumar <[email protected]> Signed-off-by: Vinod Koul <[email protected]>
2013-02-13dmaengine: ioat - fix spare sparse complainFengguang Wu1-1/+1
>> drivers/dma/ioat/dma_v3.c:371:6: sparse: symbol 'ioat3_timer_event' was not declared. Reported-by: Fengguang Wu <[email protected]> Signed-off-by: Fengguang Wu <[email protected]> Acked-by: Dave Jiang <[email protected]> Signed-off-by: Vinod Koul <[email protected]>
2013-02-13dmaengine: move drivers/of/dma.c -> drivers/dma/of-dma.cVinod Koul3-0/+270
as requested by Rob Suggested-by: Rob Herring <[email protected]> Signed-off-by: Vinod Koul <[email protected]>
2013-02-12ioatdma: fix race between updating ioat->head and IOAT_COMPLETION_PENDINGDave Jiang3-97/+128
There is a race that can hit during __cleanup() when the ioat->head pointer is incremented during descriptor submission. The __cleanup() can clear the PENDING flag when it does not see any active descriptors. This causes new submitted descriptors to be ignored because the COMPLETION_PENDING flag is cleared. This was introduced when code was adapted from ioatdma v1 to ioatdma v2. For v2 and v3, IOAT_COMPLETION_PENDING flag will be abandoned and a new flag IOAT_CHAN_ACTIVE will be utilized. This flag will also be protected under the prep_lock when being modified in order to avoid the race. Signed-off-by: Dave Jiang <[email protected]> Reviewed-by: Dan Williams <[email protected]> Signed-off-by: Vinod Koul <[email protected]>
2013-02-12dw_dmac: add support for Lynxpoint DMA controllersMika Westerberg1-0/+6
Intel Lynxpoint PCH Low Power Subsystem has DMA controller to support general purpose serial buses like SPI, I2C, and HSUART. This controller is enumerated from ACPI namespace with ACPI ID INTL9C60. Signed-off-by: Mika Westerberg <[email protected]> Signed-off-by: Andy Shevchenko <[email protected]> Acked-by: Viresh Kumar <[email protected]> Signed-off-by: Vinod Koul <[email protected]>
2013-02-05Merge tag 'tegra-for-3.9-soc-ccf' of ↵Olof Johansson1-1/+1
git://git.kernel.org/pub/scm/linux/kernel/git/swarren/linux-tegra into next/soc From Stephen Warren: ARM: tegra: Common Clock Framework rework Tegra already supports the common clock framework, but had issues: 1) The clock driver was located in arch/arm/mach-tegra/ rather than drivers/clk/. 2) A single "Tegra clock" type was implemented, rather than separate clock types for PLL, mux, divider, ... type in HW. 3) Clock lookups by device drivers were still driven by device name and connection ID, rather than through device tree. This pull request solves all three issues. This required some DT changes to add clocks properties, and driver changes to request clocks more "correctly". Finally, this rework allows all AUXDATA to be removed from Tegra board files, and various duplicate clock lookup entries to be removed from the driver. This pull request is based on the previous pull request, with tag tegra-for-3.9-cleanup. * tag 'tegra-for-3.9-soc-ccf' of git://git.kernel.org/pub/scm/linux/kernel/git/swarren/linux-tegra: (31 commits) clk: tegra30: remove unused TEGRA_CLK_DUPLICATE()s clk: tegra20: remove unused TEGRA_CLK_DUPLICATE()s ARM: tegra30: remove auxdata ARM: tegra20: remove auxdata ASoC: tegra: remove auxdata staging: nvec: remove use of clk_get_sys ARM: tegra: paz00: add clock information to DT ARM: tegra: add clock properties to Tegra30 DT ARM: tegra: add clock properties to Tegra20 DT spi: tegra: do not use clock name to get clock ARM: tegra: remove legacy clock code ARM: tegra: migrate to new clock code clk: tegra: add clock support for Tegra30 clk: tegra: add clock support for Tegra20 clk: tegra: add Tegra specific clocks ARM: tegra: define Tegra30 CAR binding ARM: tegra: define Tegra20 CAR binding ARM: tegra: move tegra_cpu_car.h to linux/clk/tegra.h ARM: tegra: add function to read chipid ARM: tegra: fix compile error when disable CPU_IDLE ... Signed-off-by: Olof Johansson <[email protected]> Conflicts: arch/arm/mach-tegra/board-dt-tegra20.c arch/arm/mach-tegra/board-dt-tegra30.c arch/arm/mach-tegra/common.c arch/arm/mach-tegra/platsmp.c drivers/clocksource/Makefile
2013-01-30Merge tag 'vexpress/drivers-for-3.9' of ↵Olof Johansson3-6/+9
git://git.linaro.org/people/pawelmoll/linux into next/drivers From Pawel Moll: Versatile Express related driver updates for 3.9: * Move sp810 header to a more generic location, mainly to share it with arm64 * tag 'vexpress/drivers-for-3.9' of git://git.linaro.org/people/pawelmoll/linux: arm: Move sp810.h to include/linux/amba/ + Linux 3.8-rc5 Signed-off-by: Olof Johansson <[email protected]>
2013-01-28Merge tag 'coh901318-for-arm-soc' of ↵Olof Johansson3-61/+1280
http://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-stericsson into next/drivers This pushes the platform data for the U300 COH901318 DMA controller down into the driver and cleans up in the <mach/*> namespace for the U300 platform. * tag 'coh901318-for-arm-soc' of http://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-stericsson: dma: coh901318: cut down on platform data abstraction dma: coh901318: merge header files dma: coh901318: push definitions into driver dma: coh901318: push header down into the DMA subsystem dma: coh901318: skip hard-coded addresses dma: coh901318: remove hardcoded target addresses dma: coh901318: push platform data into driver dma: coh901318: create a proper platform data file Signed-off-by: Olof Johansson <[email protected]> Conflicts: arch/arm/mach-u300/core.c
2013-01-28ARM: tegra: migrate to new clock codePrashant Gaikwad1-1/+1
Migrate Tegra clock support to drivers/clk/tegra, this involves moving: 1. definition of tegra_cpu_car_ops to clk.c 2. definition of reset functions to clk-peripheral.c 3. change parent of cpu clock. 4. Remove legacy clock initialization. 5. Initialize clocks using DT. 6. Remove all instance of mach/clk.h Signed-off-by: Prashant Gaikwad <[email protected]> [swarren: use to_clk_periph_gate().] Signed-off-by: Stephen Warren <[email protected]>
2013-01-28dw_dmac: return proper residue valueAndy Shevchenko2-2/+46
Currently the driver returns full length of the active descriptor which is wrong. We have to go throught the active descriptor and substract the length of each sent children in the chain from the total length along with the actual data in the DMA channel registers. The cyclic case is not handled by this patch due to len field in the descriptor structure is left untouched by the original code. Signed-off-by: Andy Shevchenko <[email protected]> Acked-by: Viresh Kumar <[email protected]> Signed-off-by: Vinod Koul <[email protected]>
2013-01-28dw_dmac: fill individual length of descriptorAndy Shevchenko1-0/+3
It will be useful to have the length of the transfer in the descriptor. The cyclic transfer functions remained untouched. Signed-off-by: Andy Shevchenko <[email protected]> Acked-by: Viresh Kumar <[email protected]> Signed-off-by: Vinod Koul <[email protected]>
2013-01-28dw_dmac: introduce total_len field in struct dw_descAndy Shevchenko2-6/+7
By this new field we distinguish a total length of the chain and the individual length of each descriptor in the chain. Signed-off-by: Andy Shevchenko <[email protected]> Acked-by: Viresh Kumar <[email protected]> Signed-off-by: Vinod Koul <[email protected]>
2013-01-28dw_dmac: remove unnecessary tx_list field in dw_dma_chanAndy Shevchenko2-6/+15
The soft LLP mode is working for active descriptor only. So, we do not need to have a copy of its pointer. Signed-off-by: Andy Shevchenko <[email protected]> Acked-by: Viresh Kumar <[email protected]> Signed-off-by: Vinod Koul <[email protected]>
2013-01-28dw_dmac: print out DW_PARAMS and DWC_PARAMS when debugAndy Shevchenko1-0/+5
It's usefull to have the values of the DW_PARAMS and DWC_PARAMS printed when debug mode is enabled. Signed-off-by: Andy Shevchenko <[email protected]> Acked-by: Viresh Kumar <[email protected]> Signed-off-by: Vinod Koul <[email protected]>
2013-01-28DMAEngine: sirf: lock the shared registers access in sirfsoc_dma_terminate_allBarry Song1-1/+3
Just like Russell pointed out in "DMAEngine: sirf: add DMA pause/resume support" at http://www.spinics.net/lists/arm-kernel/msg212496.html here I find sirfsoc_dma_terminate_all() has same problem, so move the locking to the front of registers access. Signed-off-by: Barry Song <[email protected]> Cc: Russell King <[email protected]> Signed-off-by: Vinod Koul <[email protected]>
2013-01-28DMAEngine: sirf: add DMA pause/resume supportBarry Song1-0/+46
pause/resume are important for users like ALSA sound drivers, this patches make the sirf prima2/marco support DMA commands DMA_PAUSE and DMA_RESUME. Signed-off-by: Barry Song <[email protected]> Cc: Russell King <[email protected]> Signed-off-by: Vinod Koul <[email protected]>
2013-01-25Merge 3.8-rc5 into driver-core-nextGreg Kroah-Hartman3-6/+9
This resolves a gpio driver merge issue pointed out in linux-next. Signed-off-by: Greg Kroah-Hartman <[email protected]>
2013-01-25dma: Convert to devm_ioremap_resource()Thierry Reding5-18/+20
Convert all uses of devm_request_and_ioremap() to the newly introduced devm_ioremap_resource() which provides more consistent error handling. devm_ioremap_resource() provides its own error messages so all explicit error messages can be removed from the failure code paths. Signed-off-by: Thierry Reding <[email protected]> Cc: Vinod Koul <[email protected]> Signed-off-by: Greg Kroah-Hartman <[email protected]>
2013-01-24Merge branch 'fixes' of git://git.infradead.org/users/vkoul/slave-dmaLinus Torvalds3-6/+9
Pull slave-dmaengine fixes from Vinod Koul: "A few fixes on slave dmanengine. There are trivial fixes in imx-dma, tegra-dma & ioat driver" * 'fixes' of git://git.infradead.org/users/vkoul/slave-dma: dma: tegra: implement flags parameters for cyclic transfer dmaengine: imx-dma: Disable use of hw_chain to fix sg_dma transfers. ioat: Fix DMA memory sync direction correct flag
2013-01-21Merge tag 'ux500-dma40' of //git.linaro.org/people/fabiobaltieri/linux.gitVinod Koul3-143/+505
Pull ste_dma40 fixes from Fabio Signed-off-by: Vinod Koul <[email protected]>
2013-01-20dw_dmac: move soft LLP code from tasklet to dwc_scan_descriptorsAndy Shevchenko1-22/+21
The proper place for the main logic of the soft LLP mode is dwc_scan_descriptors. It prevents to get the transfer unexpectedly aborted in case the user calls dwc_tx_status. Signed-off-by: Andy Shevchenko <[email protected]> Acked-by: Viresh Kumar <[email protected]> Signed-off-by: Vinod Koul <[email protected]>
2013-01-20dw_dmac: don't exceed AHB master number in dwc_get_data_widthAndy Shevchenko1-13/+20
The driver assumes that hardware has two AHB masters which might not be always true. In such cases we must not exceed number of the AHB masters present in the hardware. In the proposed scheme in this patch, we would choose the master with highest possible number whenever we exceed max AHB masters. Signed-off-by: Andy Shevchenko <[email protected]> Acked-by: Viresh Kumar <[email protected]> Signed-off-by: Vinod Koul <[email protected]>
2013-01-20dw_dmac: allocate dma descriptors from DMA_COHERENT memoryAndy Shevchenko2-64/+18
Currently descriptors are allocated from normal cacheable memory and that slows down filling the descriptors, as we need to call cache_coherency routines afterwards. It would be better to allocate memory for these descriptors from DMA_COHERENT memory. This would make code much cleaner too. Signed-off-by: Andy Shevchenko <[email protected]> Tested-by: Mika Westerberg <[email protected]> Acked-by: Viresh Kumar <[email protected]> Signed-off-by: Vinod Koul <[email protected]>
2013-01-20dma: sh/shdma-base.c: remove unnecessary null pointer checkCong Ding1-3/+0
the variable chan is dereferenced in line 635, so it is no reason to check null again in line 641. Signed-off-by: Cong Ding <[email protected]> Signed-off-by: Vinod Koul <[email protected]>
2013-01-20dma: remove unnecessary null pointer check in mmp_pdma.cCong Ding1-4/+2
the pointer cfg is dereferenced in line 594, so it's no reason to check null again in line 620. Signed-off-by: Cong Ding <[email protected]> Signed-off-by: Vinod Koul <[email protected]>
2013-01-20dma: edma: fix slave config dependency on directionMatt Porter1-28/+27
The edma_slave_config() implementation depends on the direction field such that it will not properly configure a slave channel when called without direction set. This fixes the implementation so that the slave config is copied as is and prep_slave_sg() handles the direction dependent handling. spi-omap2-mcspi and omap_hsmmc both expose this bug as they configure the slave channel config from a common path with an unconfigured direction field. Signed-off-by: Matt Porter <[email protected]> Signed-off-by: Vinod Koul <[email protected]>
2013-01-14dmaengine: set_dma40: balance clock in probe fail codeFabio Baltieri1-1/+1
Clock code was changed to use clk_prepare_enable in: b707c65 dma/ste_dma40: Fixup clock usage during probe but clk_disable on probe fail path was not updated. This patch fix this by using clk_disable_unprepare in place of clk_disable. Acked-by: Ulf Hansson <[email protected]> Acked-by: Linus Walleij <[email protected]> Acked-by: Vinod Koul <[email protected]> Signed-off-by: Fabio Baltieri <[email protected]>
2013-01-14dmaengine: set_dma40: ignore spurious interruptsFabio Baltieri1-3/+12
Some DMA channels may be used by other cores in the SoC. This patch modifies the dma interrupt handler to ignore interrupts from unknown channels. Cc: Rabin Vincent <[email protected]> Acked-by: Linus Walleij <[email protected]> Acked-by: Vinod Koul <[email protected]> Signed-off-by: Fabio Baltieri <[email protected]>
2013-01-14dmaengine: ste_dma40: add software lli supportFabio Baltieri1-1/+19
This patch add support to manage LLI by SW for select phy channels. There is a HW issue in certain controllers due to which on certain occassions HW LLI cannot be used on some physical channels. To avoid the HW issue on a specific phy channel, the phy channel number can be added to the list of soft_lli_channels and there after all the transfers on that channel will use software LLI, for peripheral to memory transfers. SoftLLI introduces relink overhead, that could impact performace for certain use cases. This is based on a previous patch of Narayanan Gopalakrishnan. Cc: Shreshtha Kumar Sahu <[email protected]> Acked-by: Linus Walleij <[email protected]> Acked-by: Vinod Koul <[email protected]> Signed-off-by: Fabio Baltieri <[email protected]>
2013-01-14dmaengine: ste_dma40: minor code readability fixesFabio Baltieri1-9/+8
Use internal variables to the cycles to improve code readability, no functional changes. Acked-by: Linus Walleij <[email protected]> Acked-by: Vinod Koul <[email protected]> Signed-off-by: Fabio Baltieri <[email protected]>
2013-01-14dmaengine: ste_dma40: minor cosmetic fixesFabio Baltieri2-22/+13
This patch contains various non functional cosmetic fixes. Acked-by: Linus Walleij <[email protected]> Acked-by: Vinod Koul <[email protected]> Signed-off-by: Fabio Baltieri <[email protected]>
2013-01-14dmaengine: ste_dma40: add a done queue for completed descriptorsFabio Baltieri1-4/+33
This is to keep the active queue for only those transfers which are actually active in the hardware. Descriptors will be moved to the done queue after they are completed in the hardware (interrupt handler) but before all the cleanup work has been completed (tasklet). Mostly based on a previous patch by Rabin Vincent. Cc: Rabin Vincent <[email protected]> Acked-by: Linus Walleij <[email protected]> Acked-by: Vinod Koul <[email protected]> Signed-off-by: Fabio Baltieri <[email protected]>
2013-01-14dmaengine: ste_dma40: support more than 128 event linesTong Liu2-81/+355
U8540 DMA controller is different from u9540 we need define new registers and use them to support handling more than 128 event lines. Signed-off-by: Tong Liu <[email protected]> Reviewed-by: Per Forlin <[email protected]> Acked-by: Linus Walleij <[email protected]> Acked-by: Vinod Koul <[email protected]> Signed-off-by: Fabio Baltieri <[email protected]>
2013-01-14dmaengine: ste_dma40: physical channels number correctionGerald Baeza1-5/+10
DMAC_ICFG[0:2]=SCHNB only allows to count 'multiple of 4' physical channels so it was ok with platforms having 8 channels but cannot be used for next versions (with 10 or 14 channels). This patch allows to provide the number of physical channels for a DMA device via platform_data, or still rely on SCHNB if platform_data announces 0 channel. Signed-off-by: Gerald Baeza <[email protected]> Reviewed-by: Per Forlin <[email protected]> Acked-by: Linus Walleij <[email protected]> Acked-by: Vinod Koul <[email protected]> Signed-off-by: Fabio Baltieri <[email protected]>
2013-01-14dmaengine: ste_dma40: support fixed physical channel allocationGerald Baeza1-2/+11
This patch makes existing use_fixed_channel field (of stedma40_chan_cfg structure) applicable to physical channels. Signed-off-by: Gerald Baeza <[email protected]> Tested-by: Yannick Fertre <[email protected]> Reviewed-by: Per Forlin <[email protected]> Acked-by: Linus Walleij <[email protected]> Acked-by: Vinod Koul <[email protected]> Signed-off-by: Fabio Baltieri <[email protected]>
2013-01-14dmaengine: ste_dma40: don't allow high priority dest event linesRabin Vincent1-1/+14
Hardware bug: when a logical channel is triggerred by a high priority destination event line, an extra packet transaction is generated in case of important data write response latency on previous logical channel A and if the source transfer of current logical channel B is already completed and if no other channel with a higher priority than B is waiting for execution. Software workaround: do not set the high priority level for the destination event lines that trigger logical channels. Signed-off-by: Rabin Vincent <[email protected]> Reviewed-by: Shreshtha Kumar Sahu <[email protected]> Acked-by: Linus Walleij <[email protected]> Acked-by: Vinod Koul <[email protected]> Signed-off-by: Fabio Baltieri <[email protected]>
2013-01-14dmaengine: ste_dma40: don't check for pm_runtime_suspended()Narayanan G1-2/+0
The check for runtime suspend is not needed during a regular suspend, as the framework takes care of this. This fixes the issue of DMA driver not letting the system to go to deepsleep in the first attempt. Signed-off-by: Narayanan G <[email protected]> Reviewed-by: Rabin Vincent <[email protected]> Acked-by: Linus Walleij <[email protected]> Acked-by: Vinod Koul <[email protected]> Signed-off-by: Fabio Baltieri <[email protected]>
2013-01-14dmaengine: ste_dma40: limit burst size to 16Per Forlin1-0/+8
The client is not aware of the maximum burst size in the dma driver. If the size exceeds 16 set max to 16. Signed-off-by: Per Forlin <[email protected]> Acked-by: Linus Walleij <[email protected]> Acked-by: Vinod Koul <[email protected]> Signed-off-by: Fabio Baltieri <[email protected]>
2013-01-14dmaengine: ste_dma40: set dma max seg sizePer Forlin1-0/+8
Maximum DMA seg size is (0xffff x data_width). If max seg size is not set it deafults to 64k. This results in failure if transferring 64k in byte mode. Large seg sizes may be supported by splitting large transfer. Signed-off-by: Per Forlin <[email protected]> Acked-by: Linus Walleij <[email protected]> Acked-by: Vinod Koul <[email protected]> Signed-off-by: Fabio Baltieri <[email protected]>
2013-01-14dmaengine: ste_dma40: use writel_relaxed for lcxaPer Forlin1-8/+8
lcpa and lcla are written often and the cache_sync() overhead in writel is costly, especially for wlan where every single network packet (in RX mode) corresponds to a separate DMA transfer. Signed-off-by: Per Forlin <[email protected]> Reviewed-by: Narayanan Gopalakrishnan <[email protected]> Reviewed-by: Rabin Vincent <[email protected]> Acked-by: Linus Walleij <[email protected]> Acked-by: Vinod Koul <[email protected]> Signed-off-by: Fabio Baltieri <[email protected]>
2013-01-14dmaengine: ste_dma40: reset priority bit for logical channelsNarayanan1-5/+6
This patch sets the SSCFG/SDCFG bit[7] PRI only for physical channel requests with high priority. For logical channels, this bit will be zero. Signed-off-by: Narayanan G <[email protected]> Reviewed-by: Rabin Vincent <[email protected]> Acked-by: Linus Walleij <[email protected]> Acked-by: Vinod Koul <[email protected]> Signed-off-by: Fabio Baltieri <[email protected]>
2013-01-13pl080.h: moved from arm/include/asm/hardware to include/linux/amba/Alessandro Rubini1-1/+1
The header is used by drivers/dma/amba-pl08x.c, which can be compiled under x86, where PL080 exists under a PCI-to-AMBA bridge. This patche moves it where it can be accessed by other architectures, and fixes all users. Signed-off-by: Alessandro Rubini <[email protected]> Acked-by: Giancarlo Asnaghi <[email protected]> Acked-by: Linus Walleij <[email protected]> Signed-off-by: Vinod Koul <[email protected]>
2013-01-12dma: dw_dmac: clear suspend bit during terminationHeikki Krogerus1-1/+1
The DMA transfer could not be established if previously it was paused and terminated. In that case the channel's suspend bit remains set that prevents to transfer anything until channel is resumed. The patch adds the dwc_chan_resume() call instead of a plain flag assignment. That clears the DWC_CFGL_CH_SUSP bit as well during termination. Signed-off-by: Heikki Krogerus <[email protected]> Signed-off-by: Andy Shevchenko <[email protected]> Acked-by: Viresh Kumar <[email protected]> Signed-off-by: Vinod Koul <[email protected]>
2013-01-12dw_dmac: backlink to dw_dma in dw_dma_chan is superfluousAndy Shevchenko2-10/+20
The same information could be extracted from the struct dma_chan. The patch introduces helper function dwc_get_data_width() as well. Signed-off-by: Andy Shevchenko <[email protected]> Acked-by: Viresh Kumar <[email protected]> Signed-off-by: Vinod Koul <[email protected]>
2013-01-12dw_dmac: make usage of dw_dma_slave optionalAndy Shevchenko1-6/+7
The driver requires a custom slave configuration to be present to be able to make the slave transfers. Nevertheless, in some cases we need only the request line as an additional information to the generic slave configuration. The request line is provided by slave_id parameter of the dma_slave_config structure. That's why the custom slave configuration could be optional for such cases. Signed-off-by: Andy Shevchenko <[email protected]> Acked-by: Viresh Kumar <[email protected]> Signed-off-by: Vinod Koul <[email protected]>
2013-01-12dw_dmac: store direction in the custom channel structureAndy Shevchenko2-8/+18
Currently the direction value comes from the generic slave configuration structure and explicitly as a preparation function parameter. The first one is kinda obsoleted. Thus, we have to store the value passed to the preparation function somewhere in our structures to be able to use it later. The best candidate to provide the storage is a custom channel structure. Until now we still keep and check the direction field of the slave config structure as well. Signed-off-by: Andy Shevchenko <[email protected]> Acked-by: Viresh Kumar <[email protected]> Signed-off-by: Vinod Koul <[email protected]>
2013-01-12dw_dmac: call .probe after we have a device in placeAndy Shevchenko1-1/+2
If we don't yet have the platform device for the driver when it is being loaded we fail to probe the driver. So instead of calling probe() directly we call platform_driver_register(). It will call the probe() immediately if we have the device but also makes the driver to work on platforms where the platform device is created later. Signed-off-by: Andy Shevchenko <[email protected]> Acked-by: Viresh Kumar <[email protected]> Signed-off-by: Vinod Koul <[email protected]>
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