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2014-05-22clocksource: marco: Fix the affinity set for local timer of CPU1Zhiwu Song1-1/+1
irqchip will reject the affinity set to CPUs which is not online yet. but in the CPU1 wakeup stage, OS only sets CPU1 to be online after local timer is set, so that causes the irq_set_affinity not work. this patch moves to irq_force_affinity() for the low level boot stage. Signed-off-by: Zhiwu Song <[email protected]> Signed-off-by: Barry Song <[email protected]> Signed-off-by: Daniel Lezcano <[email protected]>
2014-05-21Merge tag 'samsung-drivers' of ↵Olof Johansson1-0/+8
http://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung into next/drivers Merge "Samsung driver update for 3.16" from Kukjin Kim: exynos_mct update for v3.16 - register sched_clock callback to use clocksource mct-frc * tag 'samsung-drivers' of http://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung: clocksource: exynos_mct: register sched_clock callback Signed-off-by: Olof Johansson <[email protected]>
2014-05-21Merge tag 'vexpress/updates-for-3.16' of ↵Olof Johansson5-2/+63
git://git.linaro.org/people/pawel.moll/linux into next/cleanup Merge "ARM Versatile Express updates for 3.16" from Pawel Moll: This series reworks VE's platform configuration infrastructure by: - making it possible to instantiate selected devices from the Device Tree, prior to massive population, - converting custom "func" API into standard "regmap", - splitting the existing MFD driver into smaller ones and placing them into relevant directories. The common clock framework driver can now be selected individually (mostly for arm64 sake, where some of them are not used at all). It also simplifies the machine code, by: - moving the shed clock info clocksource driver, - simplifying SMP operations to base them entirely of the DT data, - moving platform ID checks into relevant driver. * tag 'vexpress/updates-for-3.16' of git://git.linaro.org/people/pawel.moll/linux: ARM: vexpress: move HBI check to sysreg driver ARM: vexpress: Simplify SMP operations for DT-powered system ARM: vexpress: remove redundant vexpress_dt_cpus_num to get cpu count clocksource: Sched clock source for Versatile Express clk: versatile: Split config options for sp810 and vexpress_osc mfd: vexpress: Define the device as MFD cells mfd: syscon: Add platform data with a regmap config name mfd: vexpress: Convert custom func API to regmap of: Keep track of populated platform devices + Linux 3.15-rc5 Signed-off-by: Olof Johansson <[email protected]>
2014-05-21Merge branch 'depends/clockevents-cleanups' into next/boardsOlof Johansson3-680/+1305
Bringing in as an external dependency that the renesas/clock-cleanup2 branch relies on. * depends/clockevents-cleanups: (52 commits) clocksource: sh_mtu2: Sort headers alphabetically clocksource: sh_mtu2: Remove FSF mail address from GPL notice clocksource: sh_mtu2: Rename clock to "fck" in the non-legacy case clocksource: sh_mtu2: Add support for multiple channels per device clocksource: sh_mtu2: Hardcode MTU2 clock event rating to 200 clocksource: sh_mtu2: Set cpumask to cpu_possible_mask clocksource: sh_mtu2: Replace hardcoded register values with macros clocksource: sh_mtu2: Allocate channels dynamically clocksource: sh_mtu2: Replace kmalloc + memset with kzalloc clocksource: sh_mtu2: Add index to struct sh_mtu2_channel clocksource: sh_mtu2: Add memory base to sh_mtu2_channel structure clocksource: sh_mtu2: Constify name argument to sh_mtu2_register() clocksource: sh_mtu2: Split channel setup to separate function clocksource: sh_mtu2: Rename struct sh_mtu2_priv to sh_mtu2_device clocksource: sh_mtu2: Split channel fields from sh_mtu2_priv clocksource: sh_mtu2: Turn sh_mtu2_priv fields into local variables clocksource: sh_mtu2: Use request_irq() instead of setup_irq() clocksource: sh_tmu: Sort headers alphabetically clocksource: sh_tmu: Remove FSF mail address from GPL notice clocksource: sh_tmu: Rename clock to "fck" in the non-legacy case ... Signed-off-by: Olof Johansson <[email protected]>
2014-05-20of: consolidate linker section OF match table declarationsRob Herring1-1/+1
We now have several OF match tables using linker sections that are nearly the same definition. The only variation is the callback function prototype. Create a common define for creating linker section OF match table entries which each table declaration can use. Acked-by: Grant Likely <[email protected]> Signed-off-by: Rob Herring <[email protected]>
2014-05-20clocksource: cadence_ttc: Use readl/writel_relaxed instead of __rawMichal Simek1-27/+27
For supporting ARM big-endian is necessary to use proper IO endianess accessors. Based on Ben Dooks BE guide. Similar conversion is done here: "mv_xor: use {readl, writel}_relaxed instead of __raw_{readl, writel}" (sha1: 5733c38ae3473115ac7df3fe19bd2502149d8c51) Signed-off-by: Michal Simek <[email protected]>
2014-05-19clocksource: sh_tmu: Fix channel IRQ retrieval in legacy caseLaurent Pinchart1-1/+1
In the legacy platform data case each TMU platform device handles a single channel with a single IRQ for the platform device. Retrieve the IRQ using the logical channel number instead of the hardware channel number. Signed-off-by: Laurent Pinchart <[email protected]> Signed-off-by: Daniel Lezcano <[email protected]>
2014-05-19clocksource: qcom: Implement read_current_timer for udelayStephen Boyd1-0/+13
Setup the same timer used as the clocksource to be used as the read_current_timer implementation. This allows us to support a stable udelay implementation on MSMs where it's possible for the CPUs to scale speeds independently of one another. Signed-off-by: Stephen Boyd <[email protected]> Signed-off-by: Daniel Lezcano <[email protected]>
2014-05-16Merge remote-tracking branch 'tip/timers/core/timers/core' into clockevents/3.16Daniel Lezcano3-11/+14
2014-05-15clocksource: Sched clock source for Versatile ExpressPawel Moll3-0/+52
This patch adds a trival sched clock source using free running, 24MHz clocked counter present in the ARM Ltd. reference platforms (Versatile, RealView, Versatile Express) System Registers block. This code replaces the call in the VE machine code. Signed-off-by: Pawel Moll <[email protected]> Reviewed-by: Linus Walleij <[email protected]>
2014-05-12clocksource:sirf: remove the hardcode for the clk of timersZhiwu Song2-9/+4
Nobody want to know the connection between io clk and timer clk, so exposing this information to timer module is not reasonable. this patch moves to define the timers' clk in dt. Signed-off-by: Zhiwu Song <[email protected]> Signed-off-by: Barry Song <[email protected]>
2014-05-12clocksource: prima2: fix some minor checkpatch issuesBin Shi1-14/+28
Fix the "line over 80 characters". users of the codes - key customers really care about that. WARNING: line over 80 characters 64: FILE: timer-prima2.c:64: + WARN_ON(!(readl_relaxed(sirfsoc_timer_base + SIRFSOC_TIMER_STATUS) & BIT(0))); WARNING: line over 80 characters 80: FILE: timer-prima2.c:80: + writel_relaxed(SIRFSOC_TIMER_LATCH_BIT, sirfsoc_timer_base + SIRFSOC_TIMER_LATCH); WARNING: line over 80 characters 82: FILE: timer-prima2.c:82: + cycles = (cycles << 32) | readl_relaxed(sirfsoc_timer_base + SIRFSOC_TIMER_LATCHED_LO); WARNING: line over 80 characters 92: FILE: timer-prima2.c:92: + writel_relaxed(SIRFSOC_TIMER_LATCH_BIT, sirfsoc_timer_base + SIRFSOC_TIMER_LATCH); WARNING: line over 80 characters 96: FILE: timer-prima2.c:96: + writel_relaxed(SIRFSOC_TIMER_LATCH_BIT, sirfsoc_timer_base + SIRFSOC_TIMER_LATCH); WARNING: line over 80 characters 111: FILE: timer-prima2.c:111: + writel_relaxed(val | BIT(0), sirfsoc_timer_base + SIRFSOC_TIMER_INT_EN); WARNING: line over 80 characters 114: FILE: timer-prima2.c:114: + writel_relaxed(val & ~BIT(0), sirfsoc_timer_base + SIRFSOC_TIMER_INT_EN); WARNING: line over 80 characters 126: FILE: timer-prima2.c:126: + writel_relaxed(SIRFSOC_TIMER_LATCH_BIT, sirfsoc_timer_base + SIRFSOC_TIMER_LATCH); WARNING: line over 80 characters 129: FILE: timer-prima2.c:129: + sirfsoc_timer_reg_val[i] = readl_relaxed(sirfsoc_timer_base + sirfsoc_timer_reg_list[i]); WARNING: line over 80 characters 137: FILE: timer-prima2.c:137: + writel_relaxed(sirfsoc_timer_reg_val[i], sirfsoc_timer_base + sirfsoc_timer_reg_list[i]); WARNING: line over 80 characters 139: FILE: timer-prima2.c:139: + writel_relaxed(sirfsoc_timer_reg_val[SIRFSOC_TIMER_REG_CNT - 2], sirfsoc_timer_base + SIRFSOC_TIMER_COUNTER_LO); WARNING: line over 80 characters 140: FILE: timer-prima2.c:140: + writel_relaxed(sirfsoc_timer_reg_val[SIRFSOC_TIMER_REG_CNT - 1], sirfsoc_timer_base + SIRFSOC_TIMER_COUNTER_HI); WARNING: line over 80 characters 216: FILE: timer-prima2.c:216: +CLOCKSOURCE_OF_DECLARE(sirfsoc_prima2_timer, "sirf,prima2-tick", sirfsoc_prima2_timer_init); total: 0 errors, 13 warnings, 216 lines checked timer-prima2.c has style problems, please review. If any of these errors are false positives, please report them to the maintainer, see CHECKPATCH in MAINTAINERS. Signed-off-by: Bin Shi <[email protected]> Signed-off-by: Barry Song <[email protected]>
2014-05-02clocksource: exynos_mct: register sched_clock callbackVincent Guittot1-0/+8
Use the clocksource mct-frc for sched_clock Signed-off-by: Vincent Guittot <[email protected]> Reviewed-by: Tomasz Figa <[email protected]> Acked-by: Daniel Lezcano <[email protected]> Signed-off-by: Kukjin Kim <[email protected]>
2014-04-29Merge branch 'clockevents/3.15-fixes' of ↵Thomas Gleixner2-2/+11
git://git.linaro.org/people/daniel.lezcano/linux into timers/urgent clockevent fixes for 3.15 from Daniel Lezcano: * Lorenzo Pieralizi fixed an issue with the arch_arm_timer where the C3STOP flag for all the arch can cause some trouble by setting the flag only if the power domain is not always on * Alexander Shiyan fixed a compilation by changing the init function to the right prototype
2014-04-29clocksource: nspire: Fix compiler warningAlexander Shiyan1-1/+6
CC drivers/clocksource/zevio-timer.o drivers/clocksource/zevio-timer.c:215:1: warning: comparison of distinct pointer types lacks a cast [enabled by default] Signed-off-by: Alexander Shiyan <[email protected]> Signed-off-by: Daniel Lezcano <[email protected]>
2014-04-29clocksource: arch_arm_timer: Fix age-old arch timer C3STOP detection issueLorenzo Pieralisi1-1/+5
ARM arch timers are tightly coupled with the CPU logic and lose context on platform implementing HW power management when cores are powered down at run-time. Marking the arch timers as C3STOP regardless of power management capabilities causes issues on platforms with no power management, since in that case the arch timers cannot possibly enter states where the timer loses context at runtime and therefore can always be used as a high resolution clockevent device. In order to fix the C3STOP issue in a way compliant with how real HW works, this patch adds a boolean property to the arch timer bindings to define if the arch timer is managed by an always-on power domain. This power domain is present on all ARM platforms to date, and manages HW that must not be turned off, whatever the state of other HW components (eg power controller). On platforms with no power management capabilities, it is the only power domain present, which encompasses and manages power supply for all HW components in the system. If the timer is powered by the always-on power domain, the always-on property must be present in the bindings which means that the timer cannot be shutdown at runtime, so it is not a C3STOP clockevent device. If the timer binding does not contain the always-on property, the timer is assumed to be power-gateable, hence it must be defined as a C3STOP clockevent device. Cc: Daniel Lezcano <[email protected]> Cc: Magnus Damm <[email protected]> Cc: Marc Carino <[email protected]> Cc: Mark Rutland <[email protected]> Acked-by: Marc Zyngier <[email protected]> Acked-by: Rob Herring <[email protected]> Signed-off-by: Lorenzo Pieralisi <[email protected]> Signed-off-by: Daniel Lezcano <[email protected]>
2014-04-22clocksource: sun5i: Add support for reset controllerMaxime Ripard1-0/+6
The Allwinner A31 that uses this timer has the timer IP asserted in reset. Add an optional reset property to the DT, and deassert the timer from reset if it's there. Signed-off-by: Maxime Ripard <[email protected]> Signed-off-by: Daniel Lezcano <[email protected]>
2014-04-22Merge branch 'clockevents/cmt-mtu2-tmu-cleanups' into clockevents/3.16Daniel Lezcano3-680/+1305
This patch set cleans up the Renesas CMT and TMU drivers in preparation for DT support. The first 35 patches are a bunch of necessary cleanups that reorganize the CMT and TMU drivers, their platform data, and the memory, interrupt and clock resources they expect. As a result the drivers accept a new platform data model close to the hardware with supports for all the timer channels using a single device. The next 13 patches (36/52 to 48/52) move all CMT and TMU platforms from the old to the new platform data model. Patches 49/52 to 52/52 then drop support for the old model and perform one more cleanup. Signed-off-by: Daniel Lezcano <[email protected]>
2014-04-22clocksource: efm32: use $vendor,$device scheme for compatible stringUwe Kleine-König1-1/+2
Wolfram Sang pointed out that "efm32,$device" is non-standard. So use the common scheme and prefix device with "efm32-". The old compatible string is left in place until arch/arm/boot/dts/efm32* is fixed. Acked-by: Wolfram Sang <[email protected]> Acked-by: Rob Herring <[email protected]> Signed-off-by: Uwe Kleine-König <[email protected]> Signed-off-by: Daniel Lezcano <[email protected]>
2014-04-22clocksource: arm_global_timer: Only check for unusable timer on A9Matthew Leach1-2/+3
The check for a usable global timer in the probe code does not enquire which CPU we are currently running on. This can cause the driver to incorrectly assume we have an unusable global timer if we are running on a CPU other than A9. Before checking the CPU revision, ensure we are running on an A9 CPU. Acked-by: Will Deacon <[email protected]> Signed-off-by: Matthew Leach <[email protected]> Signed-off-by: Daniel Lezcano <[email protected]>
2014-04-17clocksource: Exynos_mct: Register clock event after request_irq()Krzysztof Kozlowski1-2/+2
After hotplugging CPU1 the first call of interrupt handler for CPU1 oneshot timer was called on CPU0 because it fired before setting IRQ affinity. Affected are SoCs where Multi Core Timer interrupts are shared (SPI), e.g. Exynos 4210. During setup of the MCT timers the clock event device should be registered after setting the affinity for interrupt. This will prevent starting the timer too early. Signed-off-by: Krzysztof Kozlowski <[email protected]> Signed-off-by: Thomas Gleixner <[email protected]> Cc: Kyungmin Park <[email protected]> Cc: Marek Szyprowski <[email protected]> Cc: Bartlomiej Zolnierkiewicz <[email protected]> Cc: Tomasz Figa <[email protected]>, Cc: Daniel Lezcano <[email protected]>, Cc: Kukjin Kim <[email protected]> Cc: [email protected], Cc: [email protected] Link: http://lkml.kernel.org/r/[email protected] Signed-off-by: Thomas Gleixner <[email protected]>
2014-04-17clocksource: Exynos_mct: Use irq_force_affinity() in cpu bringupThomas Gleixner1-7/+1
The starting cpu is not yet in the online mask so irq_set_affinity() fails which results in per cpu timers for this cpu ending up on some other online cpu, ususally cpu 0. Use irq_force_affinity() which disables the online mask check and makes things work. Signed-off-by: Thomas Gleixner <[email protected]> Tested-by: Krzysztof Kozlowski <[email protected]> Cc: Kyungmin Park <[email protected]> Cc: Marek Szyprowski <[email protected]> Cc: Bartlomiej Zolnierkiewicz <[email protected]> Cc: Tomasz Figa <[email protected]>, Cc: Daniel Lezcano <[email protected]>, Cc: Kukjin Kim <[email protected]> Cc: [email protected], Cc: [email protected] Link: http://lkml.kernel.org/r/[email protected] Signed-off-by: Thomas Gleixner <[email protected]>
2014-04-16clocksource: sh_mtu2: Sort headers alphabeticallyLaurent Pinchart1-9/+9
This helps locating duplicates and inserting new headers. Signed-off-by: Laurent Pinchart <[email protected]> Tested-by: Wolfram Sang <[email protected]>
2014-04-16clocksource: sh_mtu2: Remove FSF mail address from GPL noticeLaurent Pinchart1-4/+0
Do not include the paragraph about writing to the Free Software Foundation's mailing address from the sample GPL notice. The FSF has changed addresses in the past, and may do so again. Linux already includes a copy of the GPL. Signed-off-by: Laurent Pinchart <[email protected]> Tested-by: Wolfram Sang <[email protected]>
2014-04-16clocksource: sh_mtu2: Rename clock to "fck" in the non-legacy caseLaurent Pinchart1-1/+1
The sh_mtu2 driver gets the MTU2 functional clock using a connection ID of "mtu2_fck". While all SH SoCs create clock lookup entries with a NULL device ID and a "mtu2_fck" connection ID, the ARM SoCs use the device ID only with a NULL connection ID. This works on legacy platforms but will break on ARM with DT boot. Fix the situation by using a connection ID of "fck" in the non-legacy platform data case. Clock lookup entries will be renamed to use the device ID as well as the connection ID as platforms get moved to new platform data. The legacy code will eventually be dropped, leaving us with device ID based clock lookup, compatible with DT boot. Signed-off-by: Laurent Pinchart <[email protected]> Tested-by: Wolfram Sang <[email protected]>
2014-04-16clocksource: sh_mtu2: Add support for multiple channels per deviceLaurent Pinchart1-54/+130
MTU2 hardware devices can support multiple channels, with global registers and per-channel registers. The sh_mtu2 driver currently models the hardware with one Linux device per channel. This model makes it difficult to handle global registers in a clean way. Add support for a new model that uses one Linux device per timer with multiple channels per device. This requires changes to platform data, add new channel configuration fields. Support for the legacy model is kept and will be removed after all platforms switch to the new model. Signed-off-by: Laurent Pinchart <[email protected]> Tested-by: Wolfram Sang <[email protected]>
2014-04-16clocksource: sh_mtu2: Hardcode MTU2 clock event rating to 200Laurent Pinchart1-6/+6
All boards use clock event ratings of 200 for the MTU2, hardcode it in the driver. Signed-off-by: Laurent Pinchart <[email protected]> Tested-by: Wolfram Sang <[email protected]>
2014-04-16clocksource: sh_mtu2: Set cpumask to cpu_possible_maskLaurent Pinchart1-1/+1
The MTU2 is not tied to CPU0, make it usable on any CPU. Signed-off-by: Laurent Pinchart <[email protected]> Tested-by: Wolfram Sang <[email protected]>
2014-04-16clocksource: sh_mtu2: Replace hardcoded register values with macrosLaurent Pinchart1-6/+92
Define symbolic macros for all used registers bits. Signed-off-by: Laurent Pinchart <[email protected]> Tested-by: Wolfram Sang <[email protected]>
2014-04-16clocksource: sh_mtu2: Allocate channels dynamicallyLaurent Pinchart1-7/+20
This prepares the driver for multi-channel support. Signed-off-by: Laurent Pinchart <[email protected]> Tested-by: Wolfram Sang <[email protected]>
2014-04-16clocksource: sh_mtu2: Replace kmalloc + memset with kzallocLaurent Pinchart1-5/+1
One kzalloc a day keeps the bugs away. Signed-off-by: Laurent Pinchart <[email protected]> Tested-by: Wolfram Sang <[email protected]>
2014-04-16clocksource: sh_mtu2: Add index to struct sh_mtu2_channelLaurent Pinchart1-9/+13
Use the index as the timer start/stop bit and when printing messages to identify the channel. Signed-off-by: Laurent Pinchart <[email protected]> Tested-by: Wolfram Sang <[email protected]>
2014-04-16clocksource: sh_mtu2: Add memory base to sh_mtu2_channel structureLaurent Pinchart1-14/+18
The channel memory base is channel-specific, add it to the channel structure in preparation for support of multiple channels per device. Signed-off-by: Laurent Pinchart <[email protected]> Tested-by: Wolfram Sang <[email protected]>
2014-04-16clocksource: sh_mtu2: Constify name argument to sh_mtu2_register()Laurent Pinchart1-3/+3
The name argument is assigned to const structure fields only, constify it. Signed-off-by: Laurent Pinchart <[email protected]> Tested-by: Wolfram Sang <[email protected]>
2014-04-16clocksource: sh_mtu2: Split channel setup to separate functionLaurent Pinchart1-10/+19
Move the channel setup code from sh_mtu2_setup to a new sh_mtu2_setup_channel function and call it from sh_mtu2_setup. Signed-off-by: Laurent Pinchart <[email protected]> Tested-by: Wolfram Sang <[email protected]>
2014-04-16clocksource: sh_mtu2: Rename struct sh_mtu2_priv to sh_mtu2_deviceLaurent Pinchart1-32/+33
Channel data is private as well, rename priv to device to make the distrinction between the core device and the channels clearer. Signed-off-by: Laurent Pinchart <[email protected]> Tested-by: Wolfram Sang <[email protected]>
2014-04-16clocksource: sh_mtu2: Split channel fields from sh_mtu2_privLaurent Pinchart1-56/+69
Create a new sh_mtu2_channel structure to hold the channel-specific fields in preparation for multiple channels per device support. Signed-off-by: Laurent Pinchart <[email protected]> Tested-by: Wolfram Sang <[email protected]>
2014-04-16clocksource: sh_mtu2: Turn sh_mtu2_priv fields into local variablesLaurent Pinchart1-5/+5
The rate and periodic fields are used in a single function only, as local variables. Remove them from the structure. Signed-off-by: Laurent Pinchart <[email protected]> Tested-by: Wolfram Sang <[email protected]>
2014-04-16clocksource: sh_mtu2: Use request_irq() instead of setup_irq()Laurent Pinchart1-14/+8
The driver claims it needs to register an interrupt handler too early for request_irq(). This might have been true in the past, but the only meaningful difference between request_irq() and setup_irq() today is an additional kzalloc() call in request_irq(). As the driver calls kmalloc() itself we know that the slab allocator is available, we can thus switch to request_irq(). Signed-off-by: Laurent Pinchart <[email protected]> Tested-by: Wolfram Sang <[email protected]>
2014-04-16clocksource: sh_tmu: Sort headers alphabeticallyLaurent Pinchart1-10/+10
This helps locating duplicates and inserting new headers. Signed-off-by: Laurent Pinchart <[email protected]>
2014-04-16clocksource: sh_tmu: Remove FSF mail address from GPL noticeLaurent Pinchart1-4/+0
Do not include the paragraph about writing to the Free Software Foundation's mailing address from the sample GPL notice. The FSF has changed addresses in the past, and may do so again. Linux already includes a copy of the GPL. Signed-off-by: Laurent Pinchart <[email protected]>
2014-04-16clocksource: sh_tmu: Rename clock to "fck" in the non-legacy caseLaurent Pinchart1-1/+2
The sh_tmu driver gets the TMU functional clock using a connection ID of "tmu_fck". While all SH SoCs create clock lookup entries with a NULL device ID and a "tmu_fck" connection ID, the ARM SoCs use the device ID only with a NULL connection ID. This works on legacy platforms but will break on ARM with DT boot. Fix the situation by using a connection ID of "fck" in the non-legacy platform data case. Clock lookup entries will be renamed to use the device ID as well as the connection ID as platforms get moved to new platform data. The legacy code will eventually be dropped, leaving us with device ID based clock lookup, compatible with DT boot. Signed-off-by: Laurent Pinchart <[email protected]>
2014-04-16clocksource: sh_tmu: Add support for multiple channels per deviceLaurent Pinchart1-61/+152
TMU hardware devices can support multiple channels, with global registers and per-channel registers. The sh_tmu driver currently models the hardware with one Linux device per channel. This model makes it difficult to handle global registers in a clean way. Add support for a new model that uses one Linux device per timer with multiple channels per device. This requires changes to platform data, add new channel configuration fields. Support for the legacy model is kept and will be removed after all platforms switch to the new model. Signed-off-by: Laurent Pinchart <[email protected]>
2014-04-16clocksource: sh_tmu: Hardcode TMU clock event and source ratings to 200Laurent Pinchart1-12/+11
All boards use clock event and clock source ratings of 200 for the TMU, hardcode it in the driver. Signed-off-by: Laurent Pinchart <[email protected]>
2014-04-16clocksource: sh_tmu: Replace hardcoded register values with macrosLaurent Pinchart1-5/+14
Define symbolic macros for all used registers bits. Signed-off-by: Laurent Pinchart <[email protected]>
2014-04-16clocksource: sh_tmu: Allocate channels dynamicallyLaurent Pinchart1-7/+20
This prepares the driver for multi-channel support. Signed-off-by: Laurent Pinchart <[email protected]>
2014-04-16clocksource: sh_tmu: Replace kmalloc + memset with kzallocLaurent Pinchart1-5/+1
One kzalloc a day keeps the bugs away. Signed-off-by: Laurent Pinchart <[email protected]>
2014-04-16clocksource: sh_tmu: Add index to struct sh_tmu_channelLaurent Pinchart1-11/+24
Use the index as the timer start/stop bit and when printing messages to identify the channel. Signed-off-by: Laurent Pinchart <[email protected]>
2014-04-16clocksource: sh_tmu: Add memory base to sh_tmu_channel structureLaurent Pinchart1-14/+16
The channel memory base is channel-specific, add it to the channel structure in preparation for support of multiple channels per device. Signed-off-by: Laurent Pinchart <[email protected]>
2014-04-16clocksource: sh_tmu: Constify name argument to sh_tmu_register()Laurent Pinchart1-4/+4
The name argument is assigned to const structure fields only, constify it. Signed-off-by: Laurent Pinchart <[email protected]>
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