Age | Commit message (Collapse) | Author | Files | Lines | |
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2019-03-23 | clocksource/drivers/riscv: Fix clocksource mask | Atish Patra | 1 | -3/+2 | |
For all riscv architectures (RV32, RV64 and RV128), the clocksource is a 64 bit incrementing counter. Fix the clock source mask accordingly. Tested on both 64bit and 32 bit virt machine in QEMU. Fixes: 62b019436814 ("clocksource: new RISC-V SBI timer driver") Signed-off-by: Atish Patra <[email protected]> Signed-off-by: Thomas Gleixner <[email protected]> Reviewed-by: Anup Patel <[email protected]> Cc: Albert Ou <[email protected]> Cc: Daniel Lezcano <[email protected]> Cc: [email protected] Cc: Palmer Dabbelt <[email protected]> Cc: Anup Patel <[email protected]> Cc: Damien Le Moal <[email protected]> Cc: [email protected] Link: https://lkml.kernel.org/r/[email protected] | |||||
2019-02-23 | clocksource/drivers/riscv: Add required checks during clock source init | Atish Patra | 1 | -3/+20 | |
Currently, clocksource registration happens for an invalid cpu for non-smp kernels. This lead to kernel panic as cpu hotplug registration will fail for those cpus. Moreover, riscv_hartid_to_cpuid can return errors now. Do not proceed if hartid or cpuid is invalid. Take this opportunity to print appropriate error strings for different failure cases. Signed-off-by: Atish Patra <[email protected]> Reviewed-by: Anup Patel <[email protected]> Reviewed-by: Palmer Dabbelt <[email protected]> Signed-off-by: Daniel Lezcano <[email protected]> | |||||
2018-12-18 | clocksource/drivers/riscv: Change name riscv_timer to timer-riscv | Daniel Lezcano | 1 | -0/+118 | |
In order to unify the names in this directory, let's rename the driver to be prefixed with timer-* Reviewed-by: Palmer Dabbelt <[email protected]> Signed-off-by: Daniel Lezcano <[email protected]> |