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path: root/drivers/clocksource/timer-riscv.c
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2020-08-20RISC-V: Remove CLINT related code from timer and archAnup Patel1-15/+2
Right now the RISC-V timer driver is convoluted to support: 1. Linux RISC-V S-mode (with MMU) where it will use TIME CSR for clocksource and SBI timer calls for clockevent device. 2. Linux RISC-V M-mode (without MMU) where it will use CLINT MMIO counter register for clocksource and CLINT MMIO compare register for clockevent device. We now have a separate CLINT timer driver which also provide CLINT based IPI operations so let's remove CLINT MMIO related code from arch/riscv directory and RISC-V timer driver. Signed-off-by: Anup Patel <[email protected]> Tested-by: Emil Renner Berhing <[email protected]> Acked-by: Daniel Lezcano <[email protected]> Reviewed-by: Atish Patra <[email protected]> Reviewed-by: Palmer Dabbelt <[email protected]> Signed-off-by: Palmer Dabbelt <[email protected]>
2020-06-09clocksource/drivers/timer-riscv: Use per-CPU timer interruptAnup Patel1-3/+40
Instead of directly calling RISC-V timer interrupt handler from RISC-V local interrupt conntroller driver, this patch implements RISC-V timer interrupt as a per-CPU interrupt using per-CPU APIs of Linux IRQ subsystem. Signed-off-by: Anup Patel <[email protected]> Reviewed-by: Atish Patra <[email protected]> Reviewed-by: Marc Zyngier <[email protected]> Signed-off-by: Palmer Dabbelt <[email protected]>
2020-01-04clocksource: riscv: add notrace to riscv_sched_clockZong Li1-1/+1
When enabling ftrace graph tracer, it gets the tracing clock in ftrace_push_return_trace(). Eventually, it invokes riscv_sched_clock() to get the clock value. If riscv_sched_clock() isn't marked with 'notrace', it will call ftrace_push_return_trace() and cause infinite loop. The result of failure as follow: command: echo function_graph >current_tracer [ 46.176787] Unable to handle kernel paging request at virtual address ffffffe04fb38c48 [ 46.177309] Oops [#1] [ 46.177478] Modules linked in: [ 46.177770] CPU: 0 PID: 256 Comm: $d Not tainted 5.5.0-rc1 #47 [ 46.177981] epc: ffffffe00035e59a ra : ffffffe00035e57e sp : ffffffe03a7569b0 [ 46.178216] gp : ffffffe000d29b90 tp : ffffffe03a756180 t0 : ffffffe03a756968 [ 46.178430] t1 : ffffffe00087f408 t2 : ffffffe03a7569a0 s0 : ffffffe03a7569f0 [ 46.178643] s1 : ffffffe00087f408 a0 : 0000000ac054cda4 a1 : 000000000087f411 [ 46.178856] a2 : 0000000ac054cda4 a3 : 0000000000373ca0 a4 : ffffffe04fb38c48 [ 46.179099] a5 : 00000000153e22a8 a6 : 00000000005522ff a7 : 0000000000000005 [ 46.179338] s2 : ffffffe03a756a90 s3 : ffffffe00032811c s4 : ffffffe03a756a58 [ 46.179570] s5 : ffffffe000d29fe0 s6 : 0000000000000001 s7 : 0000000000000003 [ 46.179809] s8 : 0000000000000003 s9 : 0000000000000002 s10: 0000000000000004 [ 46.180053] s11: 0000000000000000 t3 : 0000003fc815749c t4 : 00000000000efc90 [ 46.180293] t5 : ffffffe000d29658 t6 : 0000000000040000 [ 46.180482] status: 0000000000000100 badaddr: ffffffe04fb38c48 cause: 000000000000000f Signed-off-by: Zong Li <[email protected]> Reviewed-by: Steven Rostedt (VMware) <[email protected]> [[email protected]: cleaned up patch description] Fixes: 92e0d143fdef ("clocksource/drivers/riscv_timer: Provide the sched_clock") Cc: [email protected] Signed-off-by: Paul Walmsley <[email protected]>
2019-11-13riscv: add support for MMIO access to the timer registersChristoph Hellwig1-4/+19
When running in M-mode we can't use the SBI to set the timer, and don't have access to the time CSR as that usually is emulated by M-mode. Instead provide code that directly accesses the MMIO for the timer. Signed-off-by: Christoph Hellwig <[email protected]> Reviewed-by: Anup Patel <[email protected]> Acked-by: Thomas Gleixner <[email protected]> # for drivers/clocksource [[email protected]: updated to apply; fixed checkpatch issue; timex.h now includes asm/mmio.h to resolve header file problems] Signed-off-by: Paul Walmsley <[email protected]>
2019-11-05riscv: abstract out CSR names for supervisor vs machine modeChristoph Hellwig1-4/+4
Many of the privileged CSRs exist in a supervisor and machine version that are used very similarly. Provide versions of the CSR names and fields that map to either the S-mode or M-mode variant depending on a new CONFIG_RISCV_M_MODE kconfig symbol. Contains contributions from Damien Le Moal <[email protected]> and Paul Walmsley <[email protected]>. Signed-off-by: Christoph Hellwig <[email protected]> Acked-by: Thomas Gleixner <[email protected]> # for drivers/clocksource, drivers/irqchip [[email protected]: updated to apply] Signed-off-by: Paul Walmsley <[email protected]>
2019-09-05riscv: don't use the rdtime(h) pseudo-instructionsChristoph Hellwig1-13/+4
If we just use the CSRs that these map to directly the code is simpler and doesn't require extra inline assembly code. Also fix up the top-level comment in timer-riscv.c to not talk about the cycle count or mention details of the clocksource interface, of which this file is just a consumer. Signed-off-by: Christoph Hellwig <[email protected]> Reviewed-by: Atish Patra <[email protected]> Signed-off-by: Paul Walmsley <[email protected]>
2019-08-06RISC-V: Remove per cpu clocksourceAtish Patra1-4/+2
There is only one clocksource in RISC-V. The boot cpu initializes that clocksource. No need to keep a percpu data structure. Signed-off-by: Atish Patra <[email protected]> Signed-off-by: Paul Walmsley <[email protected]> Acked-by: Daniel Lezcano <[email protected]>
2019-03-23clocksource/drivers/riscv: Fix clocksource maskAtish Patra1-3/+2
For all riscv architectures (RV32, RV64 and RV128), the clocksource is a 64 bit incrementing counter. Fix the clock source mask accordingly. Tested on both 64bit and 32 bit virt machine in QEMU. Fixes: 62b019436814 ("clocksource: new RISC-V SBI timer driver") Signed-off-by: Atish Patra <[email protected]> Signed-off-by: Thomas Gleixner <[email protected]> Reviewed-by: Anup Patel <[email protected]> Cc: Albert Ou <[email protected]> Cc: Daniel Lezcano <[email protected]> Cc: [email protected] Cc: Palmer Dabbelt <[email protected]> Cc: Anup Patel <[email protected]> Cc: Damien Le Moal <[email protected]> Cc: [email protected] Link: https://lkml.kernel.org/r/[email protected]
2019-02-23clocksource/drivers/riscv: Add required checks during clock source initAtish Patra1-3/+20
Currently, clocksource registration happens for an invalid cpu for non-smp kernels. This lead to kernel panic as cpu hotplug registration will fail for those cpus. Moreover, riscv_hartid_to_cpuid can return errors now. Do not proceed if hartid or cpuid is invalid. Take this opportunity to print appropriate error strings for different failure cases. Signed-off-by: Atish Patra <[email protected]> Reviewed-by: Anup Patel <[email protected]> Reviewed-by: Palmer Dabbelt <[email protected]> Signed-off-by: Daniel Lezcano <[email protected]>
2018-12-18clocksource/drivers/riscv: Change name riscv_timer to timer-riscvDaniel Lezcano1-0/+118
In order to unify the names in this directory, let's rename the driver to be prefixed with timer-* Reviewed-by: Palmer Dabbelt <[email protected]> Signed-off-by: Daniel Lezcano <[email protected]>
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