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2018-07-25clk: actions: Add S700 SoC clock supportSaravanan Sekar3-0/+613
Add Actions Semi S700 SoC clock support Signed-off-by: Parthiban Nallathambi <[email protected]> Signed-off-by: Saravanan Sekar <[email protected]> Reviewed-by: Manivannan Sadhasivam <[email protected]> Signed-off-by: Stephen Boyd <[email protected]>
2018-07-25clk: actions: Add missing REGMAP_MMIO dependencySaravanan Sekar1-0/+1
Add REGMAP_MMIO as dependency to avoid undefined reference to regmap symbols. Fixes: d85d20053e19 ("clk: actions: Add S900 SoC clock support") Signed-off-by: Saravanan Sekar <[email protected]> Reviewed-by: Andreas Färber <[email protected]> Reviewed-by: Manivannan Sadhasivam <[email protected]> Signed-off-by: Stephen Boyd <[email protected]>
2018-07-25clk: uniphier: add clock frequency support for SPIKunihiko Hayashi2-0/+17
Add clock control for SPI controller on UniPhier SoCs. Signed-off-by: Kunihiko Hayashi <[email protected]> Signed-off-by: Masahiro Yamada <[email protected]> Signed-off-by: Stephen Boyd <[email protected]>
2018-07-25clk: uniphier: add more USB3 PHY clocksMasahiro Yamada1-9/+17
Add USB3 PHY clocks where missing. Use fixed-factor clocks for those without gating. For clarification, prefix clock names with 'ss' or 'hs'. Signed-off-by: Masahiro Yamada <[email protected]> Signed-off-by: Stephen Boyd <[email protected]>
2018-07-25clk: uniphier: add NAND 200MHz clockMasahiro Yamada1-7/+17
The Denali NAND controller IP needs three clocks: - clk: controller core clock - clk_x: bus interface clock - ecc_clk: clock at which ECC circuitry is run Currently, only the first one (50MHz) is provided. The rest of the two clock ports must be connected to the 200MHz clock line. Add this. Signed-off-by: Masahiro Yamada <[email protected]> Signed-off-by: Stephen Boyd <[email protected]>
2018-07-25clk: tegra: make sdmmc2 and sdmmc4 as sdmmc clocksPeter De-Schrijver3-15/+12
These clocks have low jitter paths to certain parents. To model these correctly, use the sdmmc mux divider clock type. Signed-off-by: Peter De-Schrijver <[email protected]> Signed-off-by: Aapo Vienamo <[email protected]> Acked-by: Peter De Schrijver <[email protected]> Signed-off-by: Stephen Boyd <[email protected]>
2018-07-25clk: tegra: Add sdmmc mux divider clockPeter De-Schrijver3-0/+278
Add a clock type to model the sdmmc switch divider clocks which have paths to source clocks bypassing the divider (Low Jitter paths). These are handled by selecting the lj path when the divider is 1 (ie the rate is the parent rate), otherwise the normal path with divider will be selected. Otherwise this clock behaves as a normal peripheral clock. Signed-off-by: Peter De-Schrijver <[email protected]> Signed-off-by: Aapo Vienamo <[email protected]> Acked-by: Peter De Schrijver <[email protected]> Acked-by: Jon Hunter <[email protected]> Signed-off-by: Stephen Boyd <[email protected]>
2018-07-25clk: tegra: Refactor fractional divider calculationPeter De Schrijver4-25/+52
Move this to a separate file so it can be used to calculate the sdmmc clock dividers. Signed-off-by: Peter De-Schrijver <[email protected]> Signed-off-by: Aapo Vienamo <[email protected]> Acked-by: Peter De Schrijver <[email protected]> Acked-by: Jon Hunter <[email protected]> Signed-off-by: Stephen Boyd <[email protected]>
2018-07-25clk: tegra: Fix includes required by fence_udelay()Aapo Vienamo1-0/+1
Add the missing linux/delay.h include statement for udelay() used by fence_udelay() macro. Signed-off-by: Aapo Vienamo <[email protected]> Acked-by: Peter De Schrijver <[email protected]> Acked-by: Jon Hunter <[email protected]> Signed-off-by: Stephen Boyd <[email protected]>
2018-07-25clk: imx6sll: fix missing of_node_put()Nicholas Mc Guire1-0/+1
of_find_compatible_node() is returning a device node with refcount incremented and must be explicitly decremented after the last use which is right after the us in of_iomap() here. Signed-off-by: Nicholas Mc Guire <[email protected]> Fixes: 4a5f720b6542 ("clk: imx: add clock driver for imx6sll") Signed-off-by: Stephen Boyd <[email protected]>
2018-07-25clk: imx6ul: fix missing of_node_put()Nicholas Mc Guire1-0/+1
of_find_compatible_node() is returning a device node with refcount incremented and must be explicitly decremented after the last use which is right after the us in of_iomap() here. Signed-off-by: Nicholas Mc Guire <[email protected]> Fixes: 787b4271a6a0 ("clk: imx: add imx6ul clk tree support") Signed-off-by: Stephen Boyd <[email protected]>
2018-07-25clk: imx: add ocram_s clock for i.mx6sxAnson Huang1-0/+1
i.MX6SX has a 16KB always-on ocram bank called ocram_s, and its clock gate in CCM CCGR1 CG14 needs to be enabled before access, add it to clock tree. Signed-off-by: Anson Huang <[email protected]> Reviewed-by: Fabio Estevam <[email protected]> Signed-off-by: Stephen Boyd <[email protected]>
2018-07-25clk: mvebu: armada-37xx-periph: Fix wrong return value in get_parentGregory CLEMENT1-3/+0
The return value of the get_parent operation is a u8, whereas a -EINVAL was returned. This wrong value was return if the value was bigger that the number of parent but this case was already handled by the core. So we can just remove this chunk of code to fix the issue. Reported-by: Dan Carpenter <[email protected]> Fixes: 9818a7a4fd10 ("clk: mvebu: armada-37xx-periph: prepare cpu clk to be used with DVFS") Signed-off-by: Gregory CLEMENT <[email protected]> Signed-off-by: Stephen Boyd <[email protected]>
2018-07-25clk: clk-fixed-factor: Clear OF_POPULATED flag in case of failureRajan Vaja1-1/+8
Fixed factor clock has two initializations at of_clk_init() time and during platform driver probe. Before of_clk_init() call, node is marked as populated and so its probe never gets called. During of_clk_init() fixed factor clock registration may fail if any of its parent clock is not registered. In this case, it doesn't get chance to retry registration from probe. Clear OF_POPULATED flag if fixed factor clock registration fails so that clock registration is attempted again from probe. Signed-off-by: Rajan Vaja <[email protected]> Signed-off-by: Stephen Boyd <[email protected]>
2018-07-25clk: core: Potentially free connection idMikko Perttunen1-0/+3
Patch "clk: core: Copy connection id" made it so that the connector id 'con_id' is kstrdup_const()ed to cater to drivers that pass non-constant connection ids. The patch added the corresponding kfree_const to __clk_free_clk(), but struct clk's can be freed also via __clk_put(). Add the kfree_const call to __clk_put() and add comments to both functions to remind that the logic in them should be kept in sync. Fixes: 253160a8ad06 ("clk: core: Copy connection id") Signed-off-by: Mikko Perttunen <[email protected]> Reviewed-by: Leonard Crestez <[email protected]> Signed-off-by: Stephen Boyd <[email protected]>
2018-07-25clk: qcom: Update SPDX headers for common filesTaniya Das8-84/+13
SPDX headers updated for common/branch/pll/regmap files. Signed-off-by: Taniya Das <[email protected]> Signed-off-by: Stephen Boyd <[email protected]>
2018-07-24clk: samsung: Remove support for Exynos5440Krzysztof Kozlowski2-168/+0
The Exynos5440 is not actively developed, there are no development boards available and probably there are no real products with it. Remove wide-tree support for Exynos5440. Signed-off-by: Krzysztof Kozlowski <[email protected]> Acked-by: Chanwoo Choi <[email protected]> Acked-by: Stephen Boyd <[email protected]> Acked-by: Sylwester Nawrocki <[email protected]>
2018-07-16clk: qcom: clk-rpmh: Add QCOM RPMh clock driverTaniya Das3-0/+339
Add the RPMh clock driver to control the RPMh managed clock resources on some of the Qualcomm Technologies, Inc. SoCs. Signed-off-by: Taniya Das <[email protected]> [[email protected]: Clean up whitespace, indentation, remove cmd_db_ready check] Signed-off-by: Stephen Boyd <[email protected]>
2018-07-11clk: aspeed: Support HPLL strapping on ast2400Joel Stanley1-13/+29
The HPLL can be configured through a register (SCU24), however some platforms chose to configure it through the strapping settings and do not use the register. This was not noticed as the logic for bit 18 in SCU24 was confused: set means programmed, but the driver read it as set means strapped. This gives us the correct HPLL value on Palmetto systems, from which most of the peripheral clocks are generated. Fixes: 5eda5d79e4be ("clk: Add clock driver for ASPEED BMC SoCs") Cc: [email protected] # v4.15 Reviewed-by: Cédric Le Goater <[email protected]> Signed-off-by: Joel Stanley <[email protected]> Signed-off-by: Stephen Boyd <[email protected]>
2018-07-11ARM: 8776/1: clkdev: Remove duplicated negative index check from __of_clk_get()Geert Uytterhoeven1-3/+0
__of_clk_get() calls of_parse_phandle_with_args(), which rejects negative indices since commit bd69f73f2c81eed9 ("of: Create function for counting number of phandles in a property"). Signed-off-by: Geert Uytterhoeven <[email protected]> Reviewed-by: Stephen Boyd <[email protected]> Signed-off-by: Russell King <[email protected]>
2018-07-09clk: ti: dra7: Add clkctrl clock data for the mcan clocksFaiz Abbas1-0/+1
Add clkctrl data for the m_can clocks and register it within the clkctrl driver Acked-by: Rob Herring <[email protected]> Acked-by: Stephen Boyd <[email protected]> CC: Tero Kristo <[email protected]> Signed-off-by: Faiz Abbas <[email protected]> Signed-off-by: Tony Lindgren <[email protected]>
2018-07-09clk: imx7d: add IMX7D_MU_ROOT_CLKOleksij Rempel1-0/+1
This clock is needed for iMX mailbox driver Signed-off-by: Oleksij Rempel <[email protected]> Reviewed-by: Dong Aisheng <[email protected]> Reviewed-by: Fabio Estevam <[email protected]> Signed-off-by: Stephen Boyd <[email protected]>
2018-07-09clk: mvebu: armada-37xx-periph: switch to SPDX license identifierGregory CLEMENT1-4/+1
Adopt the SPDX license identifier headers to ease license compliance management. Signed-off-by: Gregory CLEMENT <[email protected]> Signed-off-by: Stephen Boyd <[email protected]>
2018-07-09clk: mvebu: armada-37xx-periph: Fix switching CPU rate from 300Mhz to 1.2GHzGregory CLEMENT1-0/+38
Switching the CPU from the L2 or L3 frequencies (300 and 200 Mhz respectively) to L0 frequency (1.2 Ghz) requires a significant amount of time to let VDD stabilize to the appropriate voltage. This amount of time is large enough that it cannot be covered by the hardware countdown register. Due to this, the CPU might start operating at L0 before the voltage is stabilized, leading to CPU stalls. To work around this problem, we prevent switching directly from the L2/L3 frequencies to the L0 frequency, and instead switch to the L1 frequency in-between. The sequence therefore becomes: 1. First switch from L2/L3(200/300MHz) to L1(600MHZ) 2. Sleep 20ms for stabling VDD voltage 3. Then switch from L1(600MHZ) to L0(1200Mhz). It is based on the work done by Ken Ma <[email protected]> Cc: [email protected] Fixes: 2089dc33ea0e ("clk: mvebu: armada-37xx-periph: add DVFS support for cpu clocks") Signed-off-by: Gregory CLEMENT <[email protected]> Signed-off-by: Stephen Boyd <[email protected]>
2018-07-09clk: meson: add gen_clkJerome Brunet4-3/+135
GEN_CLK is able to route several internal clocks to one of the SoC pads. In the future, even more clocks could be made accessible using cts_msr_clk - the clock measure block. Signed-off-by: Jerome Brunet <[email protected]>
2018-07-09clk: meson: gxbb: remove HHI_GEN_CLK_CTNL duplicate definitionJerome Brunet1-1/+0
HHI_GEN_CLK_CTNL is defined twice, just remove the duplicate definition Fixes: 738f66d3211d ("clk: gxbb: add AmLogic GXBB clk controller driver") Acked-by: Martin Blumenstingl <[email protected]> Signed-off-by: Jerome Brunet <[email protected]>
2018-07-09clk: meson-axg: add clocks required by pcie driverYixun Lan2-1/+150
Adding clocks for the pcie driver. Due to the ASIC design, the pcie controller re-use part of the mipi clock logic, so the mipi clock is also added. Tested-by: Jianxin Qin <[email protected]> Signed-off-by: Yixun Lan <[email protected]> [amended to remove unnecessary locales] Signed-off-by: Jerome Brunet <[email protected]>
2018-07-09clk: meson: remove unused clk-audio-divider driverJerome Brunet3-119/+1
clk-audio-divider is no longer used, we can remove it. Acked-by: Neil Armstrong <[email protected]> Signed-off-by: Jerome Brunet <[email protected]>
2018-07-09clk: meson: stop rate propagation for audio clocksJerome Brunet1-9/+7
It is actually a lot easier to setup the PLL with carefully chosen rates than relying on CCF clock propagation for this audio use case. This way, we can make sure we will always be able to provide the common audio clock rates, while having the PLL in the optimal operating range. For this, we stop the rate propagation at the mux picking the PLL and let it round to the closest matching PLL. Doing so, we can use the generic divider for the i2s clock. clk-audio-divider is no longer required. It was a (poor) attempt to use CCF rate propagation while making sure the PLL rate would be high enough to work with audio use cases. Acked-by: Neil Armstrong <[email protected]> Signed-off-by: Jerome Brunet <[email protected]>
2018-07-09clk: meson: axg: add the audio clock controller driverJerome Brunet4-0/+982
The axg audio clock controller is the clock generation unit for the amlogic audio subsystem of A113 based SoCs. It may be clocked by 8 different plls provided by the primary clock controller and also by 10 slave bit clocks and 10 slave sample clocks which may be provided by external components, such as audio codecs, through the SoC pads. It contains several muxes, dividers and gates which are fed into the the different devices of the audio subsystem. Acked-by: Neil Armstrong <[email protected]> Signed-off-by: Jerome Brunet <[email protected]>
2018-07-09clk: meson: add axg audio sclk divider driverJerome Brunet3-1/+252
Add a driver to control the clock divider found in the sample clock generator of the axg audio clock controller. The sclk divider accumulates specific features which make the generic divider unsuitable to control it: - zero based divider (div = val + 1), but zero value gates the clock, so minimum divider value is 2. - lrclk variant may adjust the duty cycle depending the divider value and the 'hi' value. Acked-by: Neil Armstrong <[email protected]> Signed-off-by: Jerome Brunet <[email protected]>
2018-07-09Merge remote-tracking branch 'clk/clk-core-duty-cycle' into next/driversJerome Brunet1-5/+194
2018-07-09clk: meson: add triple phase clock driverJerome Brunet4-0/+94
Add a driver to control the output of the sample clock generator found in the axg audio clock controller. The goal of this driver is to coherently control the phase provided to the different element using the sample clock generator. This simplify the usage of the sample clock generator a lot, without comprising the ability of the SoC. Acked-by: Neil Armstrong <[email protected]> Signed-off-by: Jerome Brunet <[email protected]>
2018-07-09clk: meson: add clk-phase clock driverJerome Brunet3-0/+72
Add a driver based meson clk-regmap to control clock phase on amlogic SoCs Acked-by: Neil Armstrong <[email protected]> Signed-off-by: Jerome Brunet <[email protected]>
2018-07-09clk: meson: clean-up meson clock configurationJerome Brunet1-9/+5
Clean the dependencies in meson clock Kconfig. CLK_AMLOGIC should actually select CLK_REGMAP_MESON which it uses. Also, each platform should select CLK_AMLOGIC, so everything is properly turned on when the platform Kconfig enable each configuration flag Acked-by: Neil Armstrong <[email protected]> Signed-off-by: Jerome Brunet <[email protected]>
2018-07-09clk: meson: remove obsolete register accessJerome Brunet2-69/+4
The legacy method to access the hhi register space is not longer used. We can safely drop it now. Acked-by: Neil Armstrong <[email protected]> Signed-off-by: Jerome Brunet <[email protected]>
2018-07-08clk: tegra: emc: Avoid out-of-bounds bugDmitry Osipenko1-1/+1
Apparently there was an attempt to avoid out-of-bounds accesses when there is only one memory timing available, but there is a typo in the code that neglects that attempt. Signed-off-by: Dmitry Osipenko <[email protected]> Signed-off-by: Stephen Boyd <[email protected]>
2018-07-08clk: tegra: Mark Memory Controller clock as criticalDmitry Osipenko1-2/+3
Memory Controller should be always-on. Currently the sibling EMC clock is marked as critical, let's mark MC clock too for consistency. Signed-off-by: Dmitry Osipenko <[email protected]> Acked-By: Peter De Schrijver <[email protected]> Signed-off-by: Stephen Boyd <[email protected]>
2018-07-08clk: tegra: Make vde a child of pll_c3Thierry Reding1-1/+1
The current default is to leave the VDE clock's parent at the default, which is clk_m. However, that is not a configuration that will allow the VDE to function. Reparent it to pll_c3 instead to make sure the hardware can actually decode video content. Signed-off-by: Thierry Reding <[email protected]> Signed-off-by: Stephen Boyd <[email protected]>
2018-07-08clk: tegra: Make vic03 a child of pll_c3Thierry Reding1-0/+1
By default, the vic03 clock is a child of pll_m but that runs at 924 MHz which is too fast for VIC. Make vic03 a child of pll_c3 by default so it will run at a supported frequency. Signed-off-by: Thierry Reding <[email protected]> Signed-off-by: Stephen Boyd <[email protected]>
2018-07-08clk: tegra: bpmp: Don't crash when a clock fails to registerMikko Perttunen1-3/+9
When registering clocks, we just skip any that fail to register (leaving a NULL hole in the clock table). However, our of_xlate function still tries to dereference each entry while looking for the clock with the requested id, causing a crash if any clocks failed to register. Add a check to of_xlate to skip any NULL clocks. Signed-off-by: Mikko Perttunen <[email protected]> Acked-by: Jon Hunter <[email protected]> Signed-off-by: Stephen Boyd <[email protected]>
2018-07-08clk: rockchip: fix clk_i2sout parent selection bits on rk3399Alberto Panizzo1-1/+1
Register, shift and mask were wrong according to datasheet. Fixes: 115510053e5e ("clk: rockchip: add clock controller for the RK3399") Cc: [email protected] Signed-off-by: Alberto Panizzo <[email protected]> Signed-off-by: Anthony Brandon <[email protected]> Signed-off-by: Heiko Stuebner <[email protected]>
2018-07-06clk: qcom: Move frequency table macro to common fileTaniya Das14-26/+2
Frequency table macro is used by multiple clock drivers, move frequency table macro to common header file. Signed-off-by: Taniya Das <[email protected]> Signed-off-by: Stephen Boyd <[email protected]>
2018-07-06clk: imx51-imx53: Include sizes.h to silence compile errorsStephen Boyd1-0/+1
This driver uses sizes.h, but relies on it being implicitly included somewhere else breaking random direct compilation of the file. Include sizes.h so we can build it those configurations too for better compile coverage. Signed-off-by: Stephen Boyd <[email protected]>
2018-07-06clk: imx51-imx53: Annotate critical clocks as CLK_IS_CRITICALFabio Estevam1-29/+14
Instead of explicitly enabling critical clocks via clk_prepare_enable(), let's use the standard CLK_IS_CRITICAL flag instead, which makes the code a bit shorter. Signed-off-by: Fabio Estevam <[email protected]> Signed-off-by: Stephen Boyd <[email protected]>
2018-07-06clk: imx6sll: add GPIO LPCGsAnson Huang1-0/+6
According to Reference Manual Rev.0, 06/2017, there are GPIO LPCGs defined in CCM CCGRs, add them into clock tree. Signed-off-by: Anson Huang <[email protected]> Reviewed-by: Fabio Estevam <[email protected]> Acked-by: Rob Herring <[email protected]> Signed-off-by: Stephen Boyd <[email protected]>
2018-07-06clk: aspeed: Fix SDCLK nameLei YU1-1/+1
The SDCLK was named SDCLKCLK, and no one has used this yet. Fix it. Signed-off-by: Lei YU <[email protected]> Acked-by: Rob Herring <[email protected]> Signed-off-by: Stephen Boyd <[email protected]>
2018-07-06clk: pxa: export 32kHz PLLRobert Jarzmik3-8/+12
This clock is especially used by the RTC driver, so export it so that devicetree users can use it. Signed-off-by: Robert Jarzmik <[email protected]> Signed-off-by: Stephen Boyd <[email protected]>
2018-07-06clk: aspeed: Mark bclk (PCIe) and dclk (VGA) as criticalJoel Stanley1-2/+2
This is used by the host to talk to the BMC's PCIe slave device. The BMC is not involved, but the clock needs to be enabled so the host can use the device. Fixes: 15ed8ce5f84e ("clk: aspeed: Register gated clocks") Cc: [email protected] # 4.15 Acked-by: Andrew Jeffery <[email protected]> Tested-by: Lei YU <[email protected]> Signed-off-by: Joel Stanley <[email protected]> Signed-off-by: Stephen Boyd <[email protected]>
2018-07-06clk: Add driver for MAX9485Daniel Mack3-0/+394
This patch adds a driver for MAX9485, a programmable audio clock generator. The device requires a 27.000 MHz clock input. It can provide a gated buffered output of its input clock and two gated outputs of a PLL that can generate one out of 16 discrete frequencies. There is only one PLL however, so the two gated outputs will always have the same frequency but they can be switched individually. The driver for this device exposes 4 clocks in total: - MAX9485_MCLKOUT: A gated, buffered output of the input clock - MAX9485_CLKOUT: A PLL that can be configured to 16 different discrete frequencies - MAX9485_CLKOUT[1,2]: Two gated outputs for MAX9485_CLKOUT Some PLL output frequencies can be achieved with different register settings. The driver will select the one with lowest jitter in such cases. Signed-off-by: Daniel Mack <[email protected]> [[email protected]: Use local variable for val in max9485_clkout_recalc_rate() and shorten line of max9485_of_clk_get()] Signed-off-by: Stephen Boyd <[email protected]>
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