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Add the clock driver for the MT8516 SoC.
Signed-off-by: Fabien Parent <[email protected]>
Signed-off-by: Stephen Boyd <[email protected]>
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It's just some static data that doesn't get changed after being used.
Mark it const everywhere.
Cc: Alexandre Belloni <[email protected]>
Signed-off-by: Stephen Boyd <[email protected]>
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Add a driver for the PMC clocks of the sam9c60.
Signed-off-by: Alexandre Belloni <[email protected]>
[[email protected]: Staticize spinlock]
Signed-off-by: Stephen Boyd <[email protected]>
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The Memory Controller (MC) clock rate can't be simply changed and nothing
in kernel need to change the rate, hence let's make the clock read-only.
This id also needed for the EMC driver because timing configuration may
require the MC clock diver to be disabled, that is handled by the EMC
clock / EMC driver integration and CLK framework shall not touch the
MC divider configuration on the EMC clock rate change.
Signed-off-by: Dmitry Osipenko <[email protected]>
Signed-off-by: Stephen Boyd <[email protected]>
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There is no justification for the BUG() in this code.
Signed-off-by: Dmitry Osipenko <[email protected]>
Signed-off-by: Stephen Boyd <[email protected]>
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When a clk user requests rate that is higher than the maximum possible,
the rate shall be clamped to the maximum and not to the current value.
Signed-off-by: Dmitry Osipenko <[email protected]>
Signed-off-by: Stephen Boyd <[email protected]>
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The timings parser doesn't append timings, but instead it parses only
the first timing and hence doesn't store all of the timings when
device-tree has timings for multiple RAM codes. In a result EMC scaling
doesn't work if timings are missing.
Tested-by: Steev Klimaszewski <[email protected]>
Signed-off-by: Dmitry Osipenko <[email protected]>
Signed-off-by: Stephen Boyd <[email protected]>
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The EMC clock marked as critical, hence it is already enabled at the
registration time.
Signed-off-by: Dmitry Osipenko <[email protected]>
Signed-off-by: Stephen Boyd <[email protected]>
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The PLLs on the sam9x60 (PLLA and USB PLL) use a different register set and
programming model than the previous SoCs.
Signed-off-by: Alexandre Belloni <[email protected]>
Signed-off-by: Stephen Boyd <[email protected]>
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The sam9x60 cpu clock is located at a different offset but is otherwise
similar to the master clock.
Signed-off-by: Alexandre Belloni <[email protected]>
Signed-off-by: Stephen Boyd <[email protected]>
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The sam9x60 USB clock supports four different parents, ensure they can be
selected.
Signed-off-by: Alexandre Belloni <[email protected]>
Signed-off-by: Stephen Boyd <[email protected]>
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The PCR register layout for GCLKCSS is changing for the future SoCs, allow
configuring it.
Signed-off-by: Alexandre Belloni <[email protected]>
Signed-off-by: Stephen Boyd <[email protected]>
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The PCR register actually changed layout for each SoC. By chance, this
didn't have impact on sama5d[2-4] support but since sama5d3, PID is seven
bits wide and sama5d4 and sama5d2 don't have DIV.
For the DT backward compatibility, keep the layout as is.
Signed-off-by: Alexandre Belloni <[email protected]>
Signed-off-by: Stephen Boyd <[email protected]>
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STM32F769 clocks are derived from STM32746 clocks.
main differences are:
- new source clock for SAI1 and SAI2 (HSI or HSE)
- Add DFSDM & DSI clocks
Signed-off-by: Gabriel Fernandez <[email protected]>
Signed-off-by: Stephen Boyd <[email protected]>
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The sama5d3 slow RC oscillator as a different startup time than all the
previous SoCs. Handle that using its own compatible.
Signed-off-by: Alexandre Belloni <[email protected]>
Signed-off-by: Stephen Boyd <[email protected]>
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Remove the need for child nodes in the sckc binding and register the whole
sckc tree (3 clocks in total) from the sckc node.
DT backward compatibility is kept by looking for properties in child nodes
when they are not present in the sckc node.
Signed-off-by: Alexandre Belloni <[email protected]>
Signed-off-by: Stephen Boyd <[email protected]>
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Increase size of cmux_to_group array, to accomdate entry of
-1 termination.
Added -1, terminated, entry for 4080_cmux_grpX.
Signed-off-by: Yogesh Gaur <[email protected]>
Signed-off-by: Vabhav Sharma <[email protected]>
Acked-by: Scott Wood <[email protected]>
Signed-off-by: Stephen Boyd <[email protected]>
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Enable clock driver by adding clock configuration for ls1028a chip.
Signed-off-by: Yuantian Tang <[email protected]>
Signed-off-by: Stephen Boyd <[email protected]>
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More PLL divider clocks are needed by clock consumer IP. So enlarge
the PLL divider array to accommodate more divider clocks.
Signed-off-by: Yuantian Tang <[email protected]>
Signed-off-by: Stephen Boyd <[email protected]>
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RNG and TIMER12 are reserved for secure side usage only on HS devices,
so disable their clkctrl clocks on HS SoCs also.
Signed-off-by: Tero Kristo <[email protected]>
Tested-by: Andrew F. Davis <[email protected]>
Signed-off-by: Stephen Boyd <[email protected]>
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Certain clkctrl clocks (like the USB_OTG_SS4) do not exist on some
variants of the dra7x SoC. Append a flag for these clocks and skip
the registration in cases where the clocks do not exist.
Reported-by: Peter Ujfalusi <[email protected]>
Signed-off-by: Tero Kristo <[email protected]>
Signed-off-by: Stephen Boyd <[email protected]>
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There is one instance outside the TI clock driver that needs the info
whether a clock is an OMAP HW clock or not. Thus, move the function
declaration into the public header.
Signed-off-by: Tero Kristo <[email protected]>
Signed-off-by: Stephen Boyd <[email protected]>
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git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux into clk-imx
Pull i.MX7UPL clk changes from Shawn Guo:
- Remove SNVS clock from i.MX7UPL clock driver and bindings, as the
clock will be visible on M4 core only, and never be accessed by
Cortex-A cores
* tag 'clk-imx7ulp-5.2' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux:
dt-bindings: clock: imx7ulp: remove SNVS clock
clk: imx7ulp: remove snvs clock
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git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux into clk-imx
Pull i.MX5 clk changes from Shawn Guo:
- A couple of patches from Jonathan Neuschäfer to improve i.MX5 clock
driver for i.MX50 support
- Rename file clk-imx51-imx53.c to clk-imx5.c, as it covers support for
all i.MX5 series SoCs including i.MX50
* tag 'clk-imx5-5.2' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux:
clk: imx: rename clk-imx51-imx53.c to clk-imx5.c
clk: imx5: Fix i.MX50 ESDHC clock registers
clk: imx5: Fix i.MX50 mainbus clock registers
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According to the Tegra124 TRM documentation, PLLM_MISC2 register doesn't
have the lock-enable bit as well as any other PLLM-related register. Hence
PLLM re-locking can't be initiated by software. The incorrect bit setting
should have been harmless since that bit is undefined according to TRM.
Tested-by: Steev Klimaszewski <[email protected]>
Signed-off-by: Dmitry Osipenko <[email protected]>
Acked-By: Peter De Schrijver <[email protected]>
Signed-off-by: Stephen Boyd <[email protected]>
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There are wrongly set parenthesis in the code that are resulting in a
wrong configuration being programmed for PLLM. The original fix was made
by Danny Huang in the downstream kernel. The patch was tested on Nyan Big
Tegra124 chromebook, PLLM rate changing works correctly now and system
doesn't lock up after changing the PLLM rate due to EMC scaling.
Cc: <[email protected]>
Tested-by: Steev Klimaszewski <[email protected]>
Signed-off-by: Dmitry Osipenko <[email protected]>
Acked-By: Peter De Schrijver <[email protected]>
Signed-off-by: Stephen Boyd <[email protected]>
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Lochnagar is an evaluation and development board for Cirrus
Logic Smart CODEC and Amp devices. It allows the connection of
most Cirrus Logic devices on mini-cards, as well as allowing
connection of various application processor systems to provide a
full evaluation platform. This driver supports the board
controller chip on the Lochnagar board.
The Lochnagar can take several input clocks from the host system,
provides several of its own clock sources, and provides extensive
routing options for those clocks to be supplied to the attached
CODEC/Amp device.
Signed-off-by: Charles Keepax <[email protected]>
Signed-off-by: Stephen Boyd <[email protected]>
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Now that clk_{readl,writel} is just an alias for {readl,writel}, we can
switch all users of clk_* to use the accessors directly and remove the
helpers.
Signed-off-by: Jonas Gorski <[email protected]>
[[email protected]: Also convert renesas file so that this can be
compile independently]
Signed-off-by: Stephen Boyd <[email protected]>
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Add a clock specific flag to switch register accesses to big endian, to
allow runtime configuration of big endian mux clocks.
Signed-off-by: Jonas Gorski <[email protected]>
Signed-off-by: Stephen Boyd <[email protected]>
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Add a clock specific flag to switch register accesses to big endian, to
allow runtime configuration of big endian multiplier clocks.
Signed-off-by: Jonas Gorski <[email protected]>
Signed-off-by: Stephen Boyd <[email protected]>
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Add a clock specific flag to switch register accesses to big endian, to
allow runtime configuration of big endian gated clocks.
Signed-off-by: Jonas Gorski <[email protected]>
Signed-off-by: Stephen Boyd <[email protected]>
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Add a clock specific flag to switch register accesses to big endian, to
allow runtime configuration of big endian fractional divider clocks.
Signed-off-by: Jonas Gorski <[email protected]>
Signed-off-by: Stephen Boyd <[email protected]>
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Add a clock specific flag to switch register accesses to big endian, to
allow runtime configuration of big endian divider clocks.
Signed-off-by: Jonas Gorski <[email protected]>
Signed-off-by: Stephen Boyd <[email protected]>
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This structure can be full of junk from the stack if we don't initialize
it. The clk framework tests clk_init_data::parent_names for non-NULL and
then considers that as the parent name pointer, but if it's full of junk
then we'll try to deref a bad pointer and oops the system. Let's
initialize the structure so that only clk_init_data::parent_names or
clk_init_data::parent_data is set, and not both.
Reported-by: "kernelci.org bot" <[email protected]>
Tested-by: Geert Uytterhoeven <[email protected]>
Tested-by: Tony Lindgren <[email protected]>
Fixes: ecbf3f1795fd ("clk: fixed-factor: Let clk framework find parent")
Signed-off-by: Stephen Boyd <[email protected]>
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This is mostly a revert of commit 55bb6a633c33 ("clk: rockchip: mark
noc and some special clk as critical on rk3288") except that we're
keeping "pmu_hclk_otg0" as critical still.
NOTE: turning these clocks off doesn't seem to do a whole lot in terms
of power savings (checking the power on the logic rail). It appears
to save maybe 1-2mW. ...but still it seems like we should turn the
clocks off if they aren't needed.
About "pmu_hclk_otg0" (the one clock from the original commit we're
still keeping critical) from an email thread:
> pmu ahb clock
>
> Function: Clock to pmu module when hibernation and/or ADP is
> enabled. Must be greater than or equal to 30 MHz.
>
> If the SOC design does not support hibernation/ADP function, only have
> hclk_otg, this clk can be switched according to the usage of otg.
> If the SOC design support hibernation/ADP, has two clocks, hclk_otg and
> pmu_hclk_otg0.
> Hclk_otg belongs to the closed part of otg logic, which can be switched
> according to the use of otg.
>
> pmu_hclk_otg0 belongs to the always on part.
>
> As for whether pmu_hclk_otg0 can be turned off when otg is not in use,
> we have not tested. IC suggest make pmu_hclk_otg0 always on.
For the rest of the clocks:
atclk: No documentation about this clock other than that it goes to
the CPU. CPU functions fine without it on. Maybe needed for JTAG?
jtag: Presumably this clock is only needed if you're debugging with
JTAG. It doesn't seem like it makes sense to waste power for every
rk3288 user. In any case to do JTAG you'd need private patches to
adjust the pinctrl the mux the JTAG out anyway.
pclk_dbg, pclk_core_niu: On veyron Chromebooks we turn these two
clocks on only during kernel panics in order to access some coresight
registers. Since nothing in the upstream kernel does this we should
be able to leave them off safely. Maybe also needed for JTAG?
hsicphy12m_xin12m: There is no indication of why this clock would need
to be turned on for boards that don't use HSIC.
pclk_ddrupctl[0-1], pclk_publ0[0-1]: On veyron Chromebooks we turn
these 4 clocks on only when doing DDR transitions and they are off
otherwise. I see no reason why they'd need to be on in the upstream
kernel which doesn't support DDRFreq.
Signed-off-by: Douglas Anderson <[email protected]>
Reviewed-by: Elaine Zhang <[email protected]>
Signed-off-by: Heiko Stuebner <[email protected]>
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clk_gate_ufs_subsys is a system bus clock, turning off it will
introduce lockup issue during system suspend flow. Let's mark
clk_gate_ufs_subsys as critical clock, thus keeps it on during
system suspend and resume.
Fixes: d374e6fd5088 ("clk: hisilicon: Add clock driver for hi3660 SoC")
Cc: [email protected]
Cc: Zhong Kaihua <[email protected]>
Cc: John Stultz <[email protected]>
Cc: Zhangfei Gao <[email protected]>
Suggested-by: Dong Zhang <[email protected]>
Signed-off-by: Leo Yan <[email protected]>
Signed-off-by: Stephen Boyd <[email protected]>
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Initially Common Clock Framework isn't aware of the clock-enable status,
this results in enabling of clocks that were enabled by bootloader. This
is not a big deal for a regular clock-gates, but for PLL's it may have
some unpleasant consequences. Thus re-enabling PLLX (the main CPU parent
clock) may result in extra long period of PLL re-locking.
Acked-by: Peter De Schrijver <[email protected]>
Signed-off-by: Dmitry Osipenko <[email protected]>
Signed-off-by: Stephen Boyd <[email protected]>
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Convert this driver to a more modern way of specifying parents now that
we have a way to specify clk parents by DT index. This lets us nicely
avoid a problem where a parent clk name isn't know because the parent
clk hasn't been registered yet.
Cc: Miquel Raynal <[email protected]>
Cc: Jerome Brunet <[email protected]>
Cc: Russell King <[email protected]>
Cc: Michael Turquette <[email protected]>
Cc: Jeffrey Hugo <[email protected]>
Cc: Chen-Yu Tsai <[email protected]>
Tested-by: Jeffrey Hugo <[email protected]>
Signed-off-by: Stephen Boyd <[email protected]>
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Some clk providers are simple DT nodes that only have a 'clocks'
property without having an associated 'clock-names' property. In these
cases, we want to let these clk providers point to their parent clks
without having to dereference the 'clocks' property at probe time to
figure out the parent's globally unique clk name. Let's add an 'index'
property to the parent_data structure so that clk providers can indicate
that their parent is a particular index in the 'clocks' DT property.
Cc: Miquel Raynal <[email protected]>
Cc: Jerome Brunet <[email protected]>
Cc: Russell King <[email protected]>
Cc: Michael Turquette <[email protected]>
Cc: Jeffrey Hugo <[email protected]>
Cc: Chen-Yu Tsai <[email protected]>
Tested-by: Jeffrey Hugo <[email protected]>
Signed-off-by: Stephen Boyd <[email protected]>
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In addition to looking for DT based parents, support clkdev based
clk_lookups. This should allow non-DT based clk drivers to participate
in the parent lookup process.
Cc: Miquel Raynal <[email protected]>
Cc: Jerome Brunet <[email protected]>
Cc: Russell King <[email protected]>
Cc: Michael Turquette <[email protected]>
Cc: Jeffrey Hugo <[email protected]>
Cc: Chen-Yu Tsai <[email protected]>
Tested-by: Jeffrey Hugo <[email protected]>
Signed-off-by: Stephen Boyd <[email protected]>
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The common clk framework is lacking in ability to describe the clk
topology without specifying strings for every possible parent-child
link. There are a few drawbacks to the current approach:
1) String comparisons are used for everything, including describing
topologies that are 'local' to a single clock controller.
2) clk providers (e.g. i2c clk drivers) need to create globally unique
clk names to avoid collisions in the clk namespace, leading to awkward
name generation code in various clk drivers.
3) DT bindings may not fully describe the clk topology and linkages
between clk controllers because drivers can easily rely on globally unique
strings to describe connections between clks.
This leads to confusing DT bindings, complicated clk name generation
code, and inefficient string comparisons during clk registration just so
that the clk framework can detect the topology of the clk tree.
Furthermore, some drivers call clk_get() and then __clk_get_name() to
extract the globally unique clk name just so they can specify the parent
of the clk they're registering. We have of_clk_parent_fill() but that
mostly only works for single clks registered from a DT node, which isn't
the norm. Let's simplify this all by introducing two new ways of
specifying clk parents.
The first method is an array of pointers to clk_hw structures
corresponding to the parents at that index. This works for clks that are
registered when we have access to all the clk_hw pointers for the
parents.
The second method is a mix of clk_hw pointers and strings of local and
global parent clk names. If the .fw_name member of the map is set we'll
look for that clk by performing a DT based lookup of the device the clk
is registered with and the .name specified in the map. If that fails,
we'll fallback to the .name member and perform a global clk name lookup
like we've always done before.
Using either one of these new methods is entirely optional. Existing
drivers will continue to work, and they can migrate to this new approach
as they see fit. Eventually, we'll want to get rid of the 'parent_names'
array in struct clk_init_data and use one of these new methods instead.
Cc: Miquel Raynal <[email protected]>
Cc: Jerome Brunet <[email protected]>
Cc: Russell King <[email protected]>
Cc: Michael Turquette <[email protected]>
Cc: Jeffrey Hugo <[email protected]>
Cc: Chen-Yu Tsai <[email protected]>
Cc: Rob Herring <[email protected]>
Tested-by: Jeffrey Hugo <[email protected]>
Signed-off-by: Stephen Boyd <[email protected]>
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In some circumstances drivers register clks early and don't have access
to a struct device because the device model isn't initialized yet. Add
an API to let drivers register clks associated with a struct device_node
so that these drivers can participate in getting parent clks through DT.
Cc: Miquel Raynal <[email protected]>
Cc: Jerome Brunet <[email protected]>
Cc: Russell King <[email protected]>
Cc: Michael Turquette <[email protected]>
Cc: Jeffrey Hugo <[email protected]>
Cc: Chen-Yu Tsai <[email protected]>
Cc: Rob Herring <[email protected]>
Tested-by: Jeffrey Hugo <[email protected]>
Signed-off-by: Stephen Boyd <[email protected]>
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Split out the body of the clk_register() function so it can be shared
between the different types of registration APIs (DT, device).
Cc: Miquel Raynal <[email protected]>
Cc: Jerome Brunet <[email protected]>
Cc: Russell King <[email protected]>
Cc: Michael Turquette <[email protected]>
Cc: Jeffrey Hugo <[email protected]>
Cc: Chen-Yu Tsai <[email protected]>
Cc: Rob Herring <[email protected]>
Tested-by: Jeffrey Hugo <[email protected]>
Signed-off-by: Stephen Boyd <[email protected]>
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We don't need to hold the 'clocks_mutex' here when we're creating a clk
pointer from a clk_lookup structure. Instead, we just need to make sure
that the lookup doesn't go away while we dereference the lookup pointer
to extract the clk_hw pointer out of it. Let's move things around
slightly so that we have a new function to get the clk_hw out of the
lookup with the right locking and then chain the two together for what
used to be __clk_get_sys().
Cc: Miquel Raynal <[email protected]>
Cc: Jerome Brunet <[email protected]>
Cc: Russell King <[email protected]>
Cc: Michael Turquette <[email protected]>
Cc: Jeffrey Hugo <[email protected]>
Cc: Chen-Yu Tsai <[email protected]>
Tested-by: Jeffrey Hugo <[email protected]>
Signed-off-by: Stephen Boyd <[email protected]>
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The driver retrieves the clock tree by querying the ATF for the clock
names, the clock topology, the parents and other attributes. The driver
needs to unmarshal the responses.
The definition of the fields in the firmware responses to the queries is
inconsistent. Some are specified as a mask, some as a shift, and by the
length of the previous field.
Define C structs for the entire firmware responses to avoid passing
pointers to arrays of an implicit size and make the format of the
responses to the queries obvious.
Signed-off-by: Michael Tretter <[email protected]>
Reviewed-by: Jolly Shah <[email protected]>
[[email protected]: Drop 0 initializers because sparse complains]
Signed-off-by: Stephen Boyd <[email protected]>
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https://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux into clk-fixes
Pull Allwinner clk fixes from Maxime Ripard:
- Some fixes for odd cases of the NKMP clocks
* tag 'clk-fixes-for-5.1' of https://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux:
clk: sunxi-ng: nkmp: Explain why zero width check is needed
clk: sunxi-ng: nkmp: Avoid GENMASK(-1, 0)
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Add eclk mux and clock divider table. Also change the video engine reset
to the correct clock; it was previously on the video capture but needs
to be on the video engine clock.
Signed-off-by: Eddie James <[email protected]>
Reviewed-by: Joel Stanley <[email protected]>
Signed-off-by: Stephen Boyd <[email protected]>
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There are a few spelling mistakes in comments and a pr_err
error message. Fix these.
Signed-off-by: Colin Ian King <[email protected]>
Reviewed-by: Mukesh Ojha <[email protected]>
Signed-off-by: Stephen Boyd <[email protected]>
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We recently introduced a change to support devm clk lookups. That change
introduced a code-path that used clk_find() without holding the
'clocks_mutex'. Unfortunately, clk_find() iterates over the 'clocks'
list and so we need to prevent the list from being modified at the same
time. Do this by holding the mutex and checking to make sure it's held
while iterating the list.
Note, we don't really care if the lookup is freed after we find it with
clk_find() because we're just doing a pointer comparison, but if we did
care we would need to keep holding the mutex while we dereference the
clk_lookup pointer.
Fixes: 3eee6c7d119c ("clkdev: add managed clkdev lookup registration")
Cc: Miquel Raynal <[email protected]>
Cc: Jerome Brunet <[email protected]>
Cc: Russell King <[email protected]>
Cc: Michael Turquette <[email protected]>
Cc: Jeffrey Hugo <[email protected]>
Cc: Chen-Yu Tsai <[email protected]>
Cc: Matti Vaittinen <[email protected]>
Acked-by: Matti Vaittinen <[email protected]>
Tested-by: Jeffrey Hugo <[email protected]>
Signed-off-by: Stephen Boyd <[email protected]>
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As the driver is handling all i.MX5 series SoCs inlcuding i.MX50, rather
than just i.MX51 and i.MX53, let's rename it to clk-imx5.c.
Signed-off-by: Shawn Guo <[email protected]>
Reviewed-by: Stephen Boyd <[email protected]>
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