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Add support for the camera clock controller found on SM8250.
Based on the downstream driver.
Signed-off-by: Jonathan Marek <[email protected]>
Reviewed-by: Robert Foss <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
[[email protected]: Add UL to avoid decimal problems]
Signed-off-by: Stephen Boyd <[email protected]>
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Ported over from the downstream driver. Will be used by SM8250 CAMCC.
Signed-off-by: Jonathan Marek <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Stephen Boyd <[email protected]>
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Fix gcc '-Wunused-const-variable' warnings:
drivers/clk/qcom/gcc-mdm9607.c:122:37: warning: 'gcc_xo_gpll0_gpll1'
defined but not used [-Wunused-const-variable=]
drivers/clk/qcom/gcc-mdm9607.c:116:32: warning: 'gcc_xo_gpll0_gpll1_map'
defined but not used [-Wunused-const-variable=]
drivers/clk/qcom/gcc-mdm9607.c:42:37: warning: 'gcc_xo_sleep' defined
but not used [-Wunused-const-variable=]
drivers/clk/qcom/gcc-mdm9607.c:37:32: warning: 'gcc_xo_sleep_map'
defined but not used [-Wunused-const-variable=]
Let's remove them.
Signed-off-by: Pu Lehui <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Reported-by: kbuild test robot <[email protected]>
Signed-off-by: Stephen Boyd <[email protected]>
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Add compatible for rpm smd clocks, PMIC and bus clocks which are required
on MSM8226 for clients to vote on.
Signed-off-by: Bartosz Dudziak <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Stephen Boyd <[email protected]>
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Modify existing MSM8974 driver to support MSM8226 SoC. Override frequencies
which are different in this older chip. Register all the clocks to the
framework for the clients to be able to request for them.
Signed-off-by: Bartosz Dudziak <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Stephen Boyd <[email protected]>
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Add the clocks supported in global clock controller, which clock the
peripherals like BLSPs, SDCC, USB, MDSS etc. Register all the clocks
to the clock framework for the clients to be able to request for them.
Signed-off-by: Konrad Dybcio <[email protected]>
Signed-off-by: Martin Botka <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Reviewed-by: Bjorn Andersson <[email protected]>
[[email protected]: Mark gcc_sm6125_hws array static]
Signed-off-by: Stephen Boyd <[email protected]>
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There is a requirement to support 52MHz for qup clocks for bluetooth
usecase, thus update the frequency table to support the frequency.
Fixes: a3cc092196ef ("clk: qcom: Add Global Clock controller (GCC) driver for SC7280")
Signed-off-by: Taniya Das <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Stephen Boyd <[email protected]>
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If the bypass_reg is set, then we can return the bypass parent, however,
if there is not a bypass_reg, we need to figure what the correct parent
mux is.
The previous code never handled the parent mux if there was a
bypass_reg.
Fixes: 80c6b7a0894f ("clk: socfpga: agilex: add clock driver for the Agilex platform")
Cc: [email protected]
Signed-off-by: Dinh Nguyen <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Stephen Boyd <[email protected]>
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The EMAC clocks on Stratix10/Agilex/N5X have an additional bypass that
was not being accounted for. The bypass selects between
emaca_clk/emacb_clk and boot_clk.
Because the bypass register offset is different between Stratix10 and
Agilex/N5X, it's best to create a new function to calculate the bypass.
Fixes: 80c6b7a0894f ("clk: socfpga: agilex: add clock driver for the Agilex platform")
Cc: [email protected]
Signed-off-by: Dinh Nguyen <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Stephen Boyd <[email protected]>
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Each of these clocks(s2f_usr0/1, sdmmc_clk, gpio_db, emac_ptp,
emac0/1/2) have a bypass setting that can use the boot_clk. The
previous representation was not correct.
Fix the representation.
Fixes: 80c6b7a0894f ("clk: socfpga: agilex: add clock driver for the Agilex platform")
Cc: [email protected]
Signed-off-by: Dinh Nguyen <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Stephen Boyd <[email protected]>
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Early documentation had a noc_clk, but in reality, it's just the
noc_free_clk. Remove the noc_clk clock and just use the noc_free_clk.
Fixes: 80c6b7a0894f ("clk: socfpga: agilex: add clock driver for the Agilex platform")
Cc: [email protected]
Signed-off-by: Dinh Nguyen <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Stephen Boyd <[email protected]>
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The purpose of the device-managed functions is to bind the life-time of an
object to that of a parent device object.
This is not the case for the 'vdd-cpu' regulator in this driver. A
reference is obtained via devm_regulator_get() and immediately released
with devm_regulator_put().
In this case, the usage of devm_ functions is slightly excessive, as the
un-managed versions of these functions is a little cleaner (and slightly
more economical in terms of allocation).
This change converts the devm_regulator_{get,put}() to
regulator_{get,put}() in the get_alignment_from_regulator() function of
this driver.
Signed-off-by: Alexandru Ardelean <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Reviewed-by: Thierry Reding <[email protected]>
Signed-off-by: Stephen Boyd <[email protected]>
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'clk_hw_set_rate_range()' does not return any error code and 'ret' is
known to be 0 at this point, so this message can never be displayed.
Remove it.
Fixes: 3fde0e16d016 ("drivers: clk: Add ZynqMP clock driver")
Signed-off-by: Christophe JAILLET <[email protected]>
Link: https://lore.kernel.org/r/71a9fed5f762a71248b8ac73c0a15af82f3ce1e2.1619867987.git.christophe.jaillet@wanadoo.fr
Reviewed-by: Michael Tretter <[email protected]>
Signed-off-by: Stephen Boyd <[email protected]>
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When the firmware code is disabled, the incomplete error handling
in the clk driver causes compile-time warnings:
drivers/clk/zynqmp/pll.c: In function 'zynqmp_pll_recalc_rate':
drivers/clk/zynqmp/pll.c:147:29: error: 'fbdiv' is used uninitialized [-Werror=uninitialized]
147 | rate = parent_rate * fbdiv;
| ~~~~~~~~~~~~^~~~~~~
In function 'zynqmp_pll_get_mode',
inlined from 'zynqmp_pll_recalc_rate' at drivers/clk/zynqmp/pll.c:148:6:
drivers/clk/zynqmp/pll.c:61:27: error: 'ret_payload' is used uninitialized [-Werror=uninitialized]
61 | return ret_payload[1];
| ~~~~~~~~~~~^~~
drivers/clk/zynqmp/pll.c: In function 'zynqmp_pll_recalc_rate':
drivers/clk/zynqmp/pll.c:53:13: note: 'ret_payload' declared here
53 | u32 ret_payload[PAYLOAD_ARG_CNT];
| ^~~~~~~~~~~
drivers/clk/zynqmp/clk-mux-zynqmp.c: In function 'zynqmp_clk_mux_get_parent':
drivers/clk/zynqmp/clk-mux-zynqmp.c:57:16: error: 'val' is used uninitialized [-Werror=uninitialized]
57 | return val;
| ^~~
As it was apparently intentional to support this for compile testing
purposes, change the code to have just enough error handling for the
compiler to not notice the remaining bugs.
Fixes: 21f237534661 ("clk: zynqmp: Drop dependency on ARCH_ZYNQMP")
Co-developed-by: Arnd Bergmann <[email protected]>
Signed-off-by: Michal Simek <[email protected]>
Link: https://lore.kernel.org/r/f1c4e8c903fe2d5df5413421920a56890a46387a.1624356908.git.michal.simek@xilinx.com
Signed-off-by: Stephen Boyd <[email protected]>
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AM64 has 9 instances of EPWM modules. And each instance has a clk to
Timer-Base sub-module that can be controlled by Control module. Update
the driver with all the 9 instance of clocks associated to
ti,am64-epwm-tbclk.
Signed-off-by: Lokesh Vutla <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Reviewed-by: Tero Kristo <[email protected]>
Signed-off-by: Stephen Boyd <[email protected]>
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Remove the PLL clock gates as the allowing to gate the sys1_pll_266m breaks
the uSDHC module which is sporadically unable to enumerate devices after
this change. Also it makes AMP clock management harder with no obvious
benefit to Linux, so just revert the change.
Link: https://lore.kernel.org/r/[email protected]
Fixes: b04383b6a558 ("clk: imx8mq: Define gates for pll1/2 fixed dividers")
Signed-off-by: Lucas Stach <[email protected]>
Reviewed-by: Abel Vesa <[email protected]>
Signed-off-by: Abel Vesa <[email protected]>
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Since CPU clocks are managed by CPUFREQ and ATF, do not enable
runtime PM otherwise rpm gets out of status as cpufreq
also manages clock states.
Signed-off-by: Nitin Garg <[email protected]>
Signed-off-by: Dong Aisheng <[email protected]>
Reviewed-by: Abel Vesa <[email protected]>
Signed-off-by: Abel Vesa <[email protected]>
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Add clock parent save and restore.
Signed-off-by: Dong Aisheng <[email protected]>
Reviewed-by: Abel Vesa <[email protected]>
Signed-off-by: Abel Vesa <[email protected]>
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Display sub-system has special clock settings in SCFW, the
bypassed clock is used instead of PLL in Linux kernel clock
tree, so when saving clock rate, need to save non-cached clock
rate for Display sub-system's bypass clocks, and other clocks
still use the cached clock rate which is with runtime PM ON.
Signed-off-by: Anson Huang <[email protected]>
Signed-off-by: Dong Aisheng <[email protected]>
Reviewed-by: Abel Vesa <[email protected]>
Signed-off-by: Abel Vesa <[email protected]>
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Add A72 clock to support cpufreq on A72 cluster.
Signed-off-by: Anson Huang <[email protected]>
Signed-off-by: Dong Aisheng <[email protected]>
Reviewed-by: Abel Vesa <[email protected]>
Signed-off-by: Abel Vesa <[email protected]>
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Add i.MX8QM cpufreq support for A53 cluster.
Signed-off-by: Anson Huang <[email protected]>
Signed-off-by: Dong Aisheng <[email protected]>
Reviewed-by: Abel Vesa <[email protected]>
Signed-off-by: Abel Vesa <[email protected]>
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PI PLL does not support enable/disable. So bypass it's
enable status restore.
Signed-off-by: Dong Aisheng <[email protected]>
Reviewed-by: Abel Vesa <[email protected]>
Signed-off-by: Abel Vesa <[email protected]>
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detach pd if can't power up as it may be allocated to a differet
partition.
Signed-off-by: Dong Aisheng <[email protected]>
Reviewed-by: Abel Vesa <[email protected]>
Signed-off-by: Abel Vesa <[email protected]>
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CPU clock is managed by ATF. No need save and restore.
Signed-off-by: Dong Aisheng <[email protected]>
Reviewed-by: Abel Vesa <[email protected]>
Signed-off-by: Abel Vesa <[email protected]>
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Because digital pll for parallel interface is on by default, and
not provide enable/disable function by scu, so add the related ops
for this kind of clocks.
Signed-off-by: Guoniu.zhou <[email protected]>
Signed-off-by: Dong Aisheng <[email protected]>
Reviewed-by: Abel Vesa <[email protected]>
Signed-off-by: Abel Vesa <[email protected]>
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Add more scu clocks used by i.MX8 platforms.
Signed-off-by: Dong Aisheng <[email protected]>
Reviewed-by: Abel Vesa <[email protected]>
Signed-off-by: Abel Vesa <[email protected]>
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enet tx clk actually is sourced from a gpr divider, not default enet
clk. Add enet grp clocks for user to use correctly.
Cc: Abel Vesa <[email protected]>
Cc: Stephen Boyd <[email protected]>
Cc: Shawn Guo <[email protected]>
Signed-off-by: Dong Aisheng <[email protected]>
Reviewed-by: Abel Vesa <[email protected]>
Signed-off-by: Abel Vesa <[email protected]>
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Add imx8qm clock valid resource checking mechanism
Signed-off-by: Dong Aisheng <[email protected]>
Reviewed-by: Abel Vesa <[email protected]>
Signed-off-by: Abel Vesa <[email protected]>
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clk-imx8qxp is a common SCU clock driver used by both QM and QXP
platforms. The clock numbers vary a bit between those two platforms.
This patch introduces a mechanism to only register the valid clocks
for one platform by checking the clk resource id table.
Signed-off-by: Dong Aisheng <[email protected]>
Reviewed-by: Abel Vesa <[email protected]>
Signed-off-by: Abel Vesa <[email protected]>
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SCU clock protocol supports a few clocks based on GPR controller
registers including mux/divider/gate.
Add a generic clock register API to support them all.
Signed-off-by: Dong Aisheng <[email protected]>
Reviewed-by: Abel Vesa <[email protected]>
Signed-off-by: Abel Vesa <[email protected]>
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Legacy scu clock binding are not maintained anymore, it has a very
limited clocks supported during initial upstreaming and obviously
unusable by products. So it's meaningless to keep it in
kernel which worse the code readability.
Remove it to keep code much cleaner.
Signed-off-by: Dong Aisheng <[email protected]>
Reviewed-by: Abel Vesa <[email protected]>
Signed-off-by: Abel Vesa <[email protected]>
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There is no audio ipg clock on i.MX8MP, so remove this from
the clock driver.
Signed-off-by: Jacky Bai <[email protected]>
Reviewed-by: Abel Vesa <[email protected]>
Signed-off-by: Abel Vesa <[email protected]>
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Define the clock outputs supported by RZ/G2L (R9A07G044) SoC
and bind it with RZ/G2L CPG core.
Based on a patch in the BSP by Binh Nguyen
<[email protected]>.
Signed-off-by: Lad Prabhakar <[email protected]>
Reviewed-by: Biju Das <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Geert Uytterhoeven <[email protected]>
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Add CPG core wrapper for RZ/G2L family.
Based on a patch in the BSP by Binh Nguyen
<[email protected]>.
Signed-off-by: Lad Prabhakar <[email protected]>
Reviewed-by: Biju Das <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Geert Uytterhoeven <[email protected]>
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This adds the Neural Network Accelerator source clocks for g12b.
Initial support for sm1 already exist in
commit 2f1efa5340ef
("clk: meson: g12a: Add support for NNA CLK source clocks")
The sm1 and g12b share the same NNA source clocks.
This patch add missing NNA clocks for A311D (g12b).
Signed-off-by: Nick Xie <[email protected]>
Acked-by: Neil Armstrong <[email protected]>
Reviewed-by: Martin Blumenstingl <[email protected]>
Signed-off-by: Jerome Brunet <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
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On 5P49V6965, when an output is enabled we enable the corresponding
FOD. When this happens for the first time, and specifically when writing
register VC5_OUT_DIV_CONTROL in vc5_clk_out_prepare(), all other outputs
are stopped for a short time and then restarted.
According to Renesas support this is intended: "The reason for that is VC6E
has synced up all output function".
This behaviour can be disabled at least on VersaClock 6E devices, of which
only the 5P49V6965 is currently implemented by this driver. This requires
writing bit 7 (bypass_sync{1..4}) in register 0x20..0x50. Those registers
are named "Unused Factory Reserved Register", and the bits are documented
as "Skip VDDO<N> verification", which does not clearly explain the relation
to FOD sync. However according to Renesas support as well as my testing
setting this bit does prevent disabling of all clock outputs when enabling
a FOD.
See "VersaClock ® 6E Family Register Descriptions and Programming Guide"
(August 30, 2018), Table 116 "Power Up VDD check", page 58:
https://www.renesas.com/us/en/document/mau/versaclock-6e-family-register-descriptions-and-programming-guide
Signed-off-by: Luca Ceresoli <[email protected]>
Reviewed-by: Adam Ford <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Fixes: 2bda748e6ad8 ("clk: vc5: Add support for IDT VersaClock 5P49V6965")
Signed-off-by: Stephen Boyd <[email protected]>
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The patch enables spread spectrum clocking (SSC) for MPU and LCD PLLs.
As reported by the TI spruh73x/spruhl7x RM, SSC is only supported for
the DISP/LCD and MPU PLLs on am33xx/am43xx. SSC is not supported for
DDR, PER, and CORE PLLs.
Calculating the required values and setting the registers accordingly
was taken from the set_mpu_spreadspectrum routine contained in the
arch/arm/mach-omap2/am33xx/clock_am33xx.c file of the u-boot project.
In locked condition, DPLL output clock = CLKINP *[M/N]. In case of
SSC enabled, the reference manual explains that there is a restriction
of range of M values. Since the omap2_dpll_round_rate routine attempts
to select the minimum possible N, the value of M obtained is not
guaranteed to be within the range required. With the new "ti,min-div"
parameter it is possible to increase N and consequently M to satisfy the
constraint imposed by SSC.
Signed-off-by: Dario Binacchi <[email protected]>
Reviewed-by: Tero Kristo <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Stephen Boyd <[email protected]>
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Replace _omap3_noncore_dpll_program with omap3_noncore_dpll_program.
Signed-off-by: Dario Binacchi <[email protected]>
Reviewed-by: Stephen Boyd <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Stephen Boyd <[email protected]>
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During my big cleanup I managed to assign an AO clock to its
non-AO binding. Fix this.
Reported-by: Bartosz Dudziak <[email protected]>
Signed-off-by: Konrad Dybcio <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Fixes: a0384ecfe2aa ("clk: qcom: smd-rpm: De-duplicate identical entries")
Signed-off-by: Stephen Boyd <[email protected]>
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The last user of clkdev_alloc() and clkdev_hw_alloc() was
removed last year, so everything now calls clkdev_create()
and clkdev_hw_create() instead.
Removing the unused functions lets the compiler optimize
the remaining ones slightly better.
Fixes: e5006671acc7 ("clk: versatile: Drop the legacy IM-PD1 clock code")
Reviewed-by: Stephen Boyd <[email protected]>
Signed-off-by: Arnd Bergmann <[email protected]>
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This option is now synonymous with CONFIG_HAVE_CLK, so use
the latter globally. Any out-of-tree platform ports that
still use a private clk_get()/clk_put() implementation should
move to CONFIG_COMMON_CLK.
Signed-off-by: Arnd Bergmann <[email protected]>
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kbuild robot reports that s390 fails to build this driver with
COMPILE_TEST. Let's depend on HAS_IOMEM so that s390 doesn't try to
build it.
Cc: Lee Jones <[email protected]>
Acked-by: Linus Walleij <[email protected]>
Reported-by: kernel test robot <[email protected]>
Fixes: 419b3ab6987f ("clk: versatile: remove dependency on ARCH_*")
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Stephen Boyd <[email protected]>
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After calling clk_prepare_enable(), clk_disable_unprepare() needs
be called when prepare_timing_change() failed.
Reported-by: Hulk Robot <[email protected]>
Signed-off-by: Yang Yingliang <[email protected]>
Signed-off-by: Thierry Reding <[email protected]>
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Signed-off-by: Bjorn Andersson <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Acked-by: Rob Herring <[email protected]>
Signed-off-by: Stephen Boyd <[email protected]>
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The display clock controller in SC8180x is reused from SM8150, so add
the necessary compatible and wire up the driver to enable this.
Signed-off-by: Bjorn Andersson <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Acked-by: Rob Herring <[email protected]>
Signed-off-by: Stephen Boyd <[email protected]>
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It makes negative sense to keep repeating the same definitions
over and over and over and over again, just with changed names..
De-duplicate to make for a drastically smaller file size. This makes the
object file size 55% smaller according to bloat-o-meter:
Total: Before=70713, After=31353, chg -55.66%
Signed-off-by: Konrad Dybcio <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Stephen Boyd <[email protected]>
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Switch to parent_data and with that fix the longstanding issue where
if there wasn't a clock precisely named "xo_board", rpmcc would not play
along well. This started to show lately when "xo_board" was being changed to
"xo-board" so as to align with DTS naming spec.
Signed-off-by: Konrad Dybcio <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Stephen Boyd <[email protected]>
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Add Global Clock Controller (GCC) support for MDM9607 SoC.
Signed-off-by: Konrad Dybcio <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
[[email protected]: Drop clk.h include]
Signed-off-by: Stephen Boyd <[email protected]>
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Fix the following make W=1 warning:
drivers/clk/analogbits/wrpll-cln28hpc.c:227: warning: expecting prototype for wrpll_configure(). Prototype was for wrpll_configure_for_rate() instead
Signed-off-by: Yang Yingliang <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Stephen Boyd <[email protected]>
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Fix function name in sifive-prci.c kernel-doc comment
to remove a warning.
drivers/clk/sifive/sifive-prci.c:573: warning: expecting prototype for
sifive_prci_init(). Prototype was for sifive_prci_probe() instead
Reported-by: Abaci Robot <[email protected]>
Signed-off-by: Yang Li <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Reviewed-by: Palmer Dabbelt <[email protected]>
Acked-by: Palmer Dabbelt <[email protected]>
Signed-off-by: Stephen Boyd <[email protected]>
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