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In the next patch we're going to change these tables to reference the
PLL structures directly. Let's move them here so the diff is easier to
read. No functional change in this patch.
Signed-off-by: Stephen Boyd <[email protected]>
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Use two new helpers instead of pm_runtime_enable() and pm_clk_create(),
removing the need for calling pm_runtime_disable and pm_clk_destroy().
Signed-off-by: Dmitry Baryshkov <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Stephen Boyd <[email protected]>
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Add missing M7 core clock entry to the iMX8MN clock driver.
Signed-off-by: Marek Vasut <[email protected]>
Reviewed-by: Abel Vesa <[email protected]>
Reviewed-by: Fabio Estevam <[email protected]>
Cc: Abel Vesa <[email protected]>
Cc: Fabio Estevam <[email protected]>
Cc: NXP Linux Team <[email protected]>
Cc: Peng Fan <[email protected]>
Cc: Shawn Guo <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Abel Vesa <[email protected]>
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On the i.MX8M*, the TF-A exposes a SiP (Silicon Provider) service
for DDR frequency scaling. The imx8m-ddrc-devfreq driver calls the
SiP and then does clk_set_parent on the DDR muxes to synchronize
the clock tree.
Since 936c383673b9 ("clk: imx: fix composite peripheral flags"),
these TF-A managed muxes have SET_PARENT_GATE set, which results
in imx8m-ddrc-devfreq's clk_set_parent after SiP failing with -EBUSY:
echo 25000000 > userspace/set_freq
imx8m-ddrc-devfreq 3d400000.memory-controller: failed to set
dram_apb parent: -16
Fix this by adding a new i.MX composite flag for firmware managed
clocks, which clears SET_PARENT_GATE.
This is safe to do, because updating the Linux clock tree to reflect
reality will always be glitch-free.
Fixes: 936c383673b9 ("clk: imx: fix composite peripheral flags")
Signed-off-by: Ahmad Fatoum <[email protected]>
Reviewed-by: Abel Vesa <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Abel Vesa <[email protected]>
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.determine_rate is meant to replace .round_rate in CCF in the future.
Switch over to .determine_rate now that clk_divider_ops has gained
support for that.
Cc: Guenter Roeck <[email protected]>
Cc: Abel Vesa <[email protected]>
Cc: Shawn Guo <[email protected]>
Cc: Sascha Hauer <[email protected]>
Cc: Pengutronix Kernel Team <[email protected]>
Cc: Fabio Estevam <[email protected]>
Cc: NXP Linux Team <[email protected]>
Signed-off-by: Martin Blumenstingl <[email protected]>
Reviewed-by: Abel Vesa <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Abel Vesa <[email protected]>
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The mux in the clkout path needs the current selected parent to
be enabled for the switch to work. Use the correct mux type
to have the clk framework take care of this requirement.
Fixes: af4df655040 ("clk: imx8mn: add clkout1/2 support")
Signed-off-by: Lucas Stach <[email protected]>
Reviewed-by: Abel Vesa <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Abel Vesa <[email protected]>
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The mux in the clkout path needs the current selected parent to
be enabled for the switch to work. Use the correct mux type
to have the clk framework take care of this requirement.
Fixes: c1ae5c6f789a ("clk: imx8mm: add clkout1/2 support")
Signed-off-by: Lucas Stach <[email protected]>
Reviewed-by: Abel Vesa <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Abel Vesa <[email protected]>
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git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux
Pull clk driver fixes from Stephen Boyd:
- Make the regulator state match the GDSC power domain state at boot on
Qualcomm SoCs so that the regulator isn't turned off inadvertently.
- Fix earlycon on i.MX6Q SoCs
* tag 'clk-fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux:
clk: qcom: gdsc: Ensure regulator init state matches GDSC state
clk: imx6q: fix uart earlycon unwork
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When configuring a kernel including support for Renesas ARM/ARM64 Socs,
but excluding support for the RZ/N1D SoC, the user is always asked about
the RZ/N1D clock driver. As this driver is already auto-selected when
building a kernel including support for the RZ/N1D SoC, there is no need
to make the CLK_R9A06G032 symbol visible, unless compile-testing.
Align the symbol description with the other symbols.
Signed-off-by: Geert Uytterhoeven <[email protected]>
Reviewed-by: Niklas Söderlund <[email protected]>
Link: https://lore.kernel.org/r/4f3d30c730c30546f702715ffc648922a8156703.1628672649.git.geert+renesas@glider.be
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It appears that some code lines raise the question why they are needed
and how they are participated in the calculus of the resulting values.
Document this in a form of the top comment in the module file.
Reported-by: Liu Ying <[email protected]>
Signed-off-by: Andy Shevchenko <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
[[email protected]: Remove "die" as it isn't relevant]
Signed-off-by: Stephen Boyd <[email protected]>
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The newly introduced POWER_OF_TWO_PS flag, when set, makes the flow
to skip the assumption that the caller will use an additional 2^scale
prescaler to get the desired clock rate.
Reported-by: Liu Ying <[email protected]>
Signed-off-by: Andy Shevchenko <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Stephen Boyd <[email protected]>
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The providers are all located in drivers/clk/ and hence no need
to export the clock operations to wider audience. Hide them by
moving to drivers/clk/clk-fractional-divider.h.
Signed-off-by: Andy Shevchenko <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Stephen Boyd <[email protected]>
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At least one user currently duplicates some functions that are provided
by fractional divider module. Let's export approximation algorithm and
replace the open-coded variant.
As a bonus the exported function will get better documentation in place.
Signed-off-by: Andy Shevchenko <[email protected]>
Tested-by: Heiko Stuebner <[email protected]>
Acked-by: Heiko Stuebner <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
[[email protected]: Add header guard because why not]
Signed-off-by: Stephen Boyd <[email protected]>
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We're moving pistachio to generic MIPS kernel. The clk driver
should be avilable to the generic MIPS kernel.
Signed-off-by: Jiaxun Yang <[email protected]>
Acked-by: Stephen Boyd <[email protected]>
Signed-off-by: Thomas Bogendoerfer <[email protected]>
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FUSE driver now takes care of keeping the clock enabled when necessary.
Remove the CLK_IS_CRITICAL flag from the clock.
Signed-off-by: Dmitry Osipenko <[email protected]>
Signed-off-by: Thierry Reding <[email protected]>
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There was an "unknown" firmware variant turning up in the wild
causing problems in the clock driver. Add this missing variant
and clarify that varian 11 and 15 are Samsung variants, as this
is now very well known from released products.
Signed-off-by: Linus Walleij <[email protected]>
Acked-by: Stephen Boyd <[email protected]>
Signed-off-by: Lee Jones <[email protected]>
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MSM8939 has 3 a53pll clocks with different frequency table for Cluster0,
Cluster1 and CCI. It adds function qcom_a53pll_get_freq_tbl() to create
pll_freq_tbl from OPP, so that those a53pll frequencies can be defined
in DT with operating-points-v2 bindings rather than being coded in the
driver. In this case, one compatible rather than three would be needed
for these 3 a53pll clocks.
Signed-off-by: Shawn Guo <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Stephen Boyd <[email protected]>
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Different from MSM8916 which has only one a53pll/mux clock, MSM8939 gets
three for Cluster0 (little cores), Cluster1 (big cores) and CCI (Cache
Coherent Interconnect). That said, a53pll/mux clock needs to be named
uniquely. Append @unit-address of device node to the clock name, so
that a53pll/mux will be named like below on MSM8939.
a53pll@b016000
a53pll@b116000
a53pll@b1d0000
a53mux@b1d1000
a53mux@b011000
a53mux@b111000
Signed-off-by: Shawn Guo <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Stephen Boyd <[email protected]>
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The clock source for MSM8916 cpu cores is like below.
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a53pll --------| \ a53mux +------+
| |------------| cpus |
gpll0_vote --------| / +------+
|/
So a53mux rather than a53pll is actually the parent clock of cpu cores.
It makes more sense to flag a53mux as critical instead, so that when
either a53pll or gpll0_vote is used by cpu cores, the clock will be kept
enabled while the other can be disabled.
Signed-off-by: Shawn Guo <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Stephen Boyd <[email protected]>
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The GPU clock controller found in SC8180x is a variant of the same block
found in SM8150, but with one additional clock frequency for the
gmu_clk_src clock.
Signed-off-by: Bjorn Andersson <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Acked-by: Rob Herring <[email protected]>
Signed-off-by: Stephen Boyd <[email protected]>
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Add support for RPM-managed clocks on the MDM9607 platform.
Signed-off-by: Konrad Dybcio <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Stephen Boyd <[email protected]>
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Add definitions for RPM clocks used on MSM8953 platform.
Signed-off-by: Vladimir Lypak <[email protected]>
Signed-off-by: Adam Skladowski <[email protected]>
Reviewed-by: Konrad Dybcio <[email protected]>
Signed-off-by: Sireesh Kodali <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Stephen Boyd <[email protected]>
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Add rpm smd clocks, PMIC and bus clocks which are required on
SM4250/6115 for clients to vote on.
Signed-off-by: Iskren Chernev <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
[[email protected]: Drop duplicate define, merge with sm6125 support]
Signed-off-by: Stephen Boyd <[email protected]>
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Add rpm smd clocks, PMIC and bus clocks which are required on SM6125
for clients to vote on.
Signed-off-by: Martin Botka <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Stephen Boyd <[email protected]>
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As GDSCs are registered and found to be already enabled gdsc_init()
ensures that 1) the kernel state matches the hardware state, and 2)
votable GDSCs are properly enabled from this master as well.
But as the (optional) supply regulator is enabled deep into
gdsc_toggle_logic(), which is only executed for votable GDSCs, the
kernel's state of the regulator might not match the hardware. The
regulator might be automatically turned off if no other users are
present or the next call to gdsc_disable() would cause an unbalanced
regulator_disable().
Given that the votable case deals with an already enabled GDSC, most of
gdsc_enable() and gdsc_toggle_logic() can be skipped. Reduce it to just
clearing the SW_COLLAPSE_MASK and enabling hardware control to simply
call regulator_enable() in both cases.
The enablement of hardware control seems to be an independent property
from the GDSC being enabled, so this is moved outside that conditional
segment.
Lastly, as the propagation of ALWAYS_ON to GENPD_FLAG_ALWAYS_ON needs to
happen regardless of the initial state this is grouped together with the
other sc->pd updates at the end of the function.
Cc: [email protected]
Fixes: 37416e554961 ("clk: qcom: gdsc: Handle GDSC regulator supplies")
Signed-off-by: Bjorn Andersson <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
[[email protected]: Rephrase commit text]
Signed-off-by: Stephen Boyd <[email protected]>
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The earlycon depends on the bootloader setup UART clocks being retained.
There're actually two uart clocks (ipg, per) on MX6QDL,
but the 'Fixes' commit change to register only one which means
another clock may be disabled during booting phase
and result in the earlycon unwork.
Cc: [email protected] # v5.10+
Fixes: 379c9a24cc23 ("clk: imx: Fix reparenting of UARTs not associated with stdout")
Signed-off-by: Dong Aisheng <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Reviewed-by: Abel Vesa <[email protected]>
Signed-off-by: Stephen Boyd <[email protected]>
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.determine_rate is meant to replace .round_rate in CCF in the future.
Switch over to .determine_rate now that clk_divider_ops has gained
support for that.
Cc: Maxime Coquelin <[email protected]>
Cc: Alexandre Torgue <[email protected]>
Cc: [email protected]
Signed-off-by: Martin Blumenstingl <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Stephen Boyd <[email protected]>
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.determine_rate is meant to replace .round_rate in CCF in the future.
Switch over to .determine_rate now that clk_divider_ops has gained
support for that.
Cc: Maxime Coquelin <[email protected]>
Cc: Alexandre Torgue <[email protected]>
Cc: [email protected]
Signed-off-by: Martin Blumenstingl <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Stephen Boyd <[email protected]>
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.determine_rate is meant to replace .round_rate in CCF in the future.
Switch over to .determine_rate now that clk_divider_ops has gained
support for that.
Cc: Maxime Coquelin <[email protected]>
Cc: Alexandre Torgue <[email protected]>
Cc: [email protected]
Signed-off-by: Martin Blumenstingl <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Stephen Boyd <[email protected]>
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.determine_rate is meant to replace .round_rate in CCF in the future.
Switch over to .determine_rate now that clk_divider_ops has gained
support for that.
Cc: Marek Szyprowski <[email protected]>
Cc: Nicolas Saenz Julienne <[email protected]>
Cc: Florian Fainelli <[email protected]>
Cc: Ray Jui <[email protected]>
Cc: Scott Branden <[email protected]>
Cc: [email protected]
Cc: [email protected]
Signed-off-by: Martin Blumenstingl <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Tested-by: Marek Szyprowski <[email protected]>
Signed-off-by: Stephen Boyd <[email protected]>
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.determine_rate is meant to replace .round_rate. The former comes with a
benefit which is especially relevant on 32-bit systems: since
.determine_rate uses an "unsigned long" (compared to a "signed long"
which is used by .round_rate) the maximum value on 32-bit systems
increases from 2^31 (or approx. 2.14GHz) to 2^32 (or approx. 4.29GHz).
Implement .determine_rate in addition to .round_rate so drivers that are
using clk_divider_{ro_,}ops can benefit from this by default. Keep the
.round_rate callback for now since some drivers rely on
clk_divider_ops.round_rate being implemented.
Signed-off-by: Martin Blumenstingl <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Stephen Boyd <[email protected]>
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Add the missing SPDX license header to drivers/clk/clk-palmas.c.
Signed-off-by: Jason Wang <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
[[email protected]: Also remove boilerplate from comment]
Signed-off-by: Stephen Boyd <[email protected]>
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git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux
Pull clk fixes from Stephen Boyd:
"A collection of clk driver fixes and one core clk API fix:
- Fix stm32 clk data to avoid a crash early on
- Fix a randconfig build error in HiSilicon clk driver
- Avoid an oops at boot on Qualcomm MSM8936 SoCs due to
an improper consolidation of structs
- Fix imbalanced disabling of the unused MMC clock on
Tegra210 Jetson Nano
- Plug a memory leak in devm_clk_bulk_get_all() unwind
path"
* tag 'clk-fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux:
clk: fix leak on devm_clk_bulk_get_all() unwind
clk: tegra: Implement disable_unused() of tegra_clk_sdmmc_mux_ops
clk: qcom: smd-rpm: Fix MSM8936 RPM_SMD_PCNOC_A_CLK
clk: hisilicon: hi3559a: select RESET_HISI
clk: stm32f4: fix post divisor setup for I2S/SAI PLLs
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clk_bulk_get_all() allocates an array of struct clk_bulk data for us
(unlike clk_bulk_get()), so we need to free it. Let's use the
clk_bulk_put_all() helper.
kmemleak complains, on an RK3399 Gru/Kevin system:
unreferenced object 0xffffff80045def00 (size 128):
comm "swapper/0", pid 1, jiffies 4294667682 (age 86.394s)
hex dump (first 32 bytes):
44 32 60 fe fe ff ff ff 00 00 00 00 00 00 00 00 D2`.............
48 32 60 fe fe ff ff ff 00 00 00 00 00 00 00 00 H2`.............
backtrace:
[<00000000742860d6>] __kmalloc+0x22c/0x39c
[<00000000b0493f2c>] clk_bulk_get_all+0x64/0x188
[<00000000325f5900>] devm_clk_bulk_get_all+0x58/0xa8
[<00000000175b9bc5>] dwc3_probe+0x8ac/0xb5c
[<000000009169e2f9>] platform_drv_probe+0x9c/0xbc
[<000000005c51e2ee>] really_probe+0x13c/0x378
[<00000000c47b1f24>] driver_probe_device+0x84/0xc0
[<00000000f870fcfb>] __device_attach_driver+0x94/0xb0
[<000000004d1b92ae>] bus_for_each_drv+0x8c/0xd8
[<00000000481d60c3>] __device_attach+0xc4/0x150
[<00000000a163bd36>] device_initial_probe+0x1c/0x28
[<00000000accb6bad>] bus_probe_device+0x3c/0x9c
[<000000001a199f89>] device_add+0x218/0x3cc
[<000000001bd84952>] of_device_add+0x40/0x50
[<000000009c658c29>] of_platform_device_create_pdata+0xac/0x100
[<0000000021c69ba4>] of_platform_bus_create+0x190/0x224
Fixes: f08c2e2865f6 ("clk: add managed version of clk_bulk_get_all")
Cc: Dong Aisheng <[email protected]>
Cc: [email protected]
Signed-off-by: Brian Norris <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Stephen Boyd <[email protected]>
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Currently, no driver support for DDR memory controller (DMC) is present,
as a result, no driver is explicitly consuming the ddrphy clock. This means
that VPLL1 (parent of ddr clock) will be shutdown if we enable
and then disable any child clock of VPLL1 (e.g. SCLK_I2S0_8CH_TX).
If VPLL1 is disabled, the whole system will freeze, because the DDR
controller will lose its clock. So, it's necessary to prevent VPLL1 from
shutting down, by marking the ddrphy4x CLK_IS_CRITICAL.
This bug was discovered when I was porting rockchip_i2s_tdm driver to
mainline kernel from Rockchip 4.4 kernel. I guess that other Rockchip
SoCs without DMC driver may need the same patch. If this applies to
other devices, please let us know.
Signed-off-by: Yunhao Tian <[email protected]>
Link: https://lore.kernel.org/r/BYAPR20MB24886765F888A9705CBEB70789E39@BYAPR20MB2488.namprd20.prod.outlook.com
[adapted subject, changed to add the clock to the critical list]
Signed-off-by: Heiko Stuebner <[email protected]>
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The rk3036/rk3328 pll types were converted to checking the lock status
via the internal register in january 2020, so don't need the grf
reference since then.
But it was forgotten to remove grf check when deciding between the
pll rate ops (read-only vs. read-write), so a clock driver without
the needed grf reference might've been put into the read-only mode
just because the grf reference was missing.
This affected the rk356x that needs to reclock certain plls at boot.
Fix this by removing the check for the grf for selecting the utilized
operations.
Suggested-by: Heiko Stuebner <[email protected]>
Fixes: 7f6ffbb885d1 ("clk: rockchip: convert rk3036 pll type to use internal lock status")
Signed-off-by: Peter Geis <[email protected]>
[adjusted the commit message, adjusted the fixes tag]
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Heiko Stuebner <[email protected]>
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Implement disable_unused() callback of tegra_clk_sdmmc_mux_ops to fix
imbalanced disabling of the unused MMC clock on Tegra210 Jetson Nano.
Fixes: c592c8a28f58 ("clk: tegra: Fix refcounting of gate clocks")
Reported-by: Jon Hunter <[email protected]> # T210 Nano
Tested-by: Jon Hunter <[email protected]> # T210 Nano
Acked-by: Jon Hunter <[email protected]>
Signed-off-by: Dmitry Osipenko <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Stephen Boyd <[email protected]>
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The LPT stands for Lynxpoint PCH. However the driver is used on a few
Intel Atom SoCs. Rename it to reflect this in a way how another clock
driver, i.e. clk-pmc-atom, is called.
Signed-off-by: Andy Shevchenko <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Acked-by: Rafael J. Wysocki <[email protected]>
Signed-off-by: Stephen Boyd <[email protected]>
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When the body of a case statement is empty, it is well understood that
it is intentional and explicit fallthrough statements are not required.
Drop them.
Signed-off-by: Liam Beguin <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Stephen Boyd <[email protected]>
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I found that COMMON_CLK_MT8167* do not depend on COMMON_CLK_MT8167,
so it is possible to config:
CONFIG_COMMON_CLK_MT8167=n
CONFIG_COMMON_CLK_MT8167_*=y
Although it does not cause build breaks with such configuration,
I think it is clearer to make COMMON_CLK_MT8167* depend on
COMMON_CLK_MT8167.
Signed-off-by: Miles Chen <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Stephen Boyd <[email protected]>
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The clock controller has two additional clock source pairs, in order to
support more than a single DisplayPort PHY. List these, so it's possible
to describe them all.
Also drop the unnecessary freq_tbl for the link clock sources, to allow
these parents to be used.
Signed-off-by: Bjorn Andersson <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Reviewed-by: Dmitry Baryshkov <[email protected]>
Signed-off-by: Stephen Boyd <[email protected]>
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Commit a0384ecfe2aa ("clk: qcom: smd-rpm: De-duplicate identical
entries") introduces the following regression on MSM8936/MSM8939, as
RPM_SMD_PCNOC_A_CLK gets pointed to pcnoc_clk by mistake. Fix it by
correcting the clock to pcnoc_a_clk.
[ 1.307363] Unable to handle kernel NULL pointer dereference at virtual address 0000000000000000
[ 1.313593] Mem abort info:
[ 1.322512] ESR = 0x96000004
[ 1.325132] EC = 0x25: DABT (current EL), IL = 32 bits
[ 1.338872] SET = 0, FnV = 0
[ 1.355483] EA = 0, S1PTW = 0
[ 1.368702] FSC = 0x04: level 0 translation fault
[ 1.383294] Data abort info:
[ 1.398292] ISV = 0, ISS = 0x00000004
[ 1.398297] CM = 0, WnR = 0
[ 1.398301] [0000000000000000] user address but active_mm is swapper
[ 1.404193] Internal error: Oops: 96000004 [#1] PREEMPT SMP
[ 1.420596] Modules linked in:
[ 1.420604] CPU: 0 PID: 5 Comm: kworker/0:0 Not tainted 5.14.0-rc3+ #198
[ 1.441010] pc : __clk_register+0x48/0x780
[ 1.446045] lr : __clk_register+0x3c/0x780
[ 1.449953] sp : ffff800010063440
[ 1.454031] x29: ffff800010063440 x28: 0000000000000004 x27: 0000000000000066
[ 1.457423] x26: 0000000000000001 x25: 000000007fffffff x24: ffff800010f9f388
[ 1.464540] x23: ffff00007fc12a90 x22: ffff0000034b2010 x21: 0000000000000000
[ 1.471658] x20: ffff800010f9fff8 x19: ffff00000152a700 x18: 0000000000000001
[ 1.478778] x17: ffff00007fbd40c8 x16: 0000000000000460 x15: 0000000000000465
[ 1.485895] x14: ffffffffffffffff x13: 746e756f635f7265 x12: 696669746f6e5f6b
[ 1.493013] x11: 0000000000000006 x10: 0000000000000000 x9 : 0000000000000000
[ 1.500131] x8 : ffff00000152a800 x7 : 0000000000000000 x6 : 000000000000003f
[ 1.507249] x5 : 0000000000000040 x4 : 0000000000000000 x3 : 0000000000000004
[ 1.514367] x2 : 0000000000000000 x1 : 0000000000000cc0 x0 : ffff00000152a700
[ 1.521486] Call trace:
[ 1.528598] __clk_register+0x48/0x780
[ 1.530855] clk_hw_register+0x20/0x60
[ 1.534674] devm_clk_hw_register+0x50/0xa8
[ 1.538408] rpm_smd_clk_probe+0x1a4/0x260
[ 1.542488] platform_probe+0x68/0xd8
[ 1.546653] really_probe+0x140/0x2f8
[ 1.550386] __driver_probe_device+0x78/0xe0
[ 1.554033] driver_probe_device+0x80/0x110
[ 1.558373] __device_attach_driver+0x90/0xe0
[ 1.562280] bus_for_each_drv+0x78/0xc8
[ 1.566793] __device_attach+0xf0/0x150
[ 1.570438] device_initial_probe+0x14/0x20
[ 1.574259] bus_probe_device+0x9c/0xa8
[ 1.578425] device_add+0x378/0x870
[ 1.582243] of_device_add+0x44/0x60
[ 1.585716] of_platform_device_create_pdata+0xc0/0x110
[ 1.589538] of_platform_bus_create+0x17c/0x388
[ 1.594485] of_platform_populate+0x50/0xf0
[ 1.598998] qcom_smd_rpm_probe+0xd4/0x128
[ 1.603164] rpmsg_dev_probe+0xbc/0x1a8
[ 1.607330] really_probe+0x140/0x2f8
[ 1.611063] __driver_probe_device+0x78/0xe0
[ 1.614883] driver_probe_device+0x80/0x110
[ 1.619224] __device_attach_driver+0x90/0xe0
[ 1.623131] bus_for_each_drv+0x78/0xc8
[ 1.627643] __device_attach+0xf0/0x150
[ 1.631289] device_initial_probe+0x14/0x20
[ 1.635109] bus_probe_device+0x9c/0xa8
[ 1.639275] device_add+0x378/0x870
[ 1.643095] device_register+0x20/0x30
[ 1.646567] rpmsg_register_device+0x54/0x90
[ 1.650387] qcom_channel_state_worker+0x168/0x288
[ 1.654814] process_one_work+0x1a0/0x328
[ 1.659415] worker_thread+0x4c/0x420
[ 1.663494] kthread+0x150/0x160
[ 1.667138] ret_from_fork+0x10/0x18
[ 1.670442] Code: 97f56b92 b40034a0 aa0003f3 52819801 (f94002a0)
[ 1.674004] ---[ end trace 412fa6f47384cdfe ]---
Fixes: a0384ecfe2aa ("clk: qcom: smd-rpm: De-duplicate identical entries")
Signed-off-by: Shawn Guo <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Stephen Boyd <[email protected]>
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Add MT8192 vencsys clock provider
Signed-off-by: Weiyi Lu <[email protected]>
Signed-off-by: Chun-Jie Chen <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Reviewed-by: Ikjoon Jang <[email protected]>
Signed-off-by: Stephen Boyd <[email protected]>
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Add MT8192 vdecsys and vdecsys soc clock providers
Signed-off-by: Weiyi Lu <[email protected]>
Signed-off-by: Chun-Jie Chen <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Reviewed-by: Ikjoon Jang <[email protected]>
Signed-off-by: Stephen Boyd <[email protected]>
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Add MT8192 scp adsp clock provider
Signed-off-by: Weiyi Lu <[email protected]>
Signed-off-by: Chun-Jie Chen <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Reviewed-by: Ikjoon Jang <[email protected]>
Signed-off-by: Stephen Boyd <[email protected]>
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Add MT8192 msdc and msdc top clock providers
Signed-off-by: Weiyi Lu <[email protected]>
Signed-off-by: Chun-Jie Chen <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Reviewed-by: Ikjoon Jang <[email protected]>
Signed-off-by: Stephen Boyd <[email protected]>
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Add MT8192 mmsys clock provider
Signed-off-by: Weiyi Lu <[email protected]>
Signed-off-by: Chun-Jie Chen <[email protected]>
Reviewed-by: Matthias Brugger <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Stephen Boyd <[email protected]>
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Add MT8192 mfgcfg clock provider
Signed-off-by: Weiyi Lu <[email protected]>
Signed-off-by: Chun-Jie Chen <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Reviewed-by: Ikjoon Jang <[email protected]>
Signed-off-by: Stephen Boyd <[email protected]>
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Add MT8192 mdpsys clock provider
Signed-off-by: Weiyi Lu <[email protected]>
Signed-off-by: Chun-Jie Chen <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Reviewed-by: Ikjoon Jang <[email protected]>
Signed-off-by: Stephen Boyd <[email protected]>
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Add MT8192 ipesys clock provider
Signed-off-by: Weiyi Lu <[email protected]>
Signed-off-by: Chun-Jie Chen <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Reviewed-by: Ikjoon Jang <[email protected]>
Signed-off-by: Stephen Boyd <[email protected]>
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