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2021-09-20clk: rockchip: rk3399: expose PCLK_COREDBG_{B,L}Brian Norris1-2/+2
We have DT IDs for PCLK_COREDBG_L and PCLK_COREDBG_B, but we don't actually expose them. Note that this requires the previous patch (making "armclkl" and "armclkb" into "critical" clocks) to prevent these clocks from taking down the CPU. Reviewed-by: Chen-Yu Tsai <[email protected]> Signed-off-by: Brian Norris <[email protected]> Reviewed-by: Douglas Anderson <[email protected]> Link: https://lore.kernel.org/r/20210908111337.v2.2.If29cd838efbcee4450a62b8d84a99b23c86e0a3f@changeid Signed-off-by: Heiko Stuebner <[email protected]>
2021-09-20clk: rockchip: rk3399: make CPU clocks criticalBrian Norris1-4/+7
The CPU clocks don't currently have any owner (e.g., cpufreq-dt doesn't enable() them -- and even if it did, it's not early enough compared to other consumers -- nor does arch/arm64/kernel/smp.c), and instead are simply assumed to be "on" all the time. They are also parents of a few other clocks which haven't been previously exposed for other devices to consume. If we want to expose those clocks, then the common clock framework may eventually choose to disable their parents (including the CPU PLLs) -- which is no fun for anyone. Thus, mark the CPU clocks as critical, to prevent them from being disabled implicitly. Signed-off-by: Brian Norris <[email protected]> Reviewed-by: Douglas Anderson <[email protected]> Reviewed-by: Chen-Yu Tsai <[email protected]> Reviewed-by: Douglas Anderson <[email protected]> Link: https://lore.kernel.org/r/20210908111337.v2.1.I006bb36063555079b1a88f01d20e38d7e4705ae0@changeid Signed-off-by: Heiko Stuebner <[email protected]>
2021-09-17clk: imx: Rework all clk_hw_register_gate wrappersAbel Vesa1-41/+23
Instead of having multiple inline functions that were calling clk_hw_register_gate, implement a generic low-level __imx_clk_hw_gate and implement the rest as macros that pass on as arguments whatever is needed in each case. Signed-off-by: Abel Vesa <[email protected]> Link: https://lore.kernel.org/r/[email protected] Reviewed-by: Stephen Boyd <[email protected]>
2021-09-17clk: imx: Make mux/mux2 clk based helpers use clk_hw based onesAbel Vesa1-20/+6
Implement the clk based helpers as macros rather than as inline functions. Once all the provider drivers have switch to clk_hw, all the clk based macros will go away. Signed-off-by: Abel Vesa <[email protected]> Link: https://lore.kernel.org/r/[email protected] Reviewed-by: Stephen Boyd <[email protected]>
2021-09-17clk: imx: Remove unused helpersAbel Vesa1-103/+0
Remove all the helpers that are not referenced anywhere anymore. Most of them are not clk_hw based. The rest are passing the device as an argument and were intented for BLK_CTL driver usage, but that is not the case anymore since the BLK_CTL is (or will be) implemented outside of CCF. - imx_clk_divider2 - imx_clk_gate2_shared2 - imx_clk_gate3 - imx_clk_gate4 - imx_clk_frac_pll - imx_clk_sscg_pll - imx_clk_pll14xx - imx_clk_pll14xx - imx_clk_divider2_flags - imx_dev_clk_hw_gate - imx_dev_clk_hw_gate_shared - imx_clk_gate3_flags - imx_clk_gate4_flags - imx_dev_clk_hw_mux - imx_clk_mux2 - imx_dev_clk_hw_mux_flags - imx8m_clk_composite_flags - __imx8m_clk_composite - imx8m_clk_composite - imx8m_clk_composite_critical Signed-off-by: Abel Vesa <[email protected]> Link: https://lore.kernel.org/r/[email protected] Reviewed-by: Stephen Boyd <[email protected]>
2021-09-14clk: mediatek: Export clk_ops structures to modulesStephen Boyd1-0/+2
modpost complains once these drivers become modules. ERROR: modpost: "mtk_mux_gate_clr_set_upd_ops" [drivers/clk/mediatek/clk-mt6779.ko] undefined! Let's just export them. Cc: Hanks Chen <[email protected]> Cc: Wendell Lin <[email protected]> Cc: Lee Jones <[email protected]> Cc: Miles Chen <[email protected]> Fixes: 32b028fb1d09 ("clk: mediatek: support COMMON_CLK_MEDIATEK module build") Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Stephen Boyd <[email protected]>
2021-09-14clk: mvebu: ap-cpu-clk: Fix a memory leak in error handling pathsChristophe JAILLET1-3/+11
If we exit the for_each_of_cpu_node loop early, the reference on the current node must be decremented, otherwise there is a leak. Fixes: f756e362d938 ("clk: mvebu: add CPU clock driver for Armada 7K/8K") Signed-off-by: Christophe JAILLET <[email protected]> Link: https://lore.kernel.org/r/545df946044fc1fc05a4217cdf0054be7a79e49e.1619161112.git.christophe.jaillet@wanadoo.fr Reviewed-by: Dan Carpenter <[email protected]> Signed-off-by: Stephen Boyd <[email protected]>
2021-09-14clk: mediatek: support COMMON_CLK_MT6779 module buildMiles Chen10-17/+35
To support COMMON_CLK_MT6779* module build, add MODULE_LICENSE and export necessary symbols. Cc: Stephen Boyd <[email protected]> Cc: Hanks Chen <[email protected]> Cc: Wendell Lin <[email protected]> Cc: Lee Jones <[email protected]> Signed-off-by: Miles Chen <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Stephen Boyd <[email protected]>
2021-09-14clk: mediatek: support COMMON_CLK_MEDIATEK module buildMiles Chen8-1/+33
To support COMMON_CLK_MEDIATEK module build, add MODULE_LICENSE and export necessary symbols. Cc: Stephen Boyd <[email protected]> Cc: Hanks Chen <[email protected]> Cc: Wendell Lin <[email protected]> Cc: Lee Jones <[email protected]> Signed-off-by: Miles Chen <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Stephen Boyd <[email protected]>
2021-09-14clk: composite: export clk_register_compositeMiles Chen1-0/+1
To support module build of mediatek clk drivers, it is necessary to export clk_register_composite. Cc: Stephen Boyd <[email protected]> Cc: Hanks Chen <[email protected]> Cc: Wendell Lin <[email protected]> Cc: Lee Jones <[email protected]> Signed-off-by: Miles Chen <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Stephen Boyd <[email protected]>
2021-09-14clk: versatile: clk-icst: Support 'reg' in addition to 'vco-offset' for ↵Rob Herring1-1/+2
register address The ICST binding now also supports 'reg' in addition to 'vco-offset' for the VCO register address. Add support to the driver to get the VCO address from 'reg'. Cc: Linus Walleij <[email protected]> Cc: Stephen Boyd <[email protected]> Cc: [email protected] Cc: [email protected] Signed-off-by: Rob Herring <[email protected]> Link: https://lore.kernel.org/r/[email protected] Reviewed-by: Linus Walleij <[email protected]> Signed-off-by: Stephen Boyd <[email protected]>
2021-09-14clk: mediatek: Add MT8195 apusys clock supportChun-Jie Chen2-1/+94
Add MT8195 apusys clock controller which provides PLLs in AI processor Unit. Signed-off-by: Chun-Jie Chen <[email protected]> Reviewed-by: Chen-Yu Tsai <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Stephen Boyd <[email protected]>
2021-09-14clk: mediatek: Add MT8195 imp i2c wrapper clock supportChun-Jie Chen2-1/+69
Add MT8195 imp i2c wrapper clock controllers which provide clock gate control in I2C IP blocks. Signed-off-by: Chun-Jie Chen <[email protected]> Reviewed-by: Chen-Yu Tsai <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Stephen Boyd <[email protected]>
2021-09-14clk: mediatek: Add MT8195 wpesys clock supportChun-Jie Chen2-1/+145
Add MT8195 wpesys clock controllers which provide clock gate control in Wrapping Engine. Signed-off-by: Chun-Jie Chen <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Stephen Boyd <[email protected]>
2021-09-14clk: mediatek: Add MT8195 vppsys1 clock supportChun-Jie Chen2-1/+109
Add MT8195 vppsys1 clock controller which provides clock gate controller for Video Processor Pipe. Signed-off-by: Chun-Jie Chen <[email protected]> Reviewed-by: Chen-Yu Tsai <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Stephen Boyd <[email protected]>
2021-09-14clk: mediatek: Add MT8195 vppsys0 clock supportChun-Jie Chen2-1/+111
Add MT8195 vppsys0 clock controller which provides clock gate controller for Video Processor Pipe. Signed-off-by: Chun-Jie Chen <[email protected]> Reviewed-by: Chen-Yu Tsai <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Stephen Boyd <[email protected]>
2021-09-14clk: mediatek: Add MT8195 vencsys clock supportChun-Jie Chen2-1/+71
Add MT8195 vencsys clock controllers which provide clock gate control for video encoder. Signed-off-by: Chun-Jie Chen <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Stephen Boyd <[email protected]>
2021-09-14clk: mediatek: Add MT8195 vdosys1 clock supportChun-Jie Chen2-1/+141
Add MT8195 vdosys1 clock controller which provides clock gate control in video system. This is integrated with mtk-mmsys driver which will populate device by platform_device_register_data to start vdosys clock driver. Signed-off-by: Chun-Jie Chen <[email protected]> Link: https://lore.kernel.org/r/[email protected] Reviewed-by: Chen-Yu Tsai <[email protected]> Signed-off-by: Stephen Boyd <[email protected]>
2021-09-14clk: mediatek: Add MT8195 vdosys0 clock supportChun-Jie Chen2-1/+124
Add MT8195 vdosys0 clock controller which provides clock gate control in video system. This is integrated with mtk-mmsys driver which will populate device by platform_device_register_data to start vdosys clock driver. Signed-off-by: Chun-Jie Chen <[email protected]> Link: https://lore.kernel.org/r/[email protected] Reviewed-by: Chen-Yu Tsai <[email protected]> Signed-off-by: Stephen Boyd <[email protected]>
2021-09-14clk: mediatek: Add MT8195 vdecsys clock supportChun-Jie Chen2-1/+106
Add MT8195 vdec clock controllers which provide clock gate control for video decoder. Signed-off-by: Chun-Jie Chen <[email protected]> Reviewed-by: Chen-Yu Tsai <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Stephen Boyd <[email protected]>
2021-09-14clk: mediatek: Add MT8195 scp adsp clock supportChun-Jie Chen2-1/+48
Add MT8195 scp adsp clock controller which provides clock gate control for Audio DSP. Signed-off-by: Chun-Jie Chen <[email protected]> Reviewed-by: Chen-Yu Tsai <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Stephen Boyd <[email protected]>
2021-09-14clk: mediatek: Add MT8195 mfgcfg clock supportChun-Jie Chen2-1/+48
Add MT8195 mfg clock controller which provides clock gate control for GPU. Signed-off-by: Chun-Jie Chen <[email protected]> Link: https://lore.kernel.org/r/[email protected] Reviewed-by: Chen-Yu Tsai <[email protected]> Signed-off-by: Stephen Boyd <[email protected]>
2021-09-14clk: mediatek: Add MT8195 ipesys clock supportChun-Jie Chen2-1/+53
Add MT8195 ipesys clock controller which provides clock gate control for Image Process Engine. Signed-off-by: Chun-Jie Chen <[email protected]> Link: https://lore.kernel.org/r/[email protected] Reviewed-by: Chen-Yu Tsai <[email protected]> Signed-off-by: Stephen Boyd <[email protected]>
2021-09-14clk: mediatek: Add MT8195 imgsys clock supportChun-Jie Chen2-1/+97
Add MT8195 imgsys clock controllers which provide clock gate control for image IP blocks. Signed-off-by: Chun-Jie Chen <[email protected]> Reviewed-by: Chen-Yu Tsai <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Stephen Boyd <[email protected]>
2021-09-14clk: mediatek: Add MT8195 ccusys clock supportChun-Jie Chen2-1/+51
Add MT8195 ccusys clock controller which provides clock gate control in Camera Computing Unit. Signed-off-by: Chun-Jie Chen <[email protected]> Reviewed-by: Chen-Yu Tsai <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Stephen Boyd <[email protected]>
2021-09-14clk: mediatek: Add MT8195 camsys clock supportChun-Jie Chen2-1/+144
Add MT8195 camsys clock controllers which provide clock gate control for camera IP blocks. Signed-off-by: Chun-Jie Chen <[email protected]> Reviewed-by: Chen-Yu Tsai <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Stephen Boyd <[email protected]>
2021-09-14clk: mediatek: Add MT8195 infrastructure clock supportChun-Jie Chen2-1/+207
Add MT8195 infrastructure clock controller which provides clock gate control for basic IP like pwm, uart, spi and so on. Signed-off-by: Chun-Jie Chen <[email protected]> Link: https://lore.kernel.org/r/[email protected] Reviewed-by: Chen-Yu Tsai <[email protected]> Signed-off-by: Stephen Boyd <[email protected]>
2021-09-14clk: mediatek: Add MT8195 peripheral clock supportChun-Jie Chen2-1/+64
Add MT8195 peripheral clock controller which provides clock gate control for ethernet/flashif/pcie/ssusb. Signed-off-by: Chun-Jie Chen <[email protected]> Reviewed-by: Chen-Yu Tsai <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Stephen Boyd <[email protected]>
2021-09-14clk: mediatek: Add MT8195 topckgen clock supportChun-Jie Chen2-1/+1274
Add MT8195 topckgen clock controller which provides muxes, dividers to handle variety clock selection in other IP blocks. Signed-off-by: Chun-Jie Chen <[email protected]> Link: https://lore.kernel.org/r/[email protected] Reviewed-by: Chen-Yu Tsai <[email protected]> Signed-off-by: Stephen Boyd <[email protected]>
2021-09-14clk: mediatek: Add MT8195 apmixedsys clock supportChun-Jie Chen3-0/+154
Add MT8195 apmixedsys clock controller which provides Plls generated from SoC 26m and ssusb clock gate control. Signed-off-by: Chun-Jie Chen <[email protected]> Reviewed-by: Chen-Yu Tsai <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Stephen Boyd <[email protected]>
2021-09-14clk: mediatek: Fix resource leak in mtk_clk_simple_probeChun-Jie Chen1-2/+10
Release clock data when clock driver probe fail to fix possible resource leak. Signed-off-by: Chun-Jie Chen <[email protected]> Reviewed-by: Chen-Yu Tsai <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Stephen Boyd <[email protected]>
2021-09-14clk: mediatek: Add API for clock resource recycleChun-Jie Chen2-0/+10
In order to avoid resource leak when fail clock registration appears, so adds the common interface to handle it. Signed-off-by: Chun-Jie Chen <[email protected]> Reviewed-by: Chen-Yu Tsai <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Stephen Boyd <[email protected]>
2021-09-14clk: mediatek: Fix corner case of tuner_en_regChun-Jie Chen1-1/+1
On MT8195, tuner_en_reg is moved to register offest 0x0. If we only judge by tuner_en_reg, it may lead to wrong address. Add tuner_en_bit to the check condition. And it has been confirmed, on all the MediaTek SoCs, bit0 of offset 0x0 is always occupied by clock square control. Signed-off-by: Chun-Jie Chen <[email protected]> Reviewed-by: Chen-Yu Tsai <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Stephen Boyd <[email protected]>
2021-09-14clk: qcom: mmcc-msm8998: Remove unnecessary fallbacks to global clocksMarijn Suijten1-57/+48
A previous patch removes the "xo" clock from the global namespace making it impossible to acquire by that ".name". The device-tree for msm8998 currently does not include an mmcc node but the dt-bindings for this compatible already require all these clocks, and the patch introducing this node [1] also includes them. [1]: https://patchwork.kernel.org/project/linux-arm-msm/patch/20210901183123.1087392-1-angelogioacchino.delregno@somainline.org/ Reviewed-by: AngeloGioacchino Del Regno <[email protected]> Signed-off-by: Marijn Suijten <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Stephen Boyd <[email protected]>
2021-09-14clk: qcom: gpucc-msm8998: Remove unnecessary fallbacks to global clocksMarijn Suijten1-3/+2
A previous patch removes the "xo" clock from the global namespace making it impossible to acquire by that ".name". The device-tree for msm8998 already provides the "xo" and "gpll0" clock since the addition of the gpucc node making it unnecessary to have this fallback at all. Reviewed-by: AngeloGioacchino Del Regno <[email protected]> Signed-off-by: Marijn Suijten <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Stephen Boyd <[email protected]>
2021-09-14clk: qcom: mmcc-msm8998: Use ARRAY_SIZE for num_parentsMarijn Suijten1-39/+39
Where possible, use ARRAY_SIZE to determine the number of parents in clk_parent_data, instead of hardcoding it. Reviewed-by: AngeloGioacchino Del Regno <[email protected]> Signed-off-by: Marijn Suijten <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Stephen Boyd <[email protected]>
2021-09-14clk: qcom: gpucc-msm8998: Use ARRAY_SIZE for num_parentsMarijn Suijten1-4/+4
Where possible, use ARRAY_SIZE to determine the number of parents in clk_parent_data, instead of hardcoding it. Reviewed-by: AngeloGioacchino Del Regno <[email protected]> Signed-off-by: Marijn Suijten <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Stephen Boyd <[email protected]>
2021-09-14clk: qcom: gcc-msm8998: Remove transient global "xo" clockMarijn Suijten1-27/+30
Now that all clock controllers and the DSI PLL clocks rely on "xo" being passed in DT as phandle instead of looking it up by the global "xo" name this transient clock can be removed, leaving only the fixed-factor "xo_board" clock in DT. Reviewed-by: AngeloGioacchino Del Regno <[email protected]> Signed-off-by: Marijn Suijten <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Stephen Boyd <[email protected]>
2021-09-14clk: qcom: gcc-msm8998: Use parent_data/hws for internal clock relationsMarijn Suijten1-241/+281
Use parent_data and parent_hws to specify internal relations using pointers instead of names, and use .fw_name to retrieve external clocks from clock-names in the DT rather than the global clock tree. Note that this change relies on the "xo" and "sleep_clk" clocks to be provided in DT, as per the relevant qcom,gcc-mnsm8998.yaml dt-bindings. These clocks have been added in a prior patch [1]. [1]: https://lore.kernel.org/linux-arm-msm/[email protected]/ Reviewed-by: AngeloGioacchino Del Regno <[email protected]> Signed-off-by: Marijn Suijten <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Stephen Boyd <[email protected]>
2021-09-14clk: qcom: gcc-msm8998: Move parent names and mapping below GPLLsMarijn Suijten1-92/+92
Prepare for a future patch where we use .hw pointers to these GPLL clocks in the parent mapping instead of name references. This requires the GPLL clocks to be decared before parent_data arrays. Reviewed-by: AngeloGioacchino Del Regno <[email protected]> Signed-off-by: Marijn Suijten <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Stephen Boyd <[email protected]>
2021-09-14clk: qcom: kpss-xcc: Make use of the helper function ↵Cai Huoqing1-3/+1
devm_platform_ioremap_resource() Use the devm_platform_ioremap_resource() helper instead of calling platform_get_resource() and devm_ioremap_resource() separately Signed-off-by: Cai Huoqing <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Stephen Boyd <[email protected]>
2021-09-14clk: qcom: common: Make use of the helper function ↵Cai Huoqing1-6/+2
devm_platform_ioremap_resource() Use the devm_platform_ioremap_resource() helper instead of calling platform_get_resource() and devm_ioremap_resource() separately Signed-off-by: Cai Huoqing <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Stephen Boyd <[email protected]>
2021-09-14clk: qcom: a53-pll: Make use of the helper function ↵Cai Huoqing1-3/+1
devm_platform_ioremap_resource() Use the devm_platform_ioremap_resource() helper instead of calling platform_get_resource() and devm_ioremap_resource() separately Signed-off-by: Cai Huoqing <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Stephen Boyd <[email protected]>
2021-09-14clk: qcom: gpucc-sdm660: Remove fallback to global clock namesMarijn Suijten1-5/+4
The necessary clocks for this driver are already fully specified in sdm630 DT under the .fw_name, and do not need an implicit fallback to their global name. Signed-off-by: Marijn Suijten <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Stephen Boyd <[email protected]>
2021-09-14clk: qcom: mmcc-sdm660: Use ARRAY_SIZE for num_parentsMarijn Suijten1-36/+36
Where possible, use ARRAY_SIZE to determine the number of parents in clk_parent_data, instead of hardcoding it. Signed-off-by: Marijn Suijten <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Stephen Boyd <[email protected]>
2021-09-14clk: qcom: gpucc-sdm660: Use ARRAY_SIZE for num_parentsMarijn Suijten1-3/+3
Where possible, use ARRAY_SIZE to determine the number of parents in clk_parent_data, instead of hardcoding it. Signed-off-by: Marijn Suijten <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Stephen Boyd <[email protected]>
2021-09-14clk: qcom: gcc-sdm660: Use ARRAY_SIZE for num_parentsMarijn Suijten1-40/+40
Where possible, use ARRAY_SIZE to determine the number of parents in clk_parent_data instead of hardcoding a number that relies on an array defined hundreds of lines above. Signed-off-by: Marijn Suijten <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Stephen Boyd <[email protected]>
2021-09-13clk: samsung: s5pv210-audss: Make use of devm_platform_ioremap_resource()Cai Huoqing1-3/+1
Use the devm_platform_ioremap_resource() helper instead of calling platform_get_resource() and devm_ioremap_resource() separately Signed-off-by: Cai Huoqing <[email protected]> Signed-off-by: Sylwester Nawrocki <[email protected]> Reviewed-by: Krzysztof Kozlowski <[email protected]> Link: https://lore.kernel.org/r/[email protected]
2021-09-13clk: samsung: exynos5433: Make use of devm_platform_ioremap_resource()Cai Huoqing1-3/+1
Use the devm_platform_ioremap_resource() helper instead of calling platform_get_resource() and devm_ioremap_resource() separately Signed-off-by: Cai Huoqing <[email protected]> Signed-off-by: Sylwester Nawrocki <[email protected]> Reviewed-by: Krzysztof Kozlowski <[email protected]> Link: https://lore.kernel.org/r/[email protected]
2021-09-13clk: samsung: exynos4412-isp: Make use of devm_platform_ioremap_resource()Cai Huoqing1-3/+1
Use the devm_platform_ioremap_resource() helper instead of calling platform_get_resource() and devm_ioremap_resource() separately Signed-off-by: Cai Huoqing <[email protected]> Signed-off-by: Sylwester Nawrocki <[email protected]> Reviewed-by: Krzysztof Kozlowski <[email protected]> Link: https://lore.kernel.org/r/[email protected]
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