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2022-09-13clk: qcom: mmcc-msm8960: use ARRAY_SIZE instead of specifying num_parentsDmitry Baryshkov1-42/+42
Use ARRAY_SIZE() instead of manually specifying num_parents. This makes adding/removing entries to/from parent_data easy and errorproof. Signed-off-by: Dmitry Baryshkov <[email protected]> Tested-by: David Heidelberg <[email protected]> # tested on Nexus 7 (2013) Signed-off-by: Bjorn Andersson <[email protected]> Link: https://lore.kernel.org/r/[email protected]
2022-09-13clk: qcom: lcc-msm8960: use parent_hws/_data instead of parent_namesDmitry Baryshkov1-32/+37
Convert the clock driver to specify parent data rather than parent names, to actually bind using 'clock-names' specified in the DTS rather than global clock names. Use parent_hws where possible to refer parent clocks directly, skipping the lookup. Signed-off-by: Dmitry Baryshkov <[email protected]> Tested-by: David Heidelberg <[email protected]> # tested on Nexus 7 (2013) Signed-off-by: Bjorn Andersson <[email protected]> Link: https://lore.kernel.org/r/[email protected]
2022-09-13clk: qcom: lcc-msm8960: use macros to implement mi2s clocksDmitry Baryshkov1-115/+27
Split and extend existing CLK_AIF_OSR_DIV macro to implement mi2s clocks. This simplifies the driver and removes extra code duplication. The clock mi2s_div_clk used .enable_reg/.enable_bit, however these fields are not used with by the clk_regmap_div_ops, thus they are silently dropped. Clock enablement is handled in the mi2s_bit_div_clk clock. Signed-off-by: Dmitry Baryshkov <[email protected]> Tested-by: David Heidelberg <[email protected]> # tested on Nexus 7 (2013) Signed-off-by: Bjorn Andersson <[email protected]> Link: https://lore.kernel.org/r/[email protected]
2022-09-13clk: qcom: gcc-msm8960: use parent_hws/_data instead of parent_namesDmitry Baryshkov1-132/+232
Convert the clock driver to specify parent data rather than parent names, to actually bind using 'clock-names' specified in the DTS rather than global clock names. Use parent_hws where possible to refer parent clocks directly, skipping the lookup. Signed-off-by: Dmitry Baryshkov <[email protected]> Tested-by: David Heidelberg <[email protected]> # tested on Nexus 7 (2013) Signed-off-by: Bjorn Andersson <[email protected]> Link: https://lore.kernel.org/r/[email protected]
2022-09-13clk: qcom: gcc-msm8960: use ARRAY_SIZE instead of specifying num_parentsDmitry Baryshkov1-48/+48
Use ARRAY_SIZE() instead of manually specifying num_parents. This makes adding/removing entries to/from parent_data easy and errorproof. Signed-off-by: Dmitry Baryshkov <[email protected]> Tested-by: David Heidelberg <[email protected]> # tested on Nexus 7 (2013) Signed-off-by: Bjorn Andersson <[email protected]> Link: https://lore.kernel.org/r/[email protected]
2022-09-13clk: qcom: clk-rpmh: Remove redundant if statementLi Zhengyu1-4/+0
By the clk framework already reference counts prepare/unprepare, this if statement should be never true. Signed-off-by: Li Zhengyu <[email protected]> Reviewed-by: Stephen Boyd <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Bjorn Andersson <[email protected]>
2022-09-13clk: qcom: gcc-sdm845: add sdm670 global clock dataRichard Acayan2-2/+396
The Snapdragon 670 adds and removes some clocks, adds new frequencies, and adds a new GPLL (Global Phase-Locked Loop) in reference to SDM845, while also removing some GDSCs. Despite these differences, there are many similarities with SDM670. Add data for SDM670 in the driver for SDM845 to reuse the most of the clock data. Advantages and disadvantages of this approach: + maintenance applies to both sdm670 and sdm845 by default + less duplicate code (clocks) means smaller distro/pre-built kernels with all drivers enabled - clocks for both SoC's must be compiled if the user wants clocks for one specific SoC (both or none) - additional testing needed for sdm845 devices Link: https://android.googlesource.com/kernel/msm/+/443bd8d6e2cf54698234c752e6de97b4b8a528bd%5E%21/#F10 Signed-off-by: Richard Acayan <[email protected]> Reviewed-by: Krzysztof Kozlowski <[email protected]> Signed-off-by: Bjorn Andersson <[email protected]> Link: https://lore.kernel.org/r/[email protected]
2022-09-13clk: qcom: gcc-sdm845: use device tree match dataRichard Acayan1-2/+4
This driver will support more than one SoC's set of clocks, and set of GDSCs. This behavior would be unclean with hard-coded static variables. Support it by grabbing clocks, GDSCs, and BCRs in the match data. Signed-off-by: Richard Acayan <[email protected]> Reviewed-by: Krzysztof Kozlowski <[email protected]> Signed-off-by: Bjorn Andersson <[email protected]> Link: https://lore.kernel.org/r/[email protected]
2022-09-13clk: qcom: a53-pll: convert to use parent_data rather than parent_namesDmitry Baryshkov1-1/+3
Change a53-pll driver to use clk_parent_data rather than always looking up the xo clock in the system clock list. Note, this change also switches the a53-pll from the global `xo' clock to the `xo_board', the clock that is specified as the `xo' clock in the DT file. Signed-off-by: Dmitry Baryshkov <[email protected]> Signed-off-by: Bjorn Andersson <[email protected]> Link: https://lore.kernel.org/r/[email protected]
2022-09-13clk: qcom: gcc-msm8660: use parent_hws/_data instead of parent_namesDmitry Baryshkov1-100/+164
Convert the clock driver to specify parent data rather than parent names, to actually bind using 'clock-names' specified in the DTS rather than global clock names. Use parent_hws where possible to refer parent clocks directly, skipping the lookup. Signed-off-by: Dmitry Baryshkov <[email protected]> Signed-off-by: Bjorn Andersson <[email protected]> Link: https://lore.kernel.org/r/[email protected]
2022-09-13clk: qcom: gcc-msm8660: use ARRAY_SIZE instead of specifying num_parentsDmitry Baryshkov1-41/+41
Use ARRAY_SIZE() instead of manually specifying num_parents. This makes adding/removing entries to/from parent_data easy and errorproof. Signed-off-by: Dmitry Baryshkov <[email protected]> Reviewed-by: Krzysztof Kozlowski <[email protected]> Signed-off-by: Bjorn Andersson <[email protected]> Link: https://lore.kernel.org/r/[email protected]
2022-09-13clk: qcom: sm6115: Select QCOM_GDSCDang Huynh1-0/+1
While working on the Fxtec Pro1X device, this error shows up with my own minimal configuration: gcc-sm6115: probe of 1400000.clock-controller failed with error -38 The clock driver depends on CONFIG_QCOM_GDSC and after enabling that, the driver probes successfully. Signed-off-by: Dang Huynh <[email protected]> Fixes: cbe63bfdc54f ("clk: qcom: Add Global Clock controller (GCC) Reviewed-by: Dmitry Baryshkov <[email protected]> Signed-off-by: Bjorn Andersson <[email protected]> Link: https://lore.kernel.org/r/[email protected]
2022-09-13clk: qcom: lpass: Add support for resets & external mclk for SC7280Taniya Das2-2/+55
The clock gating control for TX/RX/WSA core bus clocks would be required to be reset(moved from hardware control) from audio core driver. Thus add the support for the reset clocks. Update the lpass_aon_cc_main_rcg_clk_src ops to park the RCG at XO after disable as this clock signal is used by hardware to turn ON memories in LPASS. Also add the external mclk to interface external MI2S. Fixes: a9dd26639d05 ("clk: qcom: lpass: Add support for LPASS clock controller for SC7280") Signed-off-by: Taniya Das <[email protected]> Reviewed-by: Stephen Boyd <[email protected]> Signed-off-by: Bjorn Andersson <[email protected]> Link: https://lore.kernel.org/r/[email protected]
2022-09-13clk: qcom: lpass: Handle the regmap overlap of lpasscc and lpass_aonTaniya Das2-44/+44
Move registration of lpass_q6ss_ahbm_clk and lpass_q6ss_ahbs_clk to lpass_aon_cc_sc7280_probe and register them only if "qcom,adsp-pil-mode" is enabled in the lpass_aon DT node. Signed-off-by: Taniya Das <[email protected]> Signed-off-by: Satya Priya <[email protected]> Reviewed-by: Stephen Boyd <[email protected]> Signed-off-by: Bjorn Andersson <[email protected]> Link: https://lore.kernel.org/r/[email protected]
2022-09-13clk: rockchip: Add MUXTBL variantElaine Zhang2-6/+38
Add a clock branch consisting of a mux with non-standard select values. The parent in Mux table is sorted by priority. Use clk_register_mux_table() to register such a mux-clock. Cc: [email protected] Cc: Michael Turquette <[email protected]> Cc: Stephen Boyd <[email protected]> Signed-off-by: Elaine Zhang <[email protected]> Signed-off-by: Jagan Teki <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Heiko Stuebner <[email protected]>
2022-09-08clk: sunxi-ng: ccu-sun9i-a80-usb: Use dev_err_probe() helperYang Yingliang1-6/+3
dev_err() can be replace with dev_err_probe() which will check if error code is -EPROBE_DEFER. Signed-off-by: Yang Yingliang <[email protected]> Reviewed-by: Jernej Skrabec <[email protected]> Signed-off-by: Jernej Skrabec <[email protected]> Link: https://lore.kernel.org/r/[email protected]
2022-09-08clk: sunxi-ng: ccu-sun9i-a80-de: Use dev_err_probe() helperYang Yingliang1-13/+6
dev_err() can be replace with dev_err_probe() which will check if error code is -EPROBE_DEFER. Signed-off-by: Yang Yingliang <[email protected]> Reviewed-by: Jernej Skrabec <[email protected]> Signed-off-by: Jernej Skrabec <[email protected]> Link: https://lore.kernel.org/r/[email protected]
2022-09-08clk: sunxi-ng: sun8i-de2: Use dev_err_probe() helperYang Yingliang1-19/+9
dev_err() can be replace with dev_err_probe() which will check if error code is -EPROBE_DEFER. Signed-off-by: Yang Yingliang <[email protected]> Reviewed-by: Jernej Skrabec <[email protected]> Signed-off-by: Jernej Skrabec <[email protected]> Link: https://lore.kernel.org/r/[email protected]
2022-09-02clk: imx8mp: tune the order of enet_qos_root_clkPeng Fan1-1/+1
The enet_qos_root_clk takes sim_enet_root_clk as parent. When registering enet_qos_root_clk, it will be put into clk orphan list, because sim_enet_root_clk is not ready. When sim_enet_root_clk is ready, clk_core_reparent_orphans_nolock will set enet_qos_root_clk parent to sim_enet_root_clk. Because CLK_OPS_PARENT_ENABLE is set, sim_enet_root_clk will be enabled and disabled during the enet_qos_root_clk reparent phase. All the above are correct. But with M7 booted early and using enet, M7 enet feature will be broken, because clk driver probe phase disable the needed clks, in case M7 firmware not configure sim_enet_root_clk. And tune the order would also save cpu cycles. Reviewed-by: Ye Li <[email protected]> Signed-off-by: Peng Fan <[email protected]> Reviewed-by: Abel Vesa <[email protected]> Signed-off-by: Abel Vesa <[email protected]> Link: https://lore.kernel.org/r/[email protected]
2022-08-31clk: ingenic-tcu: Properly enable registers before accessing timersAidan MacDonald1-10/+5
Access to registers is guarded by ingenic_tcu_{enable,disable}_regs() so the stop bit can be cleared before accessing a timer channel, but those functions did not clear the stop bit on SoCs with a global TCU clock gate. Testing on the X1000 has revealed that the stop bits must be cleared _and_ the global TCU clock must be ungated to access timer registers. This appears to be the norm on Ingenic SoCs, and is specified in the documentation for the X1000 and numerous JZ47xx SoCs. If the stop bit isn't cleared, register writes don't take effect and the system can be left in a broken state, eg. the watchdog timer may not run. The bug probably went unnoticed because stop bits are zeroed when the SoC is reset, and the kernel does not set them unless a timer gets disabled at runtime. However, it is possible that a bootloader or a previous kernel (if using kexec) leaves the stop bits set and we should not rely on them being cleared. Fixing this is easy: have ingenic_tcu_{enable,disable}_regs() always clear the stop bit, regardless of the presence of a global TCU gate. Reviewed-by: Paul Cercueil <[email protected]> Tested-by: Paul Cercueil <[email protected]> Fixes: 4f89e4b8f121 ("clk: ingenic: Add driver for the TCU clocks") Cc: [email protected] Signed-off-by: Aidan MacDonald <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Stephen Boyd <[email protected]>
2022-08-31clk: mediatek: mt8195: Add reset idx for USB/PCIe T-PHYAngeloGioacchino Del Regno1-0/+1
Add the reset idx for the t-phy port 1, used as either USB or PCI-Express (secondary controller) PHY, depending on board-specific configuration/layout. Signed-off-by: AngeloGioacchino Del Regno <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Stephen Boyd <[email protected]>
2022-08-31clk: mediatek: mt8195-infra_ao: Set pwrmcu clocks as criticalAngeloGioacchino Del Regno1-3/+10
The pwrmcu is responsible for power management and idle states in SSPM: on older SoCs this was managed in Linux drivers like sspm/mcupm/eemgpu but, at least on MT8195, this functionality was transferred to the ATF firmware. For this reason, turning off the pwrmcu related clocks from the kernel will lead to unability to resume the platform after suspend and other currently unknown PM related side-effects. Set the PWRMCU and PWRMCU_BUS_H clocks as critical to prevent the kernel from turning them off, fixing the aforementioned issue. Fixes: e2edf59dec0b ("clk: mediatek: Add MT8195 infrastructure clock support") Signed-off-by: AngeloGioacchino Del Regno <[email protected]> Link: https://lore.kernel.org/r/[email protected] Reviewed-by: Matthias Brugger <[email protected]> Signed-off-by: Stephen Boyd <[email protected]>
2022-08-31clk: mediatek: mt8195: Add reset idx for PCIe0 and PCIe1AngeloGioacchino Del Regno1-0/+2
Add the reset idx for PCIe P0, P1, located in infra_ao RST2 registers. Signed-off-by: AngeloGioacchino Del Regno <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Stephen Boyd <[email protected]>
2022-08-31clk: davinci: remove PLL and PSC clocks for DaVinci DM644x and DM646xLukas Bulwahn9-363/+0
Commit 7dd33764486d ("ARM: davinci: Delete DM644x board files") and commit b4aed01de486 ("ARM: davinci: Delete DM646x board files") removes the support for DaVinci DM644x and DM646x boards. Hence, remove the PLL and PSC clock descriptions for those boards as well. Signed-off-by: Lukas Bulwahn <[email protected]> Link: https://lore.kernel.org/r/[email protected] Reviewed-by: David Lechner <[email protected]> Reviewed-by: Linus Walleij <[email protected]> Signed-off-by: Stephen Boyd <[email protected]>
2022-08-31Revert "clk: core: Honor CLK_OPS_PARENT_ENABLE for clk gate ops"Stephen Boyd1-28/+0
This reverts commit 35b0fac808b95eea1212f8860baf6ad25b88b087. Alexander reports that it causes boot failures on i.MX8M Plus based boards (specifically imx8mp-tqma8mpql-mba8mpxl.dts). Reported-by: Alexander Stein <[email protected]> Cc: Chen-Yu Tsai <[email protected]> Fixes: 35b0fac808b9 ("clk: core: Honor CLK_OPS_PARENT_ENABLE for clk gate ops") Link: https://lore.kernel.org/r/12115951.O9o76ZdvQC@steina-w Signed-off-by: Stephen Boyd <[email protected]> Link: https://lore.kernel.org/r/[email protected]
2022-08-31clk: mediatek: clk-mt8195-vdo1: Reparent and set rate on vdo1_dpintf's parentAngeloGioacchino Del Regno1-1/+5
Like it was done for the vdo0_dp_intf0_dp_intf clock (used for eDP), add the CLK_SET_RATE_PARENT flag to CLK_VDO1_DPINTF (used for DP) and also fix its parent clock name as it has to be "top_dp" for two reasons: - This is its real parent! - Likewise to eDP/VDO0 counterpart, we need clock source selection on CLK_TOP_DP. Fixes: 269987505ba9 ("clk: mediatek: Add MT8195 vdosys1 clock support") Signed-off-by: AngeloGioacchino Del Regno <[email protected]> Tested-by: Bo-Chen Chen <[email protected]> Reviewed-by: Bo-Chen Chen <[email protected]> Signed-off-by: Nícolas F. R. A. Prado <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Stephen Boyd <[email protected]>
2022-08-31clk: mediatek: clk-mt8195-vdo0: Set rate on vdo0_dp_intf0_dp_intf's parentAngeloGioacchino Del Regno1-1/+6
Add the CLK_SET_RATE_PARENT flag to the CLK_VDO0_DP_INTF0_DP_INTF clock: this is required to trigger clock source selection on CLK_TOP_EDP, while avoiding to manage the enablement of the former separately from the latter in the displayport driver. Fixes: 70282c90d4a2 ("clk: mediatek: Add MT8195 vdosys0 clock support") Signed-off-by: AngeloGioacchino Del Regno <[email protected]> Tested-by: Bo-Chen Chen <[email protected]> Reviewed-by: Bo-Chen Chen <[email protected]> Signed-off-by: Nícolas F. R. A. Prado <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Stephen Boyd <[email protected]>
2022-08-30clk: zynqmp: pll: rectify rate rounding in zynqmp_pll_round_rateQuanyang Wang1-16/+15
The function zynqmp_pll_round_rate is used to find a most appropriate PLL frequency which the hardware can generate according to the desired frequency. For example, if the desired frequency is 297MHz, considering the limited range from PS_PLL_VCO_MIN (1.5GHz) to PS_PLL_VCO_MAX (3.0GHz) of PLL, zynqmp_pll_round_rate should return 1.872GHz (297MHz * 5). There are two problems with the current code of zynqmp_pll_round_rate: 1) When the rate is below PS_PLL_VCO_MIN, it can't find a correct rate when the parameter "rate" is an integer multiple of *prate, in other words, if "f" is zero, zynqmp_pll_round_rate won't return a valid frequency which is from PS_PLL_VCO_MIN to PS_PLL_VCO_MAX. For example, *prate is 33MHz and the rate is 660MHz, zynqmp_pll_round_rate will not boost up rate and just return 660MHz, and this will cause clk_calc_new_rates failure since zynqmp_pll_round_rate returns an invalid rate out of its boundaries. 2) Even if the rate is higher than PS_PLL_VCO_MIN, there is still a risk that zynqmp_pll_round_rate returns an invalid rate because the function DIV_ROUND_CLOSEST makes some loss in the fractional part. If the parent clock *prate is 33333333Hz and we want to set the PLL rate to 1.5GHz, this function will return 1499999985Hz by using the formula below: value = *prate * DIV_ROUND_CLOSEST(rate, *prate)). This value is also invalid since it's slightly smaller than PS_PLL_VCO_MIN. because DIV_ROUND_CLOSEST makes some loss in the fractional part. Signed-off-by: Quanyang Wang <[email protected]> Link: https://lore.kernel.org/r/[email protected] Reviewed-by: Shubhrajyoti Datta <[email protected]> Signed-off-by: Stephen Boyd <[email protected]>
2022-08-29clk: qcom: gcc-sdm660: Use floor ops for SDCC1 clockMarijn Suijten1-1/+1
In commit 3f905469c8ce ("clk: qcom: gcc: Use floor ops for SDCC clocks") floor ops were applied to SDCC2 only, but flooring is also required on the SDCC1 apps clock which is used by the eMMC card on Sony's Nile platform, and otherwise result in the typicial "Card appears overclocked" warnings observed on many other platforms before: mmc0: Card appears overclocked; req 52000000 Hz, actual 100000000 Hz mmc0: Card appears overclocked; req 52000000 Hz, actual 100000000 Hz mmc0: Card appears overclocked; req 104000000 Hz, actual 192000000 Hz Fixes: f2a76a2955c0 ("clk: qcom: Add Global Clock controller (GCC) driver for SDM660") Signed-off-by: Marijn Suijten <[email protected]> Tested-by: Alexey Minnekhanov <[email protected]> Reviewed-by: Stephen Boyd <[email protected]> Signed-off-by: Bjorn Andersson <[email protected]> Link: https://lore.kernel.org/r/[email protected]
2022-08-29clk: qcom: gcc-msm8916: use parent_hws/_data instead of parent_namesDmitry Baryshkov1-333/+349
Convert the clock driver to specify parent data rather than parent names, to actually bind using 'clock-names' specified in the DTS rather than global clock names. Use parent_hws where possible to refer parent clocks directly, skipping the lookup. Reviewed-by: Marijn Suijten <[email protected]> Reviewed-by: Konrad Dybcio <[email protected]> Signed-off-by: Dmitry Baryshkov <[email protected]> Signed-off-by: Bjorn Andersson <[email protected]> Link: https://lore.kernel.org/r/[email protected]
2022-08-29clk: qcom: gcc-msm8916: move gcc_mss_q6_bimc_axi_clk downDmitry Baryshkov1-17/+17
The gcc_mss_q6_bimc_axi_clk clock depends on the bimc_ddr_clk_src clock. Move it down in the file to come after the source clock. Reviewed-by: Marijn Suijten <[email protected]> Reviewed-by: Konrad Dybcio <[email protected]> Signed-off-by: Dmitry Baryshkov <[email protected]> Signed-off-by: Bjorn Andersson <[email protected]> Link: https://lore.kernel.org/r/[email protected]
2022-08-29clk: qcom: gcc-msm8916: move GPLL definitions upDmitry Baryshkov1-108/+108
Move GPLL definitions up, before the clock parent tables, so that we can use gpll hw clock fields in the parent_data/parent_hws tables. Reviewed-by: Marijn Suijten <[email protected]> Reviewed-by: Konrad Dybcio <[email protected]> Signed-off-by: Dmitry Baryshkov <[email protected]> Signed-off-by: Bjorn Andersson <[email protected]> Link: https://lore.kernel.org/r/[email protected]
2022-08-29clk: qcom: gcc-msm8916: use ARRAY_SIZE instead of specifying num_parentsDmitry Baryshkov1-54/+54
Use ARRAY_SIZE() instead of manually specifying num_parents. This makes adding/removing entries to/from parent_data easy and errorproof. This conversion fixes an issue present since the first version of this driver. For the gp1_clk_src, gp2_clk_src and gp3_clk_src it was impossible to select sleep_clk as a prent of the clock, since num_parents was limited to 3 rather than 4. Switching to use num_parents automatically makes sleep_clk available for selection. Fixes: 3966fab8b6ab ("clk: qcom: Add MSM8916 Global Clock Controller support") Cc: Georgi Djakov <[email protected]> Reviewed-by: Marijn Suijten <[email protected]> Reviewed-by: Konrad Dybcio <[email protected]> Signed-off-by: Dmitry Baryshkov <[email protected]> Acked-by: Georgi Djakov <[email protected]> Signed-off-by: Bjorn Andersson <[email protected]> Link: https://lore.kernel.org/r/[email protected]
2022-08-29clk: renesas: r8a779f0: Add MSIOF clocksWolfram Sang1-0/+4
Signed-off-by: Wolfram Sang <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Geert Uytterhoeven <[email protected]>
2022-08-29clk: renesas: r9a09g011: Add IIC clock and reset entriesPhil Edworthy1-0/+4
Add IIC groups clock and reset entries to CPG driver. IIC Group A consists of IIC0 and IIC1. IIC Group B consists of IIC2 and IIC3. To confuse things, IIC_PCLK0 is used by group A and IIC_PCLK1 is used by group B. Signed-off-by: Phil Edworthy <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Geert Uytterhoeven <[email protected]>
2022-08-25clk: sunxi-ng: d1: Limit PLL rates to stable rangesSamuel Holland1-0/+8
Set the min/max rates for audio and video PLLs to keep them from going outside their documented stable ranges. Use the most restrictive of the "stable" and "actual" frequencies listed in the manual. Signed-off-by: Samuel Holland <[email protected]> Acked-by: Jernej Skrabec <[email protected]> Signed-off-by: Jernej Skrabec <[email protected]> Link: https://lore.kernel.org/r/[email protected]
2022-08-23clk: do not initialize retClaudiu Beznea1-1/+1
There is no need to initialize ret. Signed-off-by: Claudiu Beznea <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Stephen Boyd <[email protected]>
2022-08-23clk: remove extra empty lineClaudiu Beznea1-1/+0
Remove extra empty line. Signed-off-by: Claudiu Beznea <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Stephen Boyd <[email protected]>
2022-08-23clk: bcm: rpi: Show clock id limit in error caseStefan Wahren1-1/+2
The clock id limit will be extended in the future, so it would be helpful to see the actual clock id limit in case the firmware response has been rejected. Signed-off-by: Stefan Wahren <[email protected]> Link: https://lore.kernel.org/r/[email protected] Acked-by: Florian Fainelli <[email protected]> Reviewed-by: Ivan T. Ivanov <[email protected]> Signed-off-by: Stephen Boyd <[email protected]>
2022-08-23clk: bcm: rpi: Add missing newlineStefan Wahren1-3/+3
Some log messages lacks the final newline. So add them. Fixes: 93d2725affd6 ("clk: bcm: rpi: Discover the firmware clocks") Signed-off-by: Stefan Wahren <[email protected]> Link: https://lore.kernel.org/r/[email protected] Acked-by: Florian Fainelli <[email protected]> Reviewed-by: Ivan T. Ivanov <[email protected]> Signed-off-by: Stephen Boyd <[email protected]>
2022-08-23clk: bcm: rpi: Prevent out-of-bounds accessStefan Wahren1-1/+6
The while loop in raspberrypi_discover_clocks() relies on the assumption that the id of the last clock element is zero. Because this data comes from the Videocore firmware and it doesn't guarantuee such a behavior this could lead to out-of-bounds access. So fix this by providing a sentinel element. Fixes: 93d2725affd6 ("clk: bcm: rpi: Discover the firmware clocks") Link: https://github.com/raspberrypi/firmware/issues/1688 Suggested-by: Phil Elwell <[email protected]> Signed-off-by: Stefan Wahren <[email protected]> Link: https://lore.kernel.org/r/[email protected] Acked-by: Florian Fainelli <[email protected]> Reviewed-by: Ivan T. Ivanov <[email protected]> Signed-off-by: Stephen Boyd <[email protected]>
2022-08-23clk: samsung: exynos850: Implement CMU_MFCMSCL domainSam Protsenko1-0/+176
CMU_MFCMSCL clock domain provides clocks for MFC (Multi-Format Codec), JPEG Codec and Scaler IP-cores. According to Exynos850 TRM, CMU_MFCMSCL generates MFC, M2M, MCSC and JPEG clocks for BLK_MFCMSCL. This patch adds next clocks: - bus clocks in CMU_TOP for CMU_MFCMSCL - all internal CMU_MFCMSCL clocks - leaf clocks for MFCMSCL, TZPC (TrustZone Protection Controller), JPEG codec, M2M (Memory-to-Memory), MCSC (Multi-Channel Scaler), MFC (Multi-Format Codec), PPMU (Platform Performance Monitoring Unit), SysMMU and SysReg MFCMSCL related gate clocks in CMU_TOP were marked as CLK_IS_CRITICAL, because: 1. All of those have to be enabled in order to read /sys/kernel/debug/clk/clk_summary file 2. When some user driver (e.g. exynos-sysmmu) disables some derived leaf clock, it can lead to CMU_TOP clocks disable, which then makes the system hang. To prevent that, the CLK_IS_CRITICAL flag is used, as CLK_IGNORE_UNUSED is not enough. Signed-off-by: Sam Protsenko <[email protected]> Acked-by: Chanwoo Choi <[email protected]> Signed-off-by: Krzysztof Kozlowski <[email protected]> Link: https://lore.kernel.org/r/[email protected]
2022-08-23clk: samsung: exynos850: Implement CMU_IS domainSam Protsenko1-0/+199
CMU_IS clock domain provides clocks for IS IP-core (Image Signal Processing Subsystem). According to Exynos850 TRM, CMU_IS generates CSIS, IPP, ITP, VRA and GDC clocks for BLK_IS. This patch adds next clocks: - bus clocks in CMU_TOP needed for CMU_IS - all internal CMU_IS clocks - leaf clocks for IS IP-core, CSIS (Camera Serial Interface Slave), D_TZPC (TrustZone Protection Controller), CSIS DMA, GDC (Geometric Distortion Correction), IPP (Image Preprocessing Processing core), ITP (Image Texture Processing core), MCSC (Multi-Channel Scaler), VRA (Visual Recognition Accelerator), PPMU (Platform Performance Monitoring Unit), SysMMU and SysReg IS related gate clocks in CMU_TOP were marked as CLK_IS_CRITICAL, because: 1. All of those have to be enabled in order to read /sys/kernel/debug/clk/clk_summary file 2. When some user driver (e.g. exynos-sysmmu) disables some derived leaf clock, it can lead to CMU_TOP clocks disable, which then makes the system hang. To prevent that, the CLK_IS_CRITICAL flag is used, as CLK_IGNORE_UNUSED is not enough. Signed-off-by: Sam Protsenko <[email protected]> Acked-by: Chanwoo Choi <[email protected]> Signed-off-by: Krzysztof Kozlowski <[email protected]> Link: https://lore.kernel.org/r/[email protected]
2022-08-23clk: samsung: exynos850: Implement CMU_AUD domainSam Protsenko1-0/+302
CMU_AUD clock domain provides clocks for ABOX IP-core (audio subsystem). According to Exynos850 TRM, CMU_AUD generates Cortex-A32 clock, bus clock and audio clocks for BLK_AUD. This patch adds next clocks: - bus clocks in CMU_TOP needed for CMU_AUD - all internal CMU_AUD clocks - leaf clocks for Cortex-A32, Speedy FM, UAIF0..UAIF6 (Unified Audio Interface), CNT (counter), ABOX IP-core, ASB (Asynchronous Bridge), DAP (Debug Access Port), I2S Codec MCLK, D_TZPC (TrustZone Protection Controller), GPIO, PPMU (Platform Performance Monitoring Unit), SysMMU, SysReg and WDT ABOX clock was marked as CLK_IGNORE_UNUSED, as system hangs on boot otherwise. Once ABOX driver is implemented, maybe it can be handled there instead. Signed-off-by: Sam Protsenko <[email protected]> Acked-by: Chanwoo Choi <[email protected]> Reviewed-by: Krzysztof Kozlowski <[email protected]> Signed-off-by: Krzysztof Kozlowski <[email protected]> Link: https://lore.kernel.org/r/[email protected]
2022-08-23clk: samsung: exynos850: Style fixesSam Protsenko1-3/+2
Fix some typos in comments and do small coding style improvements. Signed-off-by: Sam Protsenko <[email protected]> Acked-by: Chanwoo Choi <[email protected]> Reviewed-by: Krzysztof Kozlowski <[email protected]> Signed-off-by: Krzysztof Kozlowski <[email protected]> Link: https://lore.kernel.org/r/[email protected]
2022-08-23clk: samsung: exynosautov9: add fsys1 clock supportChanho Park1-0/+130
CMU_FSYS1 provides clocks for USB(2 x USB3.1 Gen-1, 2 x USB 2.0) and mmc. For MMC clocks, PLL_MMC(PLL0831X type) is also supported as a PLL source clock provider. Signed-off-by: Chanho Park <[email protected]> Acked-by: Chanwoo Choi <[email protected]> Acked-by: Krzysztof Kozlowski <[email protected]> Signed-off-by: Krzysztof Kozlowski <[email protected]> Link: https://lore.kernel.org/r/d4aa967538fed9667e9550a256e545026fc2fa8d.1659054220.git.chanho61.park@samsung.com
2022-08-23clk: samsung: exynosautov9: add fsys0 clock supportChanho Park1-0/+243
CMU_FSYS0 block provides clocks for PCIe Gen3 1 x 4Lanes and 2 x 2 Lanes. Signed-off-by: Chanho Park <[email protected]> Acked-by: Chanwoo Choi <[email protected]> Acked-by: Krzysztof Kozlowski <[email protected]> Signed-off-by: Krzysztof Kozlowski <[email protected]> Link: https://lore.kernel.org/r/ae84d4a0487a5299076bfeef5732579f5207acf9.1659054220.git.chanho61.park@samsung.com
2022-08-23clk: samsung: exynosautov9: correct register offsets of peric0/c1Chanho Park1-10/+10
Some register offsets of peric0 and peric1 cmu blocks need to be corrected and re-ordered by numerical order. Fixes: f2dd366992d0 ("clk: samsung: exynosautov9: add cmu_peric0 clock support") Fixes: b35f27fe73d8 ("clk: samsung: exynosautov9: add cmu_peric1 clock support") Signed-off-by: Chanho Park <[email protected]> Reviewed-by: Krzysztof Kozlowski <[email protected]> Acked-by: Chanwoo Choi <[email protected]> Signed-off-by: Krzysztof Kozlowski <[email protected]> Link: https://lore.kernel.org/r/[email protected]
2022-08-23clk: samsung: exynosautov9: add missing gate clks for peric0/c1Chanho Park1-0/+8
"gout_peric0_pclk_1" and "gout_peric1_pclk_1" should be added to peric0 and peric1 respectively. Signed-off-by: Chanho Park <[email protected]> Reviewed-by: Krzysztof Kozlowski <[email protected]> Acked-by: Chanwoo Choi <[email protected]> Signed-off-by: Krzysztof Kozlowski <[email protected]> Link: https://lore.kernel.org/r/[email protected]
2022-08-23clk: samsung: exynos7885: Add TREX clocksDavid Virag1-7/+42
TREX D Core and P core clocks seem to be related to the BTS (Bus Traffic Shaper) inside the Exynos7885 SoC, and are needed for the SoC to function correctly. When clocks are cut from TREX D Core, the eMMC and the framebuffer stops working properly. Other unknown things may stop working as well. When clocks are cut from TREX P Core, the system locks up needing a hard reset. Add these clocks and mark them critical so that they are always on. Signed-off-by: David Virag <[email protected]> Reviewed-by: Krzysztof Kozlowski <[email protected]> Signed-off-by: Krzysztof Kozlowski <[email protected]> Link: https://lore.kernel.org/r/[email protected]
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