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2022-09-27clk: qcom: gdsc: Fix the handling of PWRSTS_RET supportRajendra Nayak2-0/+15
GDSCs cannot be transitioned into a Retention state in SW. When either the RETAIN_MEM bit, or both the RETAIN_MEM and RETAIN_PERIPH bits are set, and the GDSC is left ON, the HW takes care of retaining the memory/logic for the domain when the parent domain transitions to power collapse/power off state. On some platforms where the parent domains lowest power state itself is Retention, just leaving the GDSC in ON (without any RETAIN_MEM/RETAIN_PERIPH bits being set) will also transition it to Retention. The existing logic handling the PWRSTS_RET seems to set the RETAIN_MEM/RETAIN_PERIPH bits if the cxcs offsets are specified but then explicitly turns the GDSC OFF as part of _gdsc_disable(). Fix that by leaving the GDSC in ON state. Signed-off-by: Rajendra Nayak <[email protected]> Cc: AngeloGioacchino Del Regno <[email protected]> Signed-off-by: Bjorn Andersson <[email protected]> Link: https://lore.kernel.org/r/[email protected]
2022-09-27clk: qcom: Add SC8280XP GPU clock controllerBjorn Andersson3-0/+470
Add driver for the GPU clock controller in the Qualcomm SC8280XP platform. Signed-off-by: Bjorn Andersson <[email protected]> Reviewed-by: Konrad Dybcio <[email protected]> [bjorn: Included kernel.h and lower-cased hex numbers] Signed-off-by: Bjorn Andersson <[email protected]> Signed-off-by: Bjorn Andersson <[email protected]> Link: https://lore.kernel.org/r/[email protected]
2022-09-27clk: qcom: smd: Add SM6375 clocksKonrad Dybcio1-2/+44
Add support for controlling SMD RPM clocks on SM6375. Signed-off-by: Konrad Dybcio <[email protected]> Signed-off-by: Bjorn Andersson <[email protected]> Link: https://lore.kernel.org/r/[email protected]
2022-09-27clk: qcom: rpmhcc: add sdm670 clocksRichard Acayan1-0/+21
The Snapdragon 670 uses the RPMh mailbox for most of the clocks used in SDM845 but omits two. Add clock data for SDM670 so the driver doesn't fail to resolve a clock. Link: https://android.googlesource.com/kernel/msm/+/443bd8d6e2cf54698234c752e6de97b4b8a528bd%5E%21/#F7 Signed-off-by: Richard Acayan <[email protected]> Reviewed-by: Neil Armstrong <[email protected]> Signed-off-by: Bjorn Andersson <[email protected]> Link: https://lore.kernel.org/r/[email protected]
2022-09-26clk: qcom: Merge alt alpha plls for qcm2260, sm6115Iskren Chernev4-82/+57
The qcom2260 and sm6115 GCC drivers use a common modified DEFAULT and BRAMMO alpha pll offsets. Move these common offsets to the shared place to avoid duplication. The new layouts have a suffix EVO similar to LUCID and RIVIAN. Signed-off-by: Iskren Chernev <[email protected]> Signed-off-by: Bjorn Andersson <[email protected]> Link: https://lore.kernel.org/r/[email protected]
2022-09-26clk: qcom: gcc-sm6115: Move alpha pll bramo overridesIskren Chernev1-14/+12
sm6115 uses a modified default and bramo alpha pll offsets. Put them in the same place for consistency. Signed-off-by: Iskren Chernev <[email protected]> Signed-off-by: Bjorn Andersson <[email protected]> Link: https://lore.kernel.org/r/[email protected]
2022-09-26clk: qcom: gcc-sm6115: Override default Alpha PLL regsAdam Skladowski1-16/+30
The DEFAULT and BRAMMO PLL offsets are non-standard in downstream, but currently only BRAMMO ones are overridden. Override DEFAULT ones too. A very similar thing is happening in gcc-qcm2290 driver. Fixes: cbe63bfdc54f ("clk: qcom: Add Global Clock controller (GCC) driver for SM6115") Signed-off-by: Adam Skladowski <[email protected]> Signed-off-by: Iskren Chernev <[email protected]> Signed-off-by: Bjorn Andersson <[email protected]> Link: https://lore.kernel.org/r/[email protected]
2022-09-26clk: qcom: Add support for Display Clock Controller on SM8450Dmitry Baryshkov3-0/+1839
Add support for the dispcc on Qualcomm SM8450 platform. Signed-off-by: Dmitry Baryshkov <[email protected]> Signed-off-by: Bjorn Andersson <[email protected]> Link: https://lore.kernel.org/r/[email protected]
2022-09-26clk: qcom: alpha-pll: add support for power off mode for lucid evo PLLDmitry Baryshkov2-3/+38
PLLs can be kept in standby (default configuration) or in off mode when disabled during power collapse. Hence add support for pll disable off mode for lucid evo PLL. Signed-off-by: Dmitry Baryshkov <[email protected]> Signed-off-by: Bjorn Andersson <[email protected]> Link: https://lore.kernel.org/r/[email protected]
2022-09-26clk: qcom: Add display clock controller driver for SM6115Adam Skladowski3-0/+618
Add support for the display clock controller found in SM6115/SM4250 based devices. This clock controller feeds the Multimedia Display SubSystem (MDSS). This driver is based upon one submitted for QCM2290. Signed-off-by: Adam Skladowski <[email protected]> Signed-off-by: Bjorn Andersson <[email protected]> Link: https://lore.kernel.org/r/[email protected]
2022-09-26clk: qcom: gcc-sc7280: Update the .pwrsts for PCIe GDSCKrishna chaitanya chundru1-1/+1
Enabling PCIe GDSC retention to ensure controller and its dependent clocks won't go down during system suspend. Update the .pwrsts for PCIe GDSC so it only transitions to RET in low power. Signed-off-by: Krishna chaitanya chundru <[email protected]> Signed-off-by: Bjorn Andersson <[email protected]> Link: https://lore.kernel.org/r/[email protected]
2022-09-26clk: qcom: lpass: Fix lpass audiocc probeSatya Priya1-1/+1
Change the qcom_cc_probe_by_index() call to qcom_cc_really_probe() to avoid remapping of memory region for index 0, which is already being done through qcom_cc_map(). Fixes: 7c6a6641c2 ("clk: qcom: lpass: Add support for resets & external mclk for SC7280") Signed-off-by: Satya Priya <[email protected]> Reviewed-by: Neil Armstrong <[email protected]> Signed-off-by: Bjorn Andersson <[email protected]> Link: https://lore.kernel.org/r/[email protected]
2022-09-26clk: qcom: apss-ipq-pll: add support for IPQ8074Robert Marko1-0/+13
Add support for IPQ8074 since it uses the same PLL setup, however it uses slightly different Alpha PLL config. Alpha PLL config was obtained by dumping PLL registers from a running device. Signed-off-by: Robert Marko <[email protected]> Signed-off-by: Bjorn Andersson <[email protected]> Link: https://lore.kernel.org/r/[email protected]
2022-09-26clk: qcom: apss-ipq-pll: update IPQ6018 Alpha PLL configRobert Marko1-2/+6
Update the IPQ6018 Alpha PLL config to the latest one from the downstream 5.4 kernel[1]. This one should match the production SoC-s. Tested on IPQ6018 CP01-C1 reference board. [1] https://git.codelinaro.org/clo/qsdk/oss/kernel/linux-ipq-5.4/-/blob/NHSS.QSDK.12.1.r4/drivers/clk/qcom/apss-ipq-pll.c#L41 Signed-off-by: Robert Marko <[email protected]> Signed-off-by: Bjorn Andersson <[email protected]> Link: https://lore.kernel.org/r/[email protected]
2022-09-26clk: qcom: apss-ipq-pll: use OF match data for Alpha PLL configRobert Marko1-3/+9
Convert the driver to use OF match data for providing the Alpha PLL config per compatible. This is required for IPQ8074 support since it uses a different Alpha PLL config. While we are here rename "ipq_pll_config" to "ipq6018_pll_config" to make it clear that it is for IPQ6018 only. Signed-off-by: Robert Marko <[email protected]> Signed-off-by: Bjorn Andersson <[email protected]> Link: https://lore.kernel.org/r/[email protected]
2022-09-26clk: qcom: apss-ipq6018: mark apcs_alias0_core_clk as criticalRobert Marko1-1/+1
While fixing up the driver I noticed that my IPQ8074 board was hanging after CPUFreq switched the frequency during boot, WDT would eventually reset it. So mark apcs_alias0_core_clk as critical since its the clock feeding the CPU cluster and must never be disabled. Fixes: 5e77b4ef1b19 ("clk: qcom: Add ipq6018 apss clock controller") Signed-off-by: Robert Marko <[email protected]> Reviewed-by: Dmitry Baryshkov <[email protected]> Signed-off-by: Bjorn Andersson <[email protected]> Link: https://lore.kernel.org/r/[email protected]
2022-09-26clk: qcom: apss-ipq6018: fix apcs_alias0_clk_srcRobert Marko1-7/+6
While working on IPQ8074 APSS driver it was discovered that IPQ6018 and IPQ8074 use almost the same PLL and APSS clocks, however APSS driver is currently broken. More precisely apcs_alias0_clk_src is broken, it was added as regmap_mux clock. However after debugging why it was always stuck at 800Mhz, it was figured out that its not regmap_mux compatible at all. It is a simple mux but it uses RCG2 register layout and control bits, so utilize the new clk_rcg2_mux_closest_ops to correctly drive it while not having to provide a dummy frequency table. While we are here, use ARRAY_SIZE for number of parents. Tested on IPQ6018-CP01-C1 reference board and multiple IPQ8074 boards. Fixes: 5e77b4ef1b19 ("clk: qcom: Add ipq6018 apss clock controller") Signed-off-by: Robert Marko <[email protected]> Reviewed-by: Dmitry Baryshkov <[email protected]> Signed-off-by: Bjorn Andersson <[email protected]> Link: https://lore.kernel.org/r/[email protected]
2022-09-26clk: qcom: clk-rcg2: add rcg2 mux opsChristian Marangi2-0/+8
An RCG may act as a mux that switch between 2 parents. This is the case on IPQ6018 and IPQ8074 where the APCS core clk that feeds the CPU cluster clock just switches between XO and the PLL that feeds it. Add the required ops to add support for this special configuration and use the generic mux function to determine the rate. This way we dont have to keep a essentially dummy frequency table to use RCG2 as a mux. Signed-off-by: Christian Marangi <[email protected]> Signed-off-by: Robert Marko <[email protected]> Reviewed-by: Dmitry Baryshkov <[email protected]> Signed-off-by: Bjorn Andersson <[email protected]> Link: https://lore.kernel.org/r/[email protected]
2022-09-26clk: qcom: lcc-ipq806x: use ARRAY_SIZE for num_parentsChristian Marangi1-4/+4
Use ARRAY_SIZE for num_parents instead of raw number to prevent any confusion/mistake. Signed-off-by: Christian Marangi <[email protected]> Reviewed-by: Dmitry Baryshkov <[email protected]> Signed-off-by: Bjorn Andersson <[email protected]> Link: https://lore.kernel.org/r/[email protected]
2022-09-26clk: qcom: lcc-ipq806x: convert to parent dataChristian Marangi1-31/+38
Convert lcc-ipq806x driver to parent_data API. Change parent_name for pll4 to pxo_board to prepare the future to eventually drop the double pxo board clk. Signed-off-by: Christian Marangi <[email protected]> Reviewed-by: Dmitry Baryshkov <[email protected]> Signed-off-by: Bjorn Andersson <[email protected]> Link: https://lore.kernel.org/r/[email protected]
2022-09-26clk: qcom: lcc-ipq806x: add reset definitionChristian Marangi1-0/+7
Add reset definition for lcc-ipq806x. Signed-off-by: Christian Marangi <[email protected]> Reviewed-by: Dmitry Baryshkov <[email protected]> Signed-off-by: Bjorn Andersson <[email protected]> Link: https://lore.kernel.org/r/[email protected]
2022-09-26clk: qcom: cpu-8996: use constant mask for pmuxDmitry Baryshkov1-13/+6
Both pmux instances share the same width and shift. Specify the mask at compile time to simplify functions. Signed-off-by: Dmitry Baryshkov <[email protected]> Signed-off-by: Bjorn Andersson <[email protected]> Link: https://lore.kernel.org/r/[email protected]
2022-09-26clk: qcom: cpu-8996: don't store parents in clk_cpu_8996_pmuxDmitry Baryshkov1-13/+9
Don't store pointers to parents in struct clk_cpu_8996_pmux. Instead use clk_hw_get_parent_by_index to fetch them. Signed-off-by: Dmitry Baryshkov <[email protected]> Signed-off-by: Bjorn Andersson <[email protected]> Link: https://lore.kernel.org/r/[email protected]
2022-09-26clk: qcom: cpu-8996: move ACD logic to clk_cpu_8996_pmux_determine_rateDmitry Baryshkov1-5/+2
Rather than telling everybody that we are using PLL as a parent (and using ACD clock instead) properly select ACD as a pmux parent clock. Signed-off-by: Dmitry Baryshkov <[email protected]> Signed-off-by: Bjorn Andersson <[email protected]> Link: https://lore.kernel.org/r/[email protected]
2022-09-26clk: qcom: cpu-8996: declare ACD clocksDmitry Baryshkov1-12/+41
To simplify the code, define 1:1 fixed factor clocks to represent the ACD pmux parent. Signed-off-by: Dmitry Baryshkov <[email protected]> Signed-off-by: Bjorn Andersson <[email protected]> Link: https://lore.kernel.org/r/[email protected]
2022-09-26clk: qcom: cpu-8996: switch to devm_clk_notifier_registerDmitry Baryshkov1-23/+2
Switch to using devres-managed version of clk_notifier_register(). This allows us to drop driver's remove() callback. Signed-off-by: Dmitry Baryshkov <[email protected]> Signed-off-by: Bjorn Andersson <[email protected]> Link: https://lore.kernel.org/r/[email protected]
2022-09-26clk: qcom: msm8996-cpu: Use parent_data/_hws for all clocksYassine Oudjana1-32/+47
Replace parent_names in PLLs, secondary muxes and primary muxes with parent_data. For primary muxes there were never any *cl_pll_acd clocks, so instead of adding them, put the primary PLLs in both PLL_INDEX and ACD_INDEX, then make sure ACD_INDEX is always picked over PLL_INDEX when setting parent since we always want ACD when using the primary PLLs. Signed-off-by: Yassine Oudjana <[email protected]> [DB: switch to parent_hws for pmux clocks] Signed-off-by: Dmitry Baryshkov <[email protected]> Signed-off-by: Bjorn Andersson <[email protected]> Link: https://lore.kernel.org/r/[email protected]
2022-09-26clk: qcom: msm8996-cpu: Convert secondary muxes to clk_regmap_muxYassine Oudjana1-32/+30
There is nothing special about the secondary muxes, unlike the primary muxes which need some extra logic to handle ACD and switching between primary PLL and secondary mux sources. Turn them into clk_regmap_mux and rename cpu_clk_msm8996_mux into cpu_clk_msm8996_pmux to make it specific to primary muxes. Signed-off-by: Yassine Oudjana <[email protected]> Reviewed-by: Dmitry Baryshkov <[email protected]> Signed-off-by: Bjorn Andersson <[email protected]> Link: https://lore.kernel.org/r/[email protected]
2022-09-26clk: qcom: msm8996-cpu: Unify cluster orderYassine Oudjana1-18/+18
The power cluster comes before the performance cluster. Make everything in the driver follow this order. Signed-off-by: Yassine Oudjana <[email protected]> Reviewed-by: Dmitry Baryshkov <[email protected]> Signed-off-by: Bjorn Andersson <[email protected]> Link: https://lore.kernel.org/r/[email protected]
2022-09-26clk: qcom: msm8996-cpu: Statically define PLL dividersYassine Oudjana1-24/+42
This will allow for adding them to clk_parent_data arrays in an upcoming patch. Signed-off-by: Yassine Oudjana <[email protected]> Reviewed-by: Dmitry Baryshkov <[email protected]> Signed-off-by: Bjorn Andersson <[email protected]> Link: https://lore.kernel.org/r/[email protected]
2022-09-26clk: qcom: msm8996-cpu: Rename DIV_2_INDEX to SMUX_INDEXYassine Oudjana1-2/+2
The parent at this index is the secondary mux, which can connect not only to primary PLL/2 but also to XO. Rename the index to SMUX_INDEX to better reflect the parent. Signed-off-by: Yassine Oudjana <[email protected]> Reviewed-by: Dmitry Baryshkov <[email protected]> Signed-off-by: Bjorn Andersson <[email protected]> Link: https://lore.kernel.org/r/[email protected]
2022-09-26clk: mediatek: Use mtk_clk_register_gates_with_dev in simple probeYassine Oudjana1-1/+2
Register gates with dev in mtk_clk_simple_probe. Signed-off-by: Yassine Oudjana <[email protected]> Reviewed-by: Chen-Yu Tsai <[email protected]> Reviewed-by: AngeloGioacchino Del Regno <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Chen-Yu Tsai <[email protected]>
2022-09-26clk: mediatek: gate: Export mtk_clk_register_gates_with_devYassine Oudjana1-0/+1
This allows it to be used in drivers built as modules. Signed-off-by: Yassine Oudjana <[email protected]> Reviewed-by: Chen-Yu Tsai <[email protected]> Reviewed-by: AngeloGioacchino Del Regno <[email protected]> Reviewed-by: Markus Schneider-Pargmann <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Chen-Yu Tsai <[email protected]>
2022-09-26clk: mediatek: add VDOSYS1 clockPablo Sun1-0/+11
Add the clock gate definition for the DPI1 hardware in VDOSYS1. The parent clock "hdmi_txpll" is already defined in `mt8195.dtsi`. Signed-off-by: Pablo Sun <[email protected]> Signed-off-by: Guillaume Ranquet <[email protected]> Reviewed-by: Chen-Yu Tsai <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Chen-Yu Tsai <[email protected]>
2022-09-26clk: mediatek: mt8192: add mtk_clk_simple_removeMiles Chen10-0/+10
mt8192 is already using mtk_clk_simple_probe, but not mtk_clk_simple_remove. Let's add mtk_clk_simple_remove for mt8192. Signed-off-by: Miles Chen <[email protected]> Reviewed-by: Chen-Yu Tsai <[email protected]> Reviewed-by: AngeloGioacchino Del Regno <[email protected]> Tested-by: AngeloGioacchino Del Regno <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Chen-Yu Tsai <[email protected]>
2022-09-26clk: mediatek: mt8183: use mtk_clk_simple_probe to simplify driverMiles Chen9-137/+108
mtk_clk_simple_probe was added by Chun-Jie to simply common flow of MediaTek clock drivers and ChenYu enhanced the error path of mtk_clk_simple_probe and added mtk_clk_simple_remove. Let's use mtk_clk_simple_probe and mtk_clk_simple_probe in other MediaTek clock drivers as well. Signed-off-by: Miles Chen <[email protected]> Reviewed-by: AngeloGioacchino Del Regno <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Chen-Yu Tsai <[email protected]>
2022-09-26clk: mediatek: mt6797: use mtk_clk_simple_probe to simplify driverMiles Chen3-69/+39
mtk_clk_simple_probe was added by Chun-Jie to simply common flow of MediaTek clock drivers and ChenYu enhanced the error path of mtk_clk_simple_probe and added mtk_clk_simple_remove. Let's use mtk_clk_simple_probe and mtk_clk_simple_probe in other MediaTek clock drivers as well. Signed-off-by: Miles Chen <[email protected]> Reviewed-by: AngeloGioacchino Del Regno <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Chen-Yu Tsai <[email protected]>
2022-09-26clk: mediatek: mt6779: use mtk_clk_simple_probe to simplify driverMiles Chen7-111/+90
mtk_clk_simple_probe was added by Chun-Jie to simply common flow of MediaTek clock drivers and ChenYu enhanced the error path of mtk_clk_simple_probe and added mtk_clk_simple_remove. Let's use mtk_clk_simple_probe and mtk_clk_simple_probe in other MediaTek clock drivers as well. Signed-off-by: Miles Chen <[email protected]> Reviewed-by: AngeloGioacchino Del Regno <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Chen-Yu Tsai <[email protected]>
2022-09-26clk: mediatek: mt6765: use mtk_clk_simple_probe to simplify driverMiles Chen6-129/+72
mtk_clk_simple_probe was added by Chun-Jie to simply common flow of MediaTek clock drivers and ChenYu enhanced the error path of mtk_clk_simple_probe and added mtk_clk_simple_remove. Let's use mtk_clk_simple_probe and mtk_clk_simple_probe in other MediaTek clock drivers as well. Signed-off-by: Miles Chen <[email protected]> Reviewed-by: AngeloGioacchino Del Regno <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Chen-Yu Tsai <[email protected]>
2022-09-26clk: mediatek: mt2712: use mtk_clk_simple_probe to simplify driverMiles Chen6-132/+72
mtk_clk_simple_probe was added by Chun-Jie to simply common flow of MediaTek clock drivers and ChenYu enhanced the error path of mtk_clk_simple_probe and added mtk_clk_simple_remove. Let's use mtk_clk_simple_probe and mtk_clk_simple_probe in other MediaTek clock drivers as well. Signed-off-by: Miles Chen <[email protected]> Reviewed-by: AngeloGioacchino Del Regno <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Chen-Yu Tsai <[email protected]>
2022-09-26clk: mediatek: mt2701: use mtk_clk_simple_probe to simplify driverMiles Chen3-69/+39
mtk_clk_simple_probe was added by Chun-Jie to simply common flow of MediaTek clock drivers and ChenYu enhanced the error path of mtk_clk_simple_probe and added mtk_clk_simple_remove. Let's use mtk_clk_simple_probe and mtk_clk_simple_probe in other MediaTek clock drivers as well. Signed-off-by: Miles Chen <[email protected]> Reviewed-by: AngeloGioacchino Del Regno <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Chen-Yu Tsai <[email protected]>
2022-09-26clk: mediatek: Add MediaTek Helio X10 MT6795 clock driversAngeloGioacchino Del Regno10-0/+1408
Add the clock drivers for the entire clock tree of MediaTek Helio X10 MT6795, including system clocks (apmixedsys, infracfg, pericfg, topckgen) and multimedia clocks (mmsys, mfg, vdecsys, vencsys). Signed-off-by: AngeloGioacchino Del Regno <[email protected]> Reviewed-by: Matthias Brugger <[email protected]> Reviewed-by: Miles Chen <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Chen-Yu Tsai <[email protected]>
2022-09-26clk: mediatek: clk-apmixed: Add helper function to unregister ref2usb_txAngeloGioacchino Del Regno2-0/+10
The ref2usb_tx clock was introduced a long time ago and, at that time, the MediaTek clock drivers were using CLK_OF_DECLARE, so they would never unregister. Nowadays, unregistering clock drivers is a thing, as we're registering them as platform_driver and allowing them to be kernel modules: add a helper function to cleanup the ref2usb_tx clock during error handling and upon module removal. Signed-off-by: AngeloGioacchino Del Regno <[email protected]> Reviewed-by: Chen-Yu Tsai <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Chen-Yu Tsai <[email protected]>
2022-09-26clk: mediatek: Export required symbols to compile clk drivers as moduleAngeloGioacchino Del Regno4-0/+6
In order to compile the clock drivers for various MediaTek SoCs as modules, it is necessary to export a few functions from the MediaTek specific clocks (and reset) libraries. Signed-off-by: AngeloGioacchino Del Regno <[email protected]> Reviewed-by: Miles Chen <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Chen-Yu Tsai <[email protected]>
2022-09-26clk: mediatek: clk-apmixed: Remove unneeded __init annotationAngeloGioacchino Del Regno1-1/+1
Remove an unneeded __init annotation from the declaration of function mtk_clk_register_ref2usb_tx(): this avoids section mismatch warnings during modpost phase when called from functions that have no such annotation (useful when clocks are platform drivers). Signed-off-by: AngeloGioacchino Del Regno <[email protected]> Reviewed-by: Miles Chen <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Chen-Yu Tsai <[email protected]>
2022-09-24platform/x86: int3472: Support multiple clock consumersDaniel Scally1-4/+9
At present, the tps68470.c only supports a single clock consumer when passing platform data to the clock driver. In some devices multiple sensors depend on the clock provided by a single TPS68470 and so all need to be able to acquire the clock. Support passing multiple consumers as platform data. Reviewed-by: Hans de Goede <[email protected]> Signed-off-by: Daniel Scally <[email protected]> Reviewed-by: Stephen Boyd <[email protected]> Acked-by: Stephen Boyd <[email protected]> Signed-off-by: Rafael J. Wysocki <[email protected]>
2022-09-23clk: rockchip: Add clock controller support for RV1126 SoCJagan Teki4-0/+1165
Clock & Reset Unit (CRU) in RV1126 support clocks for CRU and CRU_PMU blocks. This patch is trying to add minimal Clock-Architecture Diagram's inferred from [1] authored by Finley Xiao. [1] https://github.com/rockchip-linux/kernel/blob/develop-4.19/drivers/clk/rockchip/clk-rv1126.c Cc: [email protected] Cc: Michael Turquette <[email protected]> Cc: Stephen Boyd <[email protected]> Signed-off-by: Finley Xiao <[email protected]> Signed-off-by: Jagan Teki <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Heiko Stuebner <[email protected]>
2022-09-19clk: imx93: add SAI IPG clkPeng Fan1-3/+9
The clk topology is as below: bus_aon_root------>\ /--->SAI IPG -->SAI LPCG gate--> sai[x]_clk_root--->/ \--->SAI MCLK So use shared count as i.MX93 MU_B gate. Signed-off-by: Peng Fan <[email protected]> Reviewed-by: Abel Vesa <[email protected]> Signed-off-by: Abel Vesa <[email protected]> Link: https://lore.kernel.org/r/[email protected]
2022-09-19clk: imx93: add MU1/2 clockPeng Fan1-2/+6
The clk tree should be as: bus_aon_root------>\ /--->MU1_B IP -->MU_B gate--> bus_wakeup_root--->/ \--->MU2_B IP bus_aon_root------>\ /--->MU1_A IP -->MU_A gate--> bus_wakeup_root--->/ \--->MU2_A IP So need use shared count gate. And linux use MU_B, so set MU_A clk as CLK_IGNORE_UNUSED. Signed-off-by: Peng Fan <[email protected]> Reviewed-by: Ye Li <[email protected]> Reviewed-by: Jacky Bai <[email protected]> Reviewed-by: Abel Vesa <[email protected]> Signed-off-by: Abel Vesa <[email protected]> Link: https://lore.kernel.org/r/[email protected]
2022-09-19clk: imx93: switch to use new clk gate APIPeng Fan1-4/+4
Use i.MX93 specific clk gate API Signed-off-by: Peng Fan <[email protected]> Reviewed-by: Ye Li <[email protected]> Reviewed-by: Jacky Bai <[email protected]> Signed-off-by: Abel Vesa <[email protected]> Link: https://lore.kernel.org/r/[email protected]
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