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2022-11-22clk: fractional-divider: Split out clk_fd_get_div() helperAndy Shevchenko1-6/+16
Split out clk_fd_get_div() helper for the future use elsewhere. Signed-off-by: Andy Shevchenko <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Stephen Boyd <[email protected]>
2022-11-22clk: spear: Fix SSP clock definition on SPEAr600Kory Maincent1-3/+3
There is no SPEAr600 device named "ssp-pl022.x". Instead, the description of the SSP (Synchronous Serial Port) was recently added to the Device Tree, and the device name is "xxx.spi", so we should associate the SSP gateable clock to these device names. Signed-off-by: Kory Maincent <[email protected]> Acked-by: Viresh Kumar <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Stephen Boyd <[email protected]>
2022-11-22clk: spear: Fix CLCD clock definition on SPEAr600Kory Maincent1-1/+1
There is no SPEAr600 device named "clcd". Instead, the description of the CLCD (color liquid crystal display controller) name is "fc200000.clcd", so we should associate the CLCD gateable clock to this device name. Signed-off-by: Kory Maincent <[email protected]> Acked-by: Viresh Kumar <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Stephen Boyd <[email protected]>
2022-11-22clk: Remove a useless includeChristophe JAILLET3-3/+0
<linux/rational.h> is not needed for these drivers. Remove the corresponding #include. Signed-off-by: Christophe JAILLET <[email protected]> Link: https://lore.kernel.org/r/12dd5cb49efa7714f8e0389e4c7b3bc829e8a90e.1668289299.git.christophe.jaillet@wanadoo.fr Acked-by: Heiko Stuebner <[email protected]> Acked-by: Jerome Brunet <[email protected]> Reviewed-by: Luca Ceresoli <[email protected]> Signed-off-by: Stephen Boyd <[email protected]>
2022-11-22clk: ti: fix typo in ti_clk_retry_init() code commentDario Binacchi1-1/+1
Replace "not" with "node". Signed-off-by: Dario Binacchi <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Stephen Boyd <[email protected]>
2022-11-22clk: ti: dra7-atl: don't allocate `parent_names' variableDario Binacchi1-12/+2
The `parent_names' variable was freed also in case of kzalloc() error. Instead of modifying the code to perform a proper memory release, I decided to fix the bug by not allocating memory. Since only one parent name is referenced, it is not necessary to allocate this variable at runtime and therefore you can avoid calling the kzalloc() function. This simplifies the code (even calls to kfree can be removed) and improves the performance of the routine. Signed-off-by: Dario Binacchi <[email protected]> Reported-by: kernel test robot <[email protected]> Link: https://lore.kernel.org/r/[email protected] Tested-by: Tony Lindgren <[email protected]> Reviewed-by: Tony Lindgren <[email protected]> Signed-off-by: Stephen Boyd <[email protected]>
2022-11-22clk: ti: change ti_clk_register[_omap_hw]() APIDario Binacchi12-42/+41
The ti_clk_register() and ti_clk_register_omap_hw() functions are always called with the parameter of type "struct device" set to NULL, since the functions from which they are called always have a parameter of type "struct device_node". Replacing "struct device" type parameter with "struct device_node" will allow you to register a TI clock to the common clock framework by taking advantage of the facilities provided by the "struct device_node" type. Further, adding the "of_" prefix to the name of these functions explicitly binds them to the "struct device_node" type. The patch has been tested on a Beaglebone board. Signed-off-by: Dario Binacchi <[email protected]> Tested-by: Tony Lindgren <[email protected]> Reviewed-by: Tony Lindgren <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Stephen Boyd <[email protected]>
2022-11-22Merge tag 'clk-microchip-fixes-6.1' of ↵Stephen Boyd1-1/+1
https://git.kernel.org/pub/scm/linux/kernel/git/at91/linux into clk-fixes Pull Microchip clk driver fixes from Claudiu Beznea: - fix the clock ID for USB device port on AT91 RM9200 SoCs; along with it the device tree references to this clocks were fixed in this patch to ease the backporting and to avoid USB driver probe failure. * tag 'clk-microchip-fixes-6.1' of https://git.kernel.org/pub/scm/linux/kernel/git/at91/linux: ARM: at91: rm9200: fix usb device clock id
2022-11-22Merge tag 'samsung-clk-6.2' of ↵Stephen Boyd2-4/+6
https://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux into clk-fixes Pull Samsung SoC clk driver fixes from Krzysztof Kozlowski: - Fix calling of_device_get_match_data() on wrong device (parent's) in Exynos clock out driver - Correct clock name in bindings of ExynosAutov9 clocks - Correct parents of div4 clock on Exynos7885 * tag 'samsung-clk-6.2' of https://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux: clk: samsung: Revert "clk: samsung: exynos-clkout: Use of_device_get_match_data()" dt-bindings: clock: exynosautov9: fix reference to CMU_FSYS1 clk: samsung: exynos7885: Correct "div4" clock parents
2022-11-22clk: imx: imxrt1050: add IMXRT1050_CLK_LCDIF_PIX clock gateGiulio Benetti1-0/+1
Add IMXRT1050_CLK_LCDIF_PIX clock gate. Cc: Jesse Taube <[email protected]> Signed-off-by: Giulio Benetti <[email protected]> Acked-by: Jesse Taube <[email protected]> Reviewed-by: Abel Vesa <[email protected]> Signed-off-by: Abel Vesa <[email protected]> Link: https://lore.kernel.org/r/[email protected]
2022-11-22clk: imx: imxrt1050: fix IMXRT1050_CLK_LCDIF_APB offsetsGiulio Benetti1-1/+1
Fix IMXRT1050_CLK_LCDIF_APB offsets. Fixes: 7154b046d8f3 ("clk: imx: Add initial support for i.MXRT1050 clock driver") Cc: Jesse Taube <[email protected]> Signed-off-by: Giulio Benetti <[email protected]> Reviewed-by: Abel Vesa <[email protected]> Signed-off-by: Abel Vesa <[email protected]> Link: https://lore.kernel.org/r/[email protected]
2022-11-22clk: imx8mp: Add audio shared gateAbel Vesa1-1/+11
According to the RM, the CCGR101 is shared for the following root clocks: - AUDIO_AHB_CLK_ROOT - AUDIO_AXI_CLK_ROOT - SAI1_CLK_ROOT - SAI2_CLK_ROOT - SAI3_CLK_ROOT - SAI5_CLK_ROOT - SAI6_CLK_ROOT - SAI7_CLK_ROOT - PDM_CLK_ROOT IMX8MP_CLK_AUDIO_ROOT is same as AUDIO_AHB_CLK_ROOT which can avoid break any users. Signed-off-by: Abel Vesa <[email protected]> Signed-off-by: Shengjiu Wang <[email protected]> Reviewed-by: Peng Fan <[email protected]> Signed-off-by: Abel Vesa <[email protected]> Link: https://lore.kernel.org/r/[email protected]
2022-11-22clk: imx: pll14xx: Add 320 MHz and 640 MHz entries for PLL146xMarek Vasut1-0/+2
The PLL146x is used to implement SYS_PLL3 on i.MX8MP and can be used to drive UARTn_ROOT clock. By setting the PLL3 to 320 MHz or 640 MHz, the PLL3 output can be divided down to supply UARTn_ROOT clock with precise 64 MHz, which divided down further by 16x oversampling factor used by the i.MX UART core yields 4 Mbdps baud base for the UART IP. This is useful e.g. for BCM bluetooth chips, which can operate up to 4 Mbdps. Add 320 MHz and 640 MHz entries so the PLL can be configured accordingly. Signed-off-by: Marek Vasut <[email protected]> Reviewed-by: Abel Vesa <[email protected]> Signed-off-by: Abel Vesa <[email protected]> Link: https://lore.kernel.org/r/[email protected]
2022-11-22clk: imx93: keep sys ctr clock always onJacky Bai1-1/+2
Keep sys ctr clock always on to make sure its register can be accessed for cpuidle. Reviewed-by: Peng Fan <[email protected]> Signed-off-by: Jacky Bai <[email protected]> Signed-off-by: Peng Fan <[email protected]> Reviewed-by: Abel Vesa <[email protected]> Signed-off-by: Abel Vesa <[email protected]> Link: https://lore.kernel.org/r/[email protected]
2022-11-22clk: imx: keep hsio bus clock always onJacky Bai1-1/+5
During Linux System suspend/resume stress test after System Sleep enabled, system will stuck sometimes. It is because NICMIX is powered down, which HSIOMIX(always on) is not powered down. When NICMIX powering down, HSIOMIX will get a hardware handshake, without HSIO ROOT clk, the handshake will lose. Then after NICMIX power on when system resume, the access to HSIOMIX through NICMIX would be broken. So keep HSIO ROOT always on. Signed-off-by: Jacky Bai <[email protected]> Signed-off-by: Peng Fan <[email protected]> Reviewed-by: Abel Vesa <[email protected]> Signed-off-by: Abel Vesa <[email protected]> Link: https://lore.kernel.org/r/[email protected]
2022-11-21clk: imx93: drop tpm1/3, lpit1/2 clkPeng Fan1-8/+4
Per Reference Mannual System Clocks Table, LPIT1 and TPM1 sources from bus_aon_root LPIT2 and TPM3 sources from bus_wakeup_root So update driver to reflect that. Reviewed-by: Jacky Bai <[email protected]> Signed-off-by: Peng Fan <[email protected]> Reviewed-by: Abel Vesa <[email protected]> Signed-off-by: Abel Vesa <[email protected]> Link: https://lore.kernel.org/r/[email protected]
2022-11-21clk: imx93: correct enet clockPeng Fan1-1/+1
Per update Reference Mannual, correct the enet clock parent to wakeup_axi_root. Fixes: 24defbe194b6 ("clk: imx: add i.MX93 clk") Reviewed-by: Ye Li <[email protected]> Signed-off-by: Peng Fan <[email protected]> Reviewed-by: Abel Vesa <[email protected]> Signed-off-by: Abel Vesa <[email protected]> Link: https://lore.kernel.org/r/[email protected]
2022-11-21clk: imx93: unmap anatop base in error handling pathPeng Fan1-6/+9
The anatop base is not unmapped during error handling path, fix it. Fixes: 24defbe194b6 ("clk: imx: add i.MX93 clk") Reported-by: Dan Carpenter <[email protected]> Signed-off-by: Peng Fan <[email protected]> Reviewed-by: Abel Vesa <[email protected]> Signed-off-by: Abel Vesa <[email protected]> Link: https://lore.kernel.org/r/[email protected]
2022-11-21clk: imx: imx8mp: add shared clk gate for usb suspend clkLi Jun1-1/+3
32K usb suspend clock gate is shared with usb_root_clk, this shared clock gate was initially defined only for usb suspend clock, usb suspend clk is kept on while system is active or system sleep with usb wakeup enabled, so usb root clock is fine with this situation; with the commit cf7f3f4fa9e5 ("clk: imx8mp: fix usb_root_clk parent"), this clock gate is changed to be for usb root clock, but usb root clock will be off while usb is suspended, so usb suspend clock will be gated too, this cause some usb functionalities will not work, so define this clock to be a shared clock gate to conform with the real HW status. Fixes: 9c140d9926761 ("clk: imx: Add support for i.MX8MP clock driver") Cc: [email protected] # v5.19+ Tested-by: Alexander Stein <[email protected]> Signed-off-by: Li Jun <[email protected]> Signed-off-by: Abel Vesa <[email protected]> Link: https://lore.kernel.org/r/[email protected]
2022-11-21clk: imx93: correct the flexspi1 clock settingHaibo Chen1-1/+1
Correct IMX93_CLK_FLEXSPI1_GATE CCGR setting. Otherwise the flexspi always can't be assigned to a parent clock when dump the clock tree. Fixes: 24defbe194b6 ("clk: imx: add i.MX93 clk") Reviewed-by: Peng Fan <[email protected]> Signed-off-by: Haibo Chen <[email protected]> Reviewed-by: Abel Vesa <[email protected]> Signed-off-by: Abel Vesa <[email protected]> Link: https://lore.kernel.org/r/[email protected]
2022-11-19clk: tegra: Support BPMP-FW ABI deny flagsPeter De Schrijver1-3/+34
Support BPMP_CLK_STATE_CHANGE_DENIED by not populating state changing operations when the flag is set. Support BPMP_CLK_RATE_PARENT_CHANGE_DENIED by not populating rate or parent changing operations when the flag is set. Signed-off-by: Peter De Schrijver <[email protected]> Acked-by: Stephen Boyd <[email protected]> Signed-off-by: Thierry Reding <[email protected]>
2022-11-17ARM: at91: rm9200: fix usb device clock idMichael Grzeschik1-1/+1
Referring to the datasheet the index 2 is the MCKUDP. When enabled, it "Enables the automatic disable of the Master Clock of the USB Device Port when a suspend condition occurs". We fix the index to the real UDP id which "Enables the 48 MHz clock of the USB Device Port". Cc: [email protected] Cc: [email protected] Cc: [email protected] Cc: [email protected] Cc: [email protected] Cc: [email protected] Cc: [email protected] Cc: [email protected] Cc: [email protected] Fixes: 02ff48e4d7f7 ("clk: at91: add at91rm9200 pmc driver") Fixes: 0e0e528d8260 ("ARM: dts: at91: rm9200: switch to new clock bindings") Reviewed-by: Claudiu Beznea <[email protected]> Signed-off-by: Michael Grzeschik <[email protected]> Signed-off-by: Claudiu Beznea <[email protected]> Link: https://lore.kernel.org/r/[email protected]
2022-11-16clk: sunxi-ng: f1c100s: Add IR mod clockAndre Przywara2-2/+11
For some reason the mod clock for the Allwinner F1C100s CIR (infrared receiver) peripheral was not modeled in the CCU driver. Add the clock description to the list, and wire it up in the clock list. By assigning a new clock ID at the end, it extends the number of clocks. This allows to use the CIR peripheral on any F1C100s series board. Signed-off-by: Andre Przywara <[email protected]> Reviewed-by: Jernej Skrabec <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Jernej Skrabec <[email protected]>
2022-11-16clk: sunxi-ng: v3s: Correct the header guard of ccu-sun8i-v3s.hWei Li1-3/+3
Rename the header guard of ccu-sun8i-v3s.h from _CCU_SUN8I_H3_H_ to _CCU_SUN8I_V3S_H_ what corresponding with the file name. Fixes: d0f11d14b0bc ("clk: sunxi-ng: add support for V3s CCU") Signed-off-by: Wei Li <[email protected]> Acked-by: Jernej Skrabec <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Jernej Skrabec <[email protected]>
2022-11-16clk: renesas: r8a779f0: Fix Ethernet Switch clocksGeert Uytterhoeven1-2/+2
The RSwitch2 and EtherTSN-IF clocks were accidentally mixed up. While at it, rename them to better match the (future) documentation. Fixes: a3b4137a4d4023e6 ("clk: renesas: r8a779f0: Add Ethernet Switch clocks") Tested-by: Yoshihiro Shimoda <[email protected]> Signed-off-by: Geert Uytterhoeven <[email protected]> Reviewed-by: Yoshihiro Shimoda <[email protected]> Link: https://lore.kernel.org/r/99b8b41bd2c5043c9e457862ef4bc144869eca58.1668501212.git.geert+renesas@glider.be
2022-11-15clk: qcom: Add display clock controller driver for SM6375Konrad Dybcio3-0/+620
Add support for the display clock controller found on SM6375. Signed-off-by: Konrad Dybcio <[email protected]> Signed-off-by: Konrad Dybcio <[email protected]> Signed-off-by: Bjorn Andersson <[email protected]> Link: https://lore.kernel.org/r/[email protected]
2022-11-15clk: rockchip: add clock controller for the RK3588Elaine Zhang5-1/+3447
Add full clock controller support RK3588. [rebase, integrate fixes from Wyon and Finley, add missing frequencies to PLL lookup table, update commit message, add GATE_LINK clocks which downstream handles in its own driver with one DT node per clock] Signed-off-by: Wyon Bi <[email protected]> Signed-off-by: Finley Xiao <[email protected]> Signed-off-by: Elaine Zhang <[email protected]> Signed-off-by: Sebastian Reichel <[email protected]> Link: https://lore.kernel.org/r/[email protected] [dropped module stuff after talking to Sebastian] Signed-off-by: Heiko Stuebner <[email protected]>
2022-11-15clk: samsung: Revert "clk: samsung: exynos-clkout: Use ↵Marek Szyprowski1-2/+4
of_device_get_match_data()" of_device_get_match_data() function should not be used on the device other than the one matched to the given driver, because it always returns the match_data of the matched driver. In case of exynos-clkout driver, the code matched the OF IDs on the PARENT device, so replacing it with of_device_get_match_data() broke the driver. This reverts commit 777aaf3d1daf793461269b49c063aca1cee06a44. Signed-off-by: Marek Szyprowski <[email protected]> Fixes: 777aaf3d1daf ("clk: samsung: exynos-clkout: Use of_device_get_match_data()") Reviewed-by: Krzysztof Kozlowski <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Krzysztof Kozlowski <[email protected]>
2022-11-15clk: renesas: r8a779g0: Add Z0 clock supportGeert Uytterhoeven1-0/+1
Add support for the Z0 (Cortex-A76 Sub-System) clock on R-Car V4H, based on the existing support for Z clocks on R-Car Gen4. Extracted from a patch in the BSP by LUU HOAI. Signed-off-by: Geert Uytterhoeven <[email protected]> Link: https://lore.kernel.org/r/75daa1fd8fa7eaef7b8945bb5906c787222c7ac4.1668423063.git.geert+renesas@glider.be
2022-11-14clk: rockchip: add lookup table supportSebastian Reichel2-15/+40
Add support for mapping reset IDs to register offsets to support gapless continous platform reset IDs. Signed-off-by: Sebastian Reichel <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Heiko Stuebner <[email protected]>
2022-11-14clk: rockchip: simplify rockchip_clk_add_lookupSebastian Reichel2-10/+6
rockchip_clk_add_lookup is only called from within the file, so it can be made static. The additional checks are removed with the following reasoning: 1. The data structure is initialized by rockchip_clk_init(), which is called by all rockchip platforms before the clocks are registered. Not doing so would result in an incomplete clock tree at the moment, which is a fatal error. In other parts of the kernel these kind of checks are usually omitted, so this was done here. The alternative is adding a pr_err to inform the kernel programmer adding a new platform about his incorrect code. Apart from that we are also not checking if the clock id is within the array boundings. 2. While not used so far by any rockchip platform, 0 is a valid clock identifier. To align rockchip closer to other ARM platforms we will start using it with rk3588. Signed-off-by: Sebastian Reichel <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Heiko Stuebner <[email protected]>
2022-11-14clk: rockchip: allow additional mux options for cpu-clock frequency changesElaine Zhang2-0/+43
In order to improve the main frequency of CPU, the clock path of CPU is simplified as follows: |--\ | \ |--\ --apll--|\ | \ | \ | |--apll_core--| \ | \ --24M---|/ |mux1 |--[gate]--|mux2|---clk_core | / | / --gpll--|\ | / |------| / | |--gpll_core--| / | |--/ --24M---|/ |--/ | | -------apll_directly--------------| When the CPU requests high frequency, we want to use MUX2 select the "apll_directly". At low frequencies use MUX1 to select “apll_core" and then MUX2 to select "apll_core_gate". However, in this way, the CPU frequency conversion needs to be in the following order: 1. MUX2 select to "apll_core_gate", MUX1 select "gpll_core" 2. Apll sets slow_mode, sets APLL parameters, locks APLL, and then APLL sets normal_mode 3. MUX1 select "apll_core", MUX2 select "apll_directly" So add pre_mux and post_mux options to cover this special requirements. Signed-off-by: Elaine Zhang <[email protected]> [rebase] Signed-off-by: Sebastian Reichel <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Heiko Stuebner <[email protected]>
2022-11-14clk: rockchip: add pll type for RK3588Elaine Zhang2-1/+235
Add RK3588 PLL support fully relying on lookup tables like the other upstream supported rockchip platforms. Signed-off-by: Elaine Zhang <[email protected]> [rebase and modify code to avoid PLL parameter calculation] Signed-off-by: Sebastian Reichel <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Heiko Stuebner <[email protected]>
2022-11-14clk: rockchip: add register offset of the cores select parentElaine Zhang2-8/+23
The cores select parent register is special on RK3588. Signed-off-by: Elaine Zhang <[email protected]> Signed-off-by: Sebastian Reichel <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Heiko Stuebner <[email protected]>
2022-11-09clk: qcom: Add SC8280XP display clock controllerBjorn Andersson3-0/+3228
The Qualcomm SC8280XP platform has two display clock controller instances, add support for these. Duplication between the two implementations is reduced by reusing any constant data between the two sets of clock data. Signed-off-by: Bjorn Andersson <[email protected]> Signed-off-by: Bjorn Andersson <[email protected]> Reviewed-by: Konrad Dybcio <[email protected]> Tested-by: Steev Klimaszewski <[email protected]> Signed-off-by: Bjorn Andersson <[email protected]> Link: https://lore.kernel.org/r/[email protected]
2022-11-08clk: meson: pll: add pcie lock retry workaroundHeiner Kallweit1-4/+8
The PCIe PLL locking may be unreliable under some circumstance, such as high or low temperature. If the PLL fails to lock, reset it a try again. This helps on the S905X4 Signed-off-by: Heiner Kallweit <[email protected]> [commit message amend] Signed-off-by: Jerome Brunet <[email protected]> Link: https://lore.kernel.org/r/[email protected]
2022-11-08clk: meson: pll: adjust timeout in meson_clk_pll_wait_lock()Heiner Kallweit1-4/+4
Currently we loop over meson_parm_read() up to 24mln times. This results in a unpredictable timeout period. In my case it's over 5s on a S905X4-based system. Make the timeout period predictable and set it to 100ms. Signed-off-by: Heiner Kallweit <[email protected]> Signed-off-by: Jerome Brunet <[email protected]> Link: https://lore.kernel.org/r/[email protected]
2022-11-08clk: renesas: r8a779g0: Add CMT clocksWolfram Sang1-0/+4
Signed-off-by: Wolfram Sang <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Geert Uytterhoeven <[email protected]>
2022-11-08clk: renesas: r8a779g0: Add TMU and SASYNCRT clocksWolfram Sang1-0/+6
Signed-off-by: Wolfram Sang <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Geert Uytterhoeven <[email protected]>
2022-11-08clk: renesas: r8a779f0: Fix SCIF parent clocksWolfram Sang1-4/+4
As serial communication requires a clean clock signal, the Serial Communication Interfaces with FIFO (SCIF) are clocked by a clock that is not affected by Spread Spectrum or Fractional Multiplication. Hence change the parent clocks for the SCIF modules from the S0D12_PER clock to the SASYNCPERD4 clock (which has the same clock rate), cfr. R-Car S4-8 Hardware User's Manual rev. 0.81. Fixes: 24aaff6a6ce4 ("clk: renesas: cpg-mssr: Add support for R-Car S4-8") Reported-by: Geert Uytterhoeven <[email protected]> Signed-off-by: Wolfram Sang <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Geert Uytterhoeven <[email protected]>
2022-11-08clk: renesas: r8a779f0: Fix HSCIF parent clocksWolfram Sang1-4/+4
As serial communication requires a clean clock signal, the High Speed Serial Communication Interfaces with FIFO (HSCIF) are clocked by a clock that is not affected by Spread Spectrum or Fractional Multiplication. Hence change the parent clocks for the HSCIF modules from the S0D3_PER clock to the SASYNCPERD1 clock (which has the same clock rate), cfr. R-Car S4-8 Hardware User's Manual rev. 0.81. Fixes: 080bcd8d5997 ("clk: renesas: r8a779f0: Add HSCIF clocks") Reported-by: Geert Uytterhoeven <[email protected]> Signed-off-by: Wolfram Sang <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Geert Uytterhoeven <[email protected]>
2022-11-07clk: qcom: ipq8074: convert to parent dataRobert Marko1-968/+813
Convert the IPQ8074 GCC driver to use parent data instead of global name matching. Utilize ARRAY_SIZE for num_parents instead of hardcoding the value. Signed-off-by: Robert Marko <[email protected]> Signed-off-by: Bjorn Andersson <[email protected]> Link: https://lore.kernel.org/r/[email protected]
2022-11-07clk: qcom: Add support for QDU1000 and QRU1000 RPMh clocksMelody Olvera1-0/+13
Add support for RMPh clocks for QDU1000 and QRU1000 SoCs. Signed-off-by: Melody Olvera <[email protected]> Signed-off-by: Bjorn Andersson <[email protected]> Link: https://lore.kernel.org/r/[email protected]
2022-11-05clk: qcom: dispcc-sm8250: Disable link_div_clk_src for sm8150Robert Foss1-0/+11
SM8150 does not have any of the link_div_clk_src clocks, so let's disable them for this SoC. Signed-off-by: Robert Foss <[email protected]> Reviewed-by: Dmitry Baryshkov <[email protected]> Signed-off-by: Bjorn Andersson <[email protected]> Link: https://lore.kernel.org/r/[email protected]
2022-11-05clk: qcom: dispcc-sm8250: Add missing EDP clocks for sm8350Robert Foss1-1/+21
SM8350 supports embedded displayport, but the clocks for this were previously not accounted for. Signed-off-by: Robert Foss <[email protected]> Reviewed-by: Dmitry Baryshkov <[email protected]> Signed-off-by: Bjorn Andersson <[email protected]> Link: https://lore.kernel.org/r/[email protected]
2022-11-05clk: qcom: dispcc-sm8250: Add RETAIN_FF_ENABLE flag for mdss_gdscRobert Foss1-1/+1
All SoC supported by this driver supports the RETAIN_FF_ENABLE flag, so it should be enabled here. This feature enables registers to maintain their state after dis/re-enabling the GDSC. Signed-off-by: Robert Foss <[email protected]> Reviewed-by: Dmitry Baryshkov <[email protected]> Reviewed-by: Konrad Dybcio <[email protected]> Signed-off-by: Bjorn Andersson <[email protected]> Link: https://lore.kernel.org/r/[email protected]
2022-11-05clk: qcom: dispcc-sm8250: Disable EDP_GTC for sm8350Robert Foss1-0/+3
SM8350 does not have the EDP_GTC clock, so let's disable it for this SoC. Signed-off-by: Robert Foss <[email protected]> Reviewed-by: Dmitry Baryshkov <[email protected]> Signed-off-by: Bjorn Andersson <[email protected]> Link: https://lore.kernel.org/r/[email protected]
2022-11-05clk: qcom: gcc-sm8250: Use retention mode for USB GDSCsManivannan Sadhasivam1-2/+2
USB controllers on SM8250 doesn't work after coming back from suspend. This can be fixed by keeping the USB GDSCs in retention mode so that hardware can keep them ON and put into rentention mode once the parent domain goes to a low power state. Fixes: 3e5770921a88 ("clk: qcom: gcc: Add global clock controller driver for SM8250") Signed-off-by: Manivannan Sadhasivam <[email protected]> Signed-off-by: Bjorn Andersson <[email protected]> Link: https://lore.kernel.org/r/[email protected]
2022-11-05clk: qcom: dispcc-sm6350: Add CLK_OPS_PARENT_ENABLE to pixel&byte srcKonrad Dybcio1-2/+2
Add the CLK_OPS_PARENT_ENABLE flag to pixel and byte clk srcs to ensure set_rate can succeed. Signed-off-by: Konrad Dybcio <[email protected]> Fixes: 837519775f1d ("clk: qcom: Add display clock controller driver for SM6350") Signed-off-by: Bjorn Andersson <[email protected]> Link: https://lore.kernel.org/r/[email protected]
2022-11-05clk: qcom: gcc-sm6125: Remove gpll7 from sdcc2_appsMartin Botka1-1/+0
This removes gpll7 clock source from sdcc2_apps as it caused issues on the device during testing Signed-off-by: Martin Botka <[email protected]> Signed-off-by: Bjorn Andersson <[email protected]> Link: https://lore.kernel.org/r/[email protected]
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