aboutsummaryrefslogtreecommitdiff
path: root/drivers/clk
AgeCommit message (Collapse)AuthorFilesLines
2023-01-10clk: qcom: gcc-msm8976: switch to parent_hwsDmitry Baryshkov1-15/+15
Change several entries of parent_data to use parent_hws instead, which results in slightly more ovbious code. Signed-off-by: Dmitry Baryshkov <[email protected]> Signed-off-by: Bjorn Andersson <[email protected]> Link: https://lore.kernel.org/r/[email protected]
2023-01-10clk: qcom: gcc-msm8939: switch to parent_hwsDmitry Baryshkov1-16/+16
Change several entries of parent_data to use parent_hws instead, which results in slightly more ovbious code. Signed-off-by: Dmitry Baryshkov <[email protected]> Signed-off-by: Bjorn Andersson <[email protected]> Link: https://lore.kernel.org/r/[email protected]
2023-01-10clk: qcom: camcc-sm8450: switch to parent_hwsDmitry Baryshkov1-162/+162
Change several entries of parent_data to use parent_hws instead, which results in slightly more ovbious code. Signed-off-by: Dmitry Baryshkov <[email protected]> Signed-off-by: Bjorn Andersson <[email protected]> Link: https://lore.kernel.org/r/[email protected]
2023-01-10clk: qcom: camcc-sc7280: switch to parent_hwsDmitry Baryshkov1-134/+134
Change several entries of parent_data to use parent_hws instead, which results in slightly more ovbious code. Signed-off-by: Dmitry Baryshkov <[email protected]> Signed-off-by: Bjorn Andersson <[email protected]> Link: https://lore.kernel.org/r/[email protected]
2023-01-10clk: qcom: dispcc-sm6375: switch to parent_hwsDmitry Baryshkov1-2/+2
Change several entries of parent_data to use parent_hws instead, which results in slightly more ovbious code. Signed-off-by: Dmitry Baryshkov <[email protected]> Signed-off-by: Bjorn Andersson <[email protected]> Link: https://lore.kernel.org/r/[email protected]
2023-01-10clk: qcom: dispcc-sc7180: switch to parent_hwsDmitry Baryshkov1-4/+4
Change several entries of parent_data to use parent_hws instead, which results in slightly more ovbious code. Signed-off-by: Dmitry Baryshkov <[email protected]> Signed-off-by: Bjorn Andersson <[email protected]> Link: https://lore.kernel.org/r/[email protected]
2023-01-10clk: qcom: dispcc-sm8450: switch to parent_hwsDmitry Baryshkov1-106/+106
Change several entries of parent_data to use parent_hws instead, which results in slightly more ovbious code. Signed-off-by: Dmitry Baryshkov <[email protected]> Signed-off-by: Bjorn Andersson <[email protected]> Link: https://lore.kernel.org/r/[email protected]
2023-01-10clk: qcom: add SM8550 DISPCC driverNeil Armstrong3-0/+1817
Add support for the display clock controller found in SM8550 based devices. This clock controller feeds the Multimedia Display SubSystem (MDSS). This driver is based on the SM8450 support. Signed-off-by: Neil Armstrong <[email protected]> Reviewed-by: Konrad Dybcio <[email protected]> Signed-off-by: Bjorn Andersson <[email protected]> Link: https://lore.kernel.org/r/20230103-topic-sm8550-upstream-dispcc-v3-3-8a03d348c572@linaro.org
2023-01-10clk: qcom: clk-alpha-pll: define alias of LUCID OLE reset ops to EVO reset opsNeil Armstrong1-0/+1
Add an alias of LUCID OLE reset ops to EVO reset ops similar to other aliases. Signed-off-by: Neil Armstrong <[email protected]> Acked-by: Konrad Dybcio <[email protected]> Signed-off-by: Bjorn Andersson <[email protected]> Link: https://lore.kernel.org/r/20230103-topic-sm8550-upstream-dispcc-v3-2-8a03d348c572@linaro.org
2023-01-10Merge tag '[email protected]' into ↵Bjorn Andersson1-5/+6
clk-for-6.3 v6.2-rc1 + [email protected]
2023-01-10clk: qcom: gdsc: Support 'synced_poweroff' genpd flagAkhil P Oommen1-5/+6
Add support for the newly added 'synced_poweroff' genpd flag. This allows some clients (like adreno gpu driver) to request gdsc driver to ensure a votable gdsc (like gpucc cx gdsc) has collapsed at hardware. Signed-off-by: Akhil P Oommen <[email protected]> Reviewed-by: Ulf Hansson <[email protected]> Signed-off-by: Bjorn Andersson <[email protected]> Link: https://lore.kernel.org/r/20230102161757.v5.2.Ic128c1df50b7fc9a6b919932a3b41a799b5ed5e8@changeid
2023-01-10clk: qcom: sdm845: Use generic clk_sync_state_disable_unused callbackAbel Vesa4-0/+4
By adding the newly added clk_sync_state_disable_unused as sync_state callback to all sdm845 clock providers, we make sure that no clock belonging to these providers gets disabled on clk_disable_unused, but rather they are disabled on sync_state, when it is safe, since all the consumers build as modules have had their chance of enabling their own clocks. Signed-off-by: Abel Vesa <[email protected]> Reviewed-by: Bjorn Andersson <[email protected]> Reviewed-by: Dmitry Baryshkov <[email protected]> Signed-off-by: Bjorn Andersson <[email protected]> Link: https://lore.kernel.org/r/[email protected]
2023-01-10clk: Add generic sync_state callback for disabling unused clocksAbel Vesa1-11/+46
There are unused clocks that need to remain untouched by clk_disable_unused, and most likely could be disabled later on sync_state. So provide a generic sync_state callback for the clock providers that register such clocks. Then, use the same mechanism as clk_disable_unused from that generic callback, but pass the device to make sure only the clocks belonging to the current clock provider get disabled, if unused. Also, during the default clk_disable_unused, if the driver that registered the clock has the generic clk_sync_state_disable_unused callback set for sync_state, skip disabling its clocks. Signed-off-by: Abel Vesa <[email protected]> Reviewed-by: Bjorn Andersson <[email protected]> Reviewed-by: Dmitry Baryshkov <[email protected]> Signed-off-by: Bjorn Andersson <[email protected]> Link: https://lore.kernel.org/r/[email protected]
2023-01-10clk: qcom: rpmh: add clocks for sa8775pBartosz Golaszewski1-0/+17
Extend the driver with a description of clocks for sa8775p platforms. Signed-off-by: Bartosz Golaszewski <[email protected]> Reviewed-by: Konrad Dybcio <[email protected]> Signed-off-by: Bjorn Andersson <[email protected]> Link: https://lore.kernel.org/r/[email protected]
2023-01-10clk: qcom: krait-cc: fix wrong pointer passed to IS_ERR()Yang Yingliang1-2/+2
It should be 'mux' passed to IS_ERR/PTR_ERR(). Fixes: 56a655e1c41a ("clk: qcom: krait-cc: convert to parent_data API") Signed-off-by: Yang Yingliang <[email protected]> Signed-off-by: Bjorn Andersson <[email protected]> Link: https://lore.kernel.org/r/[email protected]
2023-01-09clk: at91: do not compile dt-compat.c for sama7g5 and sam9x60Claudiu Beznea1-8/+8
There is no need to have dt-compat.c compiled for SAMA7G5 and SAM9X60 as there is no in kernel device tree that could use it. Thus avoid compiling dt-compat.c for them. Signed-off-by: Claudiu Beznea <[email protected]> Link: https://lore.kernel.org/r/[email protected]
2023-01-09clk: at91: mark ddr clocks as criticalClaudiu Beznea15-43/+131
Mark DDR clocks as critical for AT91 devices. These clocks are enabled by bootloader when initializing DDR and needs to stay enabled. Up to this patch the DDR clocks were requested from drivers/memory/atmel-sdramc.c which does only clock request and enable. There is no need to have a separate driver just for this, thus the atmel-sdramc.c will be deleted in a subsequent patch. Signed-off-by: Claudiu Beznea <[email protected]> Link: https://lore.kernel.org/r/[email protected]
2023-01-08clk: sunxi-ng: d1: Add CAN bus gates and resetsFabien Poussin2-1/+12
The D1 CCU contains gates and resets for two CAN buses. While the CAN bus controllers are only documented for the T113 SoC, the CCU is the same across all SoC variants. Signed-off-by: Fabien Poussin <[email protected]> Reviewed-by: Andre Przywara <[email protected]> Signed-off-by: Samuel Holland <[email protected]> Acked-by: Jernej Skrabec <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Jernej Skrabec <[email protected]>
2023-01-08clk: sunxi-ng: d1: Mark cpux clock as criticalAndrás Szemző1-1/+1
Some SoCs in the D1 family feature ARM CPUs instead of a RISC-V CPU. In that case, the CPUs are driven from the 'cpux' clock, so it needs to be marked as critical, since there is no consumer when DVFS is disabled. This matches the drivers for other SoCs, and the "riscv" clock in this driver. Signed-off-by: András Szemző <[email protected]> Acked-by: Jernej Skrabec <[email protected]> Reviewed-by: Andre Przywara <[email protected]> Signed-off-by: Samuel Holland <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Jernej Skrabec <[email protected]>
2023-01-08clk: sunxi-ng: d1: Allow building for R528/T113Samuel Holland1-4/+4
Allwinner released some 32-bit ARM (sun8i) SoCs which use the same CCU as D1. Allow them to reuse the driver. Acked-by: Jernej Skrabec <[email protected]> Reviewed-by: Andre Przywara <[email protected]> Signed-off-by: Samuel Holland <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Jernej Skrabec <[email protected]>
2023-01-08clk: sunxi-ng: Move SoC driver conditions to dependenciesSamuel Holland1-22/+24
Do not duplicate the same expression on the `default` line, so the two lines do not need to be kept in sync. Drivers stay disabled under COMPILE_TEST because of the `default ARCH_SUNXI` applied to SUNXI_CCU. Three drivers had no conditions. - SUN6I_RTC_CCU and SUN8I_DE2_CCU are used on current hardware regardless of CPU architecture. - SUN8I_R_CCU is only used on pre-H6 SoCs, which means no RISCV SoCs. Acked-by: Jernej Skrabec <[email protected]> Signed-off-by: Samuel Holland <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Jernej Skrabec <[email protected]>
2023-01-08clk: sunxi-ng: Remove duplicate ARCH_SUNXI dependenciesSamuel Holland1-22/+21
SUNXI_CCU already depends on ARCH_SUNXI, so adding the dependency to individual SoC drivers is redundant. Drivers stay disabled under COMPILE_TEST because of the `default ARCH_SUNXI` applied to SUNXI_CCU. Acked-by: Jernej Skrabec <[email protected]> Signed-off-by: Samuel Holland <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Jernej Skrabec <[email protected]>
2023-01-08clk: sunxi-ng: Avoid computing the rate twiceSamuel Holland5-23/+26
The ccu_*_find_best() functions already compute a best_rate at the same time as the other factors. Return this value so the caller does not need to duplicate the computation. Signed-off-by: Samuel Holland <[email protected]> Reviewed-by: Jernej Skrabec <[email protected]> Reviewed-by: Andre Przywara <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Jernej Skrabec <[email protected]>
2023-01-08clk: sunxi-ng: h3/h5: Model H3 CLK_DRAM as a fixed clockSamuel Holland1-5/+10
The DRAM controller clock is only allowed to change frequency while the DRAM chips are in self-refresh. To support this, changes to the CLK_DRAM mux and divider have no effect until acknowledged by the memory dynamic frequency scaling (MDFS) hardware inside the DRAM controller. (There is a SDRCLK_UPD bit in DRAM_CFG_REG which should serve a similar purpose, but this bit actually does nothing.) However, the MDFS hardware in H3 appears to be broken. Triggering a frequency change using the procedure from similar SoCs (A64/H5) hangs the hardware. Additionally, the vendor BSP specifically avoids using the MDFS hardware on H3, instead performing all DRAM PHY parameter updates and resets in software. Thus, it is effectively impossible to change the CLK_DRAM mux/divider, so those features should not be modeled. Add CLK_SET_RATE_PARENT so frequency changes apply to PLL_DDR instead. Signed-off-by: Samuel Holland <[email protected]> Reviewed-by: Jernej Skrabec <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Jernej Skrabec <[email protected]>
2023-01-08clk: sunxi-ng: fix ccu_mmc_timing.c kernel-doc issuesRandy Dunlap1-4/+4
Use '-' to separate the function name and its description. Use '%' on constants in kernel-doc notation. Use the kernel-doc Return: format for function return values. Fixes this warning: ccu_mmc_timing.c:21: warning: No description found for return value of 'sunxi_ccu_set_mmc_timing_mode' Signed-off-by: Randy Dunlap <[email protected]> Cc: Yang Li <[email protected]> Cc: Chen-Yu Tsai <[email protected]> Cc: Jernej Skrabec <[email protected]> Cc: Samuel Holland <[email protected]> Cc: [email protected] Cc: [email protected] Cc: Michael Turquette <[email protected]> Cc: Stephen Boyd <[email protected]> Cc: [email protected] Acked-by: Jernej Skrabec <[email protected]> Reviewed-by: Stephen Boyd <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Jernej Skrabec <[email protected]>
2023-01-06clk: qcom: Add TCSR clock driver for SM8550Abel Vesa3-0/+200
The TCSR clock controller found on SM8550 provides refclks for PCIE, USB and UFS. Add clock driver for it. This patch is based on initial code downstream. Signed-off-by: Abel Vesa <[email protected]> Reviewed-by: Konrad Dybcio <[email protected]> Signed-off-by: Bjorn Andersson <[email protected]> Link: https://lore.kernel.org/r/[email protected]
2023-01-06clk: qcom: rpmh: Add support for SM8550 rpmh clocksAbel Vesa1-0/+36
Adds the RPMH clocks present in SM8550 SoC. Signed-off-by: Abel Vesa <[email protected]> Reviewed-by: Konrad Dybcio <[email protected]> Signed-off-by: Bjorn Andersson <[email protected]> Link: https://lore.kernel.org/r/[email protected]
2022-12-29clk: qcom: dispcc-sm6125: Fix compatible string to match bindingsMarijn Suijten1-1/+1
According to generic rules the SoC name should be first: arch/arm64/boot/dts/qcom/sm6125-sony-xperia-seine-pdx201.dtb: clock-controller@5f00000: compatible: 'oneOf' conditional failed, one must be fixed: 'qcom,dispcc-sm6125' does not match '^qcom,(apq|ipq|mdm|msm|qcm|qcs|sa|sc|sdm|sdx|sm)[0-9]+-.*$' And this is already reflected by the bindings submitted prior to the addition of this driver. Any DTS following these rules will end up with a non-probing driver because of this mismatch. Fixes: 6e87c8f07407 ("clk: qcom: Add display clock controller driver for SM6125") Signed-off-by: Marijn Suijten <[email protected]> Reviewed-by: AngeloGioacchino Del Regno <[email protected]> Signed-off-by: Bjorn Andersson <[email protected]> Link: https://lore.kernel.org/r/[email protected]
2022-12-28clk: qcom: Add camera clock controller driver for SM6350Konrad Dybcio3-0/+1914
Add support for the camera clock controller found on SM6350. Signed-off-by: Konrad Dybcio <[email protected]> Signed-off-by: Konrad Dybcio <[email protected]> Signed-off-by: Bjorn Andersson <[email protected]> Link: https://lore.kernel.org/r/[email protected]
2022-12-28clk: qcom: smd-rpm: remove usage of platform nameDmitry Baryshkov1-665/+663
Now that all clocks have individual names, remove the names of SoCs from the SMD RPM clock definitions. Replace it with the common clk_smd_rpm_ prefix. Reviewed-by: Alex Elder <[email protected]> Reviewed-by: Konrad Dybcio <[email protected]> Signed-off-by: Dmitry Baryshkov <[email protected]> Signed-off-by: Bjorn Andersson <[email protected]> Link: https://lore.kernel.org/r/[email protected]
2022-12-28clk: qcom: smd-rpm: rename SMD_RPM_BUS clocksDmitry Baryshkov1-121/+131
Add special macro for the clocks of QCOM_SMD_RPM_BUS_CLK type. Use it to insert the _bus_N part into the clock symbol name. The system (and userspace) name of these clocks remains intact. Reviewed-by: Konrad Dybcio <[email protected]> Reviewed-by: Alex Elder <[email protected]> Signed-off-by: Dmitry Baryshkov <[email protected]> Signed-off-by: Bjorn Andersson <[email protected]> Link: https://lore.kernel.org/r/[email protected]
2022-12-28clk: qcom: smd-rpm: rename the qcm2290 rf_clk3 clocksDmitry Baryshkov1-3/+9
Rename the qcm2290_rf_clk3 clocks adding 38m4 prefix to distinguish it from the common (19.2 MHz) rf_clk3. The system (and userspace) name of these clocks remains intact. Reviewed-by: Konrad Dybcio <[email protected]> Reviewed-by: Alex Elder <[email protected]> Signed-off-by: Dmitry Baryshkov <[email protected]> Signed-off-by: Bjorn Andersson <[email protected]> Link: https://lore.kernel.org/r/[email protected]
2022-12-28clk: qcom: smd-rpm: rename SMD_RPM_BRANCH clock symbolsDmitry Baryshkov1-48/+54
To ease distinguishing between branch and non-branch clocks (e.g. aggre1_noc, aggre2_noc and qdss) add '_branch' to all SMD_RPM_BRANCH* clocks. The system (and userspace) name of these clocks remains intact. Reviewed-by: Konrad Dybcio <[email protected]> Reviewed-by: Alex Elder <[email protected]> Signed-off-by: Dmitry Baryshkov <[email protected]> Signed-off-by: Bjorn Andersson <[email protected]> Link: https://lore.kernel.org/r/[email protected]
2022-12-28clk: qcom: smd-rpm: simplify SMD_RPM/_BRANCH/_QDSS clock definitionsDmitry Baryshkov1-43/+53
Remove the duplication between the names of the normal and active-only clocks by moving common sufixes to the clock definition macros. This simplifies adding new clock definitions and reviewing existing defs. Reviewed-by: Alex Elder <[email protected]> Reviewed-by: Konrad Dybcio <[email protected]> Signed-off-by: Dmitry Baryshkov <[email protected]> Signed-off-by: Bjorn Andersson <[email protected]> Link: https://lore.kernel.org/r/[email protected]
2022-12-28clk: qcom: smd-rpm: simplify XO_BUFFER clocks definitionsDmitry Baryshkov1-29/+27
Remove the duplication between the names of the normal and active-only XO_BUFFER and XO_BUFFER_PINCTRL clocks by using preprocessor logic to add _a suffix. Reviewed-by: Alex Elder <[email protected]> Reviewed-by: Konrad Dybcio <[email protected]> Signed-off-by: Dmitry Baryshkov <[email protected]> Signed-off-by: Bjorn Andersson <[email protected]> Link: https://lore.kernel.org/r/[email protected]
2022-12-28clk: qcom: smd-rpm: rename some msm8974 active-only clocksDmitry Baryshkov1-17/+17
Rename msm8974_diff_a_clk, msm8974_div_a_clk1 and msm8974_div_a_clk2 to move the _a suffix to the end of the name. This follows the pattern used by other active-only clocks and thus makes it possible to simplify clock definitions. This changes the userspace-visible names for this clocks. Reviewed-by: Alex Elder <[email protected]> Reviewed-by: Konrad Dybcio <[email protected]> Signed-off-by: Dmitry Baryshkov <[email protected]> Signed-off-by: Bjorn Andersson <[email protected]> Link: https://lore.kernel.org/r/[email protected]
2022-12-28clk: qcom: smd-rpm: move clock definitions togetherDmitry Baryshkov1-69/+59
To ease review and reuse group all clock definitions together. Reviewed-by: Alex Elder <[email protected]> Reviewed-by: Konrad Dybcio <[email protected]> Signed-off-by: Dmitry Baryshkov <[email protected]> Signed-off-by: Bjorn Andersson <[email protected]> Link: https://lore.kernel.org/r/[email protected]
2022-12-28clk: qcom: smd-rpm: fix alignment of line breaking backslashesDmitry Baryshkov1-16/+16
The commit 52a436e0b7fe ("clk: qcom: smd-rpm: Switch to parent_data") introduced ragged right alignment for the line breaking backslash. Fix it to make the code look consistently. Reviewed-by: Alex Elder <[email protected]> Signed-off-by: Dmitry Baryshkov <[email protected]> Signed-off-by: Bjorn Andersson <[email protected]> Link: https://lore.kernel.org/r/[email protected]
2022-12-28clk: qcom: smd-rpm: drop the rpm_status_id fieldDmitry Baryshkov1-13/+7
The rpm_status_id field is a leftover from the non-SMD clocks. It is of no use for the SMD-RPM clock driver and is always equal to zero. Drop it completely. Reviewed-by: Konrad Dybcio <[email protected]> Reviewed-by: Alex Elder <[email protected]> Signed-off-by: Dmitry Baryshkov <[email protected]> Signed-off-by: Bjorn Andersson <[email protected]> Link: https://lore.kernel.org/r/[email protected]
2022-12-28clk: qcom: smd-rpm: add XO_BUFFER clock for each XO_BUFFER_PINCTRL clockDmitry Baryshkov1-29/+18
For each XO_BUFFER_PINCTRL there is a corresponding XO_BUFFER clock. Add them automatically to drop the duplication between the clock definitions. Reviewed-by: Alex Elder <[email protected]> Reviewed-by: Konrad Dybcio <[email protected]> Signed-off-by: Dmitry Baryshkov <[email protected]> Signed-off-by: Bjorn Andersson <[email protected]> Link: https://lore.kernel.org/r/[email protected]
2022-12-28clk: qcom: smd-rpm: remove duplication between sm6375 and sm6125 clocksDmitry Baryshkov1-6/+4
Reuse sm6125's MMAXI clocks for sm6375. Reviewed-by: Konrad Dybcio <[email protected]> Reviewed-by: Alex Elder <[email protected]> Signed-off-by: Dmitry Baryshkov <[email protected]> Signed-off-by: Bjorn Andersson <[email protected]> Link: https://lore.kernel.org/r/[email protected]
2022-12-28clk: qcom: smd-rpm: rename msm8992_ln_bb_* clocks to qcs404_ln_bb_*Dmitry Baryshkov1-12/+12
For each of XO_BUFFER_PINCTRL clocks there is a corresponding XO_BUFFER clock with the similar name (e.g. msm8998_ln_bb_clk3_pin vs msm8998_ln_bb_clk3). For qcs404_ln_bb_clk_pin there is no qcs404_ln_bb_clk, since the msm8992_ln_bb_clk was used instead (even for qcs404 platform). Follow the usual practice and rename msm8992_ln_bb_clk clocks to qcs404_ln_bb_clk (and rename active-only clock in a similar way). This is a preparation step for the next patch, which will merge XO_BUFFER and XO_BUFFER_PINCTRL definitions. Reviewed-by: Konrad Dybcio <[email protected]> Reviewed-by: Alex Elder <[email protected]> Signed-off-by: Dmitry Baryshkov <[email protected]> Signed-off-by: Bjorn Andersson <[email protected]> Link: https://lore.kernel.org/r/[email protected]
2022-12-28clk: qcom: smd-rpm: use msm8998_ln_bb_clk2 for qcm2290 SoCDmitry Baryshkov1-3/+2
The qcm2290's ln_bb_clk2 is identical to the freshly added msm8998's ln_bb_clk2 one. Use the latter and drop the SoC-specific version. Reviewed-by: Alex Elder <[email protected]> Reviewed-by: Konrad Dybcio <[email protected]> Signed-off-by: Dmitry Baryshkov <[email protected]> Signed-off-by: Bjorn Andersson <[email protected]> Link: https://lore.kernel.org/r/[email protected]
2022-12-28clk: qcom: smd-rpm: add missing ln_bb_clkN clocksDmitry Baryshkov1-20/+24
Newer platforms (msm8998, sdm660, sm6125) have low noise LN_BB_CLKn clocks. The driver already uses proper clock indices (RPM_SMD_LN_BB_CLKn). Fix clock names used by these platforms. Fixes: a0384ecfe2aa ("clk: qcom: smd-rpm: De-duplicate identical entries") Fixes: edeb2ca74716 ("clk: qcom: smd: Add support for SM6125 rpm clocks") Reviewed-by: Konrad Dybcio <[email protected]> Reviewed-by: Alex Elder <[email protected]> Signed-off-by: Dmitry Baryshkov <[email protected]> Signed-off-by: Bjorn Andersson <[email protected]> Link: https://lore.kernel.org/r/[email protected]
2022-12-28clk: qcom: smd-rpm: remove duplication between qcs404 and qcm2290 clocksDmitry Baryshkov1-7/+4
Reuse qcs404's QPIC and BIMC_GPU clock for qcm2290. Fixes: 78b727d02815 ("clk: qcom: smd-rpm: Add QCM2290 RPM clock support") Reviewed-by: Konrad Dybcio <[email protected]> Reviewed-by: Alex Elder <[email protected]> Signed-off-by: Dmitry Baryshkov <[email protected]> Signed-off-by: Bjorn Andersson <[email protected]> Link: https://lore.kernel.org/r/[email protected]
2022-12-28clk: qcom: smd-rpm: remove duplication between MMXI and MMAXI definesDmitry Baryshkov1-2/+2
The commit 644c42295592 ("clk: qcom: smd: Add SM6375 clocks") added a duplicate of the existing define QCOM_SMD_RPM_MMAXI_CLK, drop it now. Fixes: 644c42295592 ("clk: qcom: smd: Add SM6375 clocks") Reviewed-by: Alex Elder <[email protected]> Signed-off-by: Dmitry Baryshkov <[email protected]> Signed-off-by: Bjorn Andersson <[email protected]> Link: https://lore.kernel.org/r/[email protected]
2022-12-28clk: qcom: smd-rpm: enable pin-controlled ln_bb_clk clocks on qcs404Dmitry Baryshkov1-0/+2
The commit eaeee28db289 ("clk: qcom: smd: Add support for QCS404 rpm clocks") defined the pin-controlled ln_bb_clk clocks, but didn't add them to the qcs404_clks array. Add them to make these clocks usable to platform devices. Fixes: eaeee28db289 ("clk: qcom: smd: Add support for QCS404 rpm clocks") Reviewed-by: Alex Elder <[email protected]? Reviewed-by: Konrad Dybcio <[email protected]> Signed-off-by: Dmitry Baryshkov <[email protected]> Signed-off-by: Bjorn Andersson <[email protected]> Link: https://lore.kernel.org/r/[email protected]
2022-12-27clk: qcom: gcc-sm6115: Use floor_ops for SDCC1/2 core clkKonrad Dybcio1-2/+2
Just like in case of other SoCs change SDCC1/SDCC2 ops to floor to avoid overclocking the controller. Fixes: cbe63bfdc54f ("clk: qcom: Add Global Clock controller (GCC) driver for SM6115") Signed-off-by: Konrad Dybcio <[email protected]> Reviewed-by: Iskren Chernev <[email protected]> Signed-off-by: Bjorn Andersson <[email protected]> Link: https://lore.kernel.org/r/[email protected]
2022-12-27clk: qcom: gcc-qcs404: add support for GDSCsDmitry Baryshkov1-0/+24
Add support for two GDSCs provided by this clock controller. Reviewed-by: Konrad Dybcio <[email protected]> Signed-off-by: Dmitry Baryshkov <[email protected]> Signed-off-by: Bjorn Andersson <[email protected]> Link: https://lore.kernel.org/r/[email protected]
2022-12-27clk: qcom: gcc-qcs404: sort out the cxo clockDmitry Baryshkov1-56/+41
The GCC driver registers the cxo clock as a thin wrapper around board's xo_board clock. Nowadays we can use the xo_board directly in all the clocks that use it. Use the fw_name "cxo" for this clock. Reviewed-by: Konrad Dybcio <[email protected]> Signed-off-by: Dmitry Baryshkov <[email protected]> Signed-off-by: Bjorn Andersson <[email protected]> Link: https://lore.kernel.org/r/[email protected]
Powered by cgit, Gruvboxed by Blaster4385.