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Increase human readability and decrease number of lines by compressing
the clock array entries where possible, to a maximum of ~95 columns.
Signed-off-by: AngeloGioacchino Del Regno <[email protected]>
Reviewed-by: Chen-Yu Tsai <[email protected]>
Tested-by: Chen-Yu Tsai <[email protected]>
Link: https://lore.kernel.org/r/20230306140543.1813621-21-angelogioacchino.delregno@collabora.com
Signed-off-by: Stephen Boyd <[email protected]>
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In preparation for migrating all other mt8183 clocks to the common
mtk_clk_simple_probe(), move apmixedsys clocks to a different file.
While at it, use the builtin_platform_driver() macro for it and fix
some indentation issues in the PLLs table.
During the conversion, error handling was added to the apmixedsys
probe function.
Signed-off-by: AngeloGioacchino Del Regno <[email protected]>
Reviewed-by: Chen-Yu Tsai <[email protected]>
Tested-by: Chen-Yu Tsai <[email protected]>
Link: https://lore.kernel.org/r/20230306140543.1813621-20-angelogioacchino.delregno@collabora.com
Signed-off-by: Stephen Boyd <[email protected]>
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Convert topckgen and infracfg clock drivers to use the common
mtk_clk_simple_probe() mechanism and change this from the old
"static" CLK_OF_DECLARE to be a platform driver, allowing it
to eventually be built as a module.
Thanks to the conversion, more error handling was added to the clocks
registration.
Signed-off-by: AngeloGioacchino Del Regno <[email protected]>
Reviewed-by: Chen-Yu Tsai <[email protected]>
Link: https://lore.kernel.org/r/20230306140543.1813621-19-angelogioacchino.delregno@collabora.com
Signed-off-by: Stephen Boyd <[email protected]>
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In preparation for converting the MT8167 clock drivers to be proper
platform_driver(s), drop the __initconst annotation from all of the
clock arrays since they will be used not only during init but also
during runtime.
Signed-off-by: AngeloGioacchino Del Regno <[email protected]>
Reviewed-by: Chen-Yu Tsai <[email protected]>
Link: https://lore.kernel.org/r/20230306140543.1813621-18-angelogioacchino.delregno@collabora.com
Signed-off-by: Stephen Boyd <[email protected]>
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In preparation for migrating all other MT8167 clocks to the common
mtk_clk_simple_probe(), move apmixedsys clocks to a different file.
While at it, also migrate away from the legacy CLK_OF_DECLARE and
convert this clock driver to be a platform_driver instead.
During the conversion, error handling was added to the apmixedsys
probe function.
Signed-off-by: AngeloGioacchino Del Regno <[email protected]>
Reviewed-by: Chen-Yu Tsai <[email protected]>
Link: https://lore.kernel.org/r/20230306140543.1813621-17-angelogioacchino.delregno@collabora.com
Signed-off-by: Stephen Boyd <[email protected]>
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Use the GATE_MTK macro to compress the GATE_TOP{0..5} macros.
No functional changes.
Signed-off-by: AngeloGioacchino Del Regno <[email protected]>
Reviewed-by: Chen-Yu Tsai <[email protected]>
Link: https://lore.kernel.org/r/20230306140543.1813621-16-angelogioacchino.delregno@collabora.com
Signed-off-by: Stephen Boyd <[email protected]>
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All clocks in this driver are supported by the common simple probe
mechanism and it's now possible to migrate to it.
While at it, also switch to using the module_platform_driver() macro.
Signed-off-by: AngeloGioacchino Del Regno <[email protected]>
Reviewed-by: Chen-Yu Tsai <[email protected]>
Link: https://lore.kernel.org/r/20230306140543.1813621-15-angelogioacchino.delregno@collabora.com
Signed-off-by: Stephen Boyd <[email protected]>
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In preparation for migrating this driver to the simple probe mechanism,
join the audio gates to the top_misc_mux_gates array of mtk_composite
clocks in one top_misc_muxes array.
While at it, since the `apll_i2s0_parents` array is for all i2s clocks,
rename that to `apll_i2s_parents`.
Signed-off-by: AngeloGioacchino Del Regno <[email protected]>
Reviewed-by: Chen-Yu Tsai <[email protected]>
Link: https://lore.kernel.org/r/20230306140543.1813621-14-angelogioacchino.delregno@collabora.com
Signed-off-by: Stephen Boyd <[email protected]>
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On this SoC some clocks apparently don't have different offsets for
set/clr/sta registers hence they can be set, cleared and status-read
on one register: this means that it was possible to use simpler gate
clocks instead of custom mtk_gate ones.
In preparation for converting this clock driver to the common probe
mechanism for MediaTek clocks, perform a conversion from simple_gate
to mtk_gate clocks since the latter does provide implicit support
for simple gate clocks as well.
Signed-off-by: AngeloGioacchino Del Regno <[email protected]>
Reviewed-by: Chen-Yu Tsai <[email protected]>
Link: https://lore.kernel.org/r/20230306140543.1813621-13-angelogioacchino.delregno@collabora.com
Signed-off-by: Stephen Boyd <[email protected]>
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In preparation for migrating all other mt8365 clocks to the common
mtk_clk_simple_probe(), move apmixedsys clocks to a different file.
While at it, use the builtin_platform_driver() macro for it.
During the conversion, error handling was added to the apmixedsys
probe function.
Signed-off-by: AngeloGioacchino Del Regno <[email protected]>
Reviewed-by: Chen-Yu Tsai <[email protected]>
Link: https://lore.kernel.org/r/20230306140543.1813621-12-angelogioacchino.delregno@collabora.com
Signed-off-by: Stephen Boyd <[email protected]>
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Now that all of the clocks in clk-mt2712.c are using the common
mtk_clk_simple_{probe,remove}() callbacks we can safely migrate
to module_platform_driver.
While at it, also drop all references to `simple` in the specific
context of mt2712 as that was used in the past only to allow us
to have two platform_driver(s) in one file.
Signed-off-by: AngeloGioacchino Del Regno <[email protected]>
Reviewed-by: Chen-Yu Tsai <[email protected]>
Link: https://lore.kernel.org/r/20230306140543.1813621-11-angelogioacchino.delregno@collabora.com
Signed-off-by: Stephen Boyd <[email protected]>
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Add a .remove() callback to the apmixedsys driver to allow full module
build; while at it, also change the usage of builtin_platform_driver()
to module_platform_driver() to actually make use of the new callback.
Signed-off-by: AngeloGioacchino Del Regno <[email protected]>
Reviewed-by: Chen-Yu Tsai <[email protected]>
Link: https://lore.kernel.org/r/20230306140543.1813621-10-angelogioacchino.delregno@collabora.com
Signed-off-by: Stephen Boyd <[email protected]>
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The only clock driver that does not support mtk_clk_simple_probe() is
apmixedsys: in preparation for enabling module build of non-critical
mt2712 clocks, move this to its own file.
While at it, also fix some indentation issues in the PLLs table.
Signed-off-by: AngeloGioacchino Del Regno <[email protected]>
Reviewed-by: Chen-Yu Tsai <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Stephen Boyd <[email protected]>
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This function was completely missing error handling: add it.
Fixes: e2f744a82d72 ("clk: mediatek: Add MT2712 clock support")
Signed-off-by: AngeloGioacchino Del Regno <[email protected]>
Reviewed-by: Chen-Yu Tsai <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Stephen Boyd <[email protected]>
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Compress the clock arrays entries to allow a maximum of 90 columns:
this greatly increases readability and also generously reduces the
amount of lines.
While at it, also fix some indentation here and there.
This is a cosmetic change. No functional changes.
Signed-off-by: AngeloGioacchino Del Regno <[email protected]>
Reviewed-by: Chen-Yu Tsai <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Stephen Boyd <[email protected]>
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Now that the common mtk_clk_simple_{probe,remove}() functions can deal
with divider clocks it is possible to migrate more clock drivers to it:
in this case, it's about topckgen.
While at it, also perform a fast migration for mcucfg.
Thanks to the conversion, more error handling was added to the clocks
registration.
Signed-off-by: AngeloGioacchino Del Regno <[email protected]>
Reviewed-by: Chen-Yu Tsai <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Stephen Boyd <[email protected]>
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Add support for divider clocks register/unregister in the common
mtk_clk_simple_probe() and mtk_clk_simple_remove() functions.
Signed-off-by: AngeloGioacchino Del Regno <[email protected]>
Reviewed-by: Chen-Yu Tsai <[email protected]>
Tested-by: Miles Chen <[email protected]>
Tested-by: Chen-Yu Tsai <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Stephen Boyd <[email protected]>
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Reduce duplication and simplify all MediaTek multimedia clock drivers
by migrating away from defining custom probe functions for each driver
and instead use mtk_clk_pdev_probe().
While at it, also add a .remove() callback to all of the multimedia
clock drivers where missing.
Signed-off-by: AngeloGioacchino Del Regno <[email protected]>
Reviewed-by: Chen-Yu Tsai <[email protected]>
Tested-by: Miles Chen <[email protected]>
Tested-by: Chen-Yu Tsai <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Stephen Boyd <[email protected]>
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Introduce functions clk_mtk_pdev_probe() and clk_mtk_pdev_remove():
these will be useful to commonize the probe and remove handlers for
multimedia (clk-mtxxxx-mm) drivers as these are registered by the
mtk-mmsys driver instead of having their own devicetree compatible.
In order to do this, the main logic of clk_mtk_simple{probe,remove}()
was moved to new static __clk_mtk_simple_{probe,remove}() functions
that take as parameter a pointer to struct device_node because when
registering the clocks from mtk-mmsys we want to pass a pointer to
the clock driver's parent (which is, obviously, mtk-mmsys) struct
device_node instead.
As for the clock driver's platform data: for the devicetree case, we
keep using the standard match_data mechanism, else we retrieve it
from an id_table.
Signed-off-by: AngeloGioacchino Del Regno <[email protected]>
Reviewed-by: Chen-Yu Tsai <[email protected]>
Tested-by: Miles Chen <[email protected]>
Tested-by: Chen-Yu Tsai <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Stephen Boyd <[email protected]>
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Instead of using of_device_get_match_data(), switch to the generic
device_get_match_data().
Signed-off-by: AngeloGioacchino Del Regno <[email protected]>
Reviewed-by: Chen-Yu Tsai <[email protected]>
Tested-by: Miles Chen <[email protected]>
Tested-by: Chen-Yu Tsai <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Stephen Boyd <[email protected]>
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Add FHCTL parameters and register PLLs through FHCTL to add support
for frequency hopping and SSC. FHCTL will be enabled only on PLLs
specified in devicetree.
This commit brings functional changes only upon addition of
devicetree configuration.
Signed-off-by: AngeloGioacchino Del Regno <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Reviewed-by: Chen-Yu Tsai <[email protected]>
Signed-off-by: Stephen Boyd <[email protected]>
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Add FHCTL parameters and register PLLs through FHCTL to add support
for frequency hopping and SSC. FHCTL will be enabled only on PLLs
specified in devicetree.
This commit brings functional changes only upon addition of
devicetree configuration.
Signed-off-by: AngeloGioacchino Del Regno <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Reviewed-by: Chen-Yu Tsai <[email protected]>
Signed-off-by: Stephen Boyd <[email protected]>
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Add FHCTL parameters and register PLLs through FHCTL to add support
for frequency hopping and SSC. FHCTL will be enabled only on PLLs
specified in devicetree.
This commit brings functional changes only upon addition of
devicetree configuration.
Signed-off-by: AngeloGioacchino Del Regno <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Reviewed-by: Chen-Yu Tsai <[email protected]>
Signed-off-by: Stephen Boyd <[email protected]>
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Add FHCTL parameters and register PLLs through FHCTL to add support
for frequency hopping and SSC. FHCTL will be enabled only on PLLs
specified in devicetree.
This commit brings functional changes only upon addition of
devicetree configuration.
Signed-off-by: AngeloGioacchino Del Regno <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Reviewed-by: Chen-Yu Tsai <[email protected]>
Signed-off-by: Stephen Boyd <[email protected]>
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These functions are used by the various MediaTek apmixed clock drivers
that may be built as modules: export the common functions used to parse
related devicetree properties, register and unregister the PLLFH clocks.
Signed-off-by: AngeloGioacchino Del Regno <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Reviewed-by: Chen-Yu Tsai <[email protected]>
Signed-off-by: Stephen Boyd <[email protected]>
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The Frequency Hopping Controller (FHCTL) seems to have different
versions, as it has a slightly different register layout on some
older SoCs like MT6795, MT8173, MT8183 (and others).
This driver is indeed compatible with at least some of those older
IP revisions, so all we need to do is to add a way to select the
right register layout at registration time.
Signed-off-by: AngeloGioacchino Del Regno <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Reviewed-by: Chen-Yu Tsai <[email protected]>
Signed-off-by: Stephen Boyd <[email protected]>
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The .remove() callback for a platform driver returns an int which makes
many driver authors wrongly assume it's possible to do error handling by
returning an error code. However the value returned is (mostly) ignored
and this typically results in resource leaks. To improve here there is a
quest to make the remove callback return void. In the first step of this
quest all drivers are converted to .remove_new() which already returns
void.
Trivially convert this driver from always returning zero in the remove
callback to the void returning variant.
Signed-off-by: Uwe Kleine-König <[email protected]>
Signed-off-by: Bjorn Andersson <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
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PMU_ALIVE_PCLK is needed for PMU registers access, and it must be always
running, as not only the kernel accesses PMU registers. Make it critical
to ensure that.
Signed-off-by: Sam Protsenko <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Krzysztof Kozlowski <[email protected]>
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The .remove() callback for a platform driver returns an int which makes
many driver authors wrongly assume it's possible to do error handling by
returning an error code. However the value returned is (mostly) ignored
and this typically results in resource leaks. To improve here there is a
quest to make the remove callback return void. In the first step of this
quest all drivers are converted to .remove_new() which already returns
void.
Trivially convert this driver from always returning zero in the remove
callback to the void returning variant.
Signed-off-by: Uwe Kleine-König <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Krzysztof Kozlowski <[email protected]>
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Each entry in the clock table specifies a number of individual bits in
registers, for contolling clock reset, gaiting, etc. These reg/bit were
packed into a u16 to save space. The combined value is difficult to
understand when reviewing the clock table entries.
Introduce a "struct regbit" which still occupies only 16 bits, but
allows the register and bit values to be specified explicitly. Convert
all previous uses of u16 for reg/bit into "struct regbit".
The bulk of this patch converts the clock table to use struct regbit,
making use of the RB() helper macro. The conversion was automated by
script, and as a further verification, the compiled binary of the table
was compared before/after the change (with objdump -D).
The clk_rdesc_set() function now checks for zero reg/bit internally.
This allows callers of that function to remove those checks.
Signed-off-by: Ralph Siemsen <[email protected]>
Reviewed-by: Miquel Raynal <[email protected]>
Reviewed-by: Geert Uytterhoeven <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Geert Uytterhoeven <[email protected]>
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Add some kerneldoc comments for the structures.
Signed-off-by: Ralph Siemsen <[email protected]>
Reviewed-by: Miquel Raynal <[email protected]>
Reviewed-by: Geert Uytterhoeven <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Geert Uytterhoeven <[email protected]>
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Drop three unused fields from the clock descriptor structure, and update
the macros for filling such structures accordingly.
The values for such fields are kept in the source code, now unused, in
case they are needed later.
Signed-off-by: Ralph Siemsen <[email protected]>
Reviewed-by: Miquel Raynal <[email protected]>
Reviewed-by: Geert Uytterhoeven <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Geert Uytterhoeven <[email protected]>
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Several small readability improvements:
- Move enum gate_type definition up and add comments to each field.
- Use this enum instead of generic uint32_t type in clock desc struct.
- Tidy up bitfield syntax and comments in clock desc structure
- Reformat macros for building clock desc to have one assignment per line
There is no functional change.
Signed-off-by: Ralph Siemsen <[email protected]>
Reviewed-by: Geert Uytterhoeven <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Geert Uytterhoeven <[email protected]>
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Add support for the Z2 (Cortex-A53 System CPU) clock on R-Car V3H, which
uses a fixed SYS-CPU divider.
Signed-off-by: Geert Uytterhoeven <[email protected]>
Link: https://lore.kernel.org/r/aad9eaa57acf65cbe43e4d374066a72d760d54d8.1676560357.git.geert+renesas@glider.be
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Add support for the Z2 (Cortex-A53 System CPU) clock on R-Car V3M, which
uses a fixed SYS-CPU divider.
Signed-off-by: Geert Uytterhoeven <[email protected]>
Link: https://lore.kernel.org/r/6a9169e5bc92c2b9549292769a0814e04b9147cf.1676560357.git.geert+renesas@glider.be
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clk_cifout is derived from clk_cifout_src through an integer divider
limited to 32. clk_cifout_src is a child of either cpll, gpll or npll
without any possibility of a divider of any sort. The default clock
parent is cpll.
Let's allow clk_cifout to ask its parent clk_cifout_src to reparent in
order to find the real closest possible rate for clk_cifout and not one
derived from cpll only.
Cc: [email protected] # 4.10+
Fixes: fd8bc829336a ("clk: rockchip: fix the rk3399 cifout clock")
Signed-off-by: Quentin Schulz <[email protected]>
Link: https://lore.kernel.org/r/20221117-rk3399-cifout-set-rate-parent-v1-0-432548d04081@theobroma-systems.com
Signed-off-by: Heiko Stuebner <[email protected]>
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Exynos5433 clock driver implements PM support internally, which might be
also useful for other Exynos clock drivers. Extract all PM related code
from clk-exynos5433 to common ARM64 functions.
Tested-by: Marek Szyprowski <[email protected]>
Signed-off-by: Sam Protsenko <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Krzysztof Kozlowski <[email protected]>
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Extract parent clock enabling from exynos_arm64_register_cmu() to
dedicated function.
Tested-by: Marek Szyprowski <[email protected]>
Signed-off-by: Sam Protsenko <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Krzysztof Kozlowski <[email protected]>
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It might be useful to have a separate clocks registration function, so
it can be called from different users. Extract that common code from
samsung_cmu_register_one() to samsung_cmu_register_clocks(). Also make
that new function global as it's going to be used in other modules
further.
Tested-by: Marek Szyprowski <[email protected]>
Signed-off-by: Sam Protsenko <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Krzysztof Kozlowski <[email protected]>
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The K210 clock driver depends on SOC_CANAAN, which is only selectable
when !MMU on RISC-V. !MMU is not possible on 32-bit yet, but patches
have been sent for its enabling. The kernel test robot reported this
implicit 64-bit division there.
Replace the implicit division with an explicit one.
Reported-by: kernel test robot <[email protected]>
Link: https://lore.kernel.org/linux-riscv/[email protected]/
Signed-off-by: Conor Dooley <[email protected]>
Signed-off-by: Jesse Taube <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Reviewed-by: Damien Le Moal <[email protected]>
Signed-off-by: Stephen Boyd <[email protected]>
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Add a little description about how reset lines can be implicit with
clock enable/disable. This is mostly based on the commit message
from the original submission in 15ed8ce5f8.
Signed-off-by: Jeremy Kerr <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Reviewed-by: Joel Stanley <[email protected]>
Tested-by: Joel Stanley <[email protected]>
Signed-off-by: Stephen Boyd <[email protected]>
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The current ast2600 I3C clock definitions are top-level (rather than
based on their actual hw sources: either HCLK or APLL), and include a
couple of definitions for (non-existent) i3c6 and i3c7.
Re-parent the individual I3C controller clocks to the main i3c clock,
explicitly sourced from the APLL rather than whatever G6_CLK_SELECTION5
was last set to.
While we're at it, remove the definitions for the i3c6 and i3c7 clock
lines; this hardware isn't present.
This is a partial cherry-pick and rework of ed44b8cdfdb and 1a35eb926d7
from Aspeed's own tree, originally by Dylan Hung
<[email protected]>.
Signed-off-by: Jeremy Kerr <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Reviewed-by: Joel Stanley <[email protected]>
Tested-by: Joel Stanley <[email protected]>
Signed-off-by: Stephen Boyd <[email protected]>
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We're about to remove an entry from aspeed_g6_gates, but we won't want
to alter/reorder existing entries. Allow empty entries in this array.
Reviewed-by: Joel Stanley <[email protected]>
Signed-off-by: Jeremy Kerr <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Tested-by: Joel Stanley <[email protected]>
Signed-off-by: Stephen Boyd <[email protected]>
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sam9x60_frac_pll_compute_mul_frac() can't return zero. Remove the check
against zero to reflect this.
Fixes: 43b1bb4a9b3e ("clk: at91: clk-sam9x60-pll: re-factor to support plls with multiple outputs")
Reported-by: Dan Carpenter <[email protected]>
Signed-off-by: Claudiu Beznea <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Stephen Boyd <[email protected]>
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Field regmap of struct visconti_pll_provider is never used. Remove it.
Signed-off-by: Dario Binacchi <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Acked-by: Nobuhiro Iwamatsu <[email protected]>
Signed-off-by: Stephen Boyd <[email protected]>
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REGMAP is a hidden (not user visible) symbol. Users cannot set it
directly thru "make *config", so drivers should select it instead of
depending on it if they need it.
Consistently using "select" or "depends on" can also help reduce
Kconfig circular dependency issues.
Therefore, change the use of "depends on REGMAP" to "select REGMAP".
Fixes: 3a49afb84ca0 ("clk: enable hi655x common clk automatically")
Signed-off-by: Randy Dunlap <[email protected]>
Cc: Riku Voipio <[email protected]>
Cc: Stephen Boyd <[email protected]>
Cc: Michael Turquette <[email protected]>
Cc: [email protected]
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Stephen Boyd <[email protected]>
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Since commit 8b41fc4454e ("kbuild: create modules.builtin without
Makefile.modbuiltin or tristate.conf"), MODULE_LICENSE declarations
are used to identify modules. As a consequence, uses of the macro
in non-modules will cause modprobe to misidentify their containing
object file as a module when it is not (false positives), and modprobe
might succeed rather than failing with a suitable error message.
So remove it in the files in this commit, none of which can be built as
modules.
Signed-off-by: Nick Alcock <[email protected]>
Suggested-by: Luis Chamberlain <[email protected]>
Cc: Luis Chamberlain <[email protected]>
Cc: [email protected]
Cc: [email protected]
Cc: Hitomi Hasegawa <[email protected]>
Cc: Michael Turquette <[email protected]>
Cc: Stephen Boyd <[email protected]>
Cc: [email protected]
Link: https://lore.kernel.org/r/[email protected]
Acked-by: Conor Dooley <[email protected]>
Reviewed-by: Conor Dooley <[email protected]>
Signed-off-by: Stephen Boyd <[email protected]>
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Since commit 8b41fc4454e ("kbuild: create modules.builtin without
Makefile.modbuiltin or tristate.conf"), MODULE_LICENSE declarations
are used to identify modules. As a consequence, uses of the macro
in non-modules will cause modprobe to misidentify their containing
object file as a module when it is not (false positives), and modprobe
might succeed rather than failing with a suitable error message.
So remove it in the files in this commit, none of which can be built as
modules.
Signed-off-by: Nick Alcock <[email protected]>
Suggested-by: Luis Chamberlain <[email protected]>
Cc: Luis Chamberlain <[email protected]>
Cc: [email protected]
Cc: [email protected]
Cc: Hitomi Hasegawa <[email protected]>
Cc: Michael Turquette <[email protected]>
Cc: Stephen Boyd <[email protected]>
Cc: Florian Fainelli <[email protected]>
Cc: Ray Jui <[email protected]>
Cc: Scott Branden <[email protected]>
Cc: [email protected]
Cc: [email protected]
Cc: [email protected]
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Stephen Boyd <[email protected]>
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Add main gate clocks for controlling AUD and HSI CMUs:
- gout_aud_cmu_aud_pclk
- gout_hsi_cmu_hsi_pclk
Those clocks were marked as CLK_IGNORE_UNUSED, as system hangs on
boot otherwise.
While at it, add missing PPMU (Performance Profiling Monitor Unit)
clocks for CMU_HSI.
Signed-off-by: Sam Protsenko <[email protected]>
Reviewed-by: Chanho Park <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Krzysztof Kozlowski <[email protected]>
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CMU_G3D clock domain provides clocks for Mali-G52 GPU and bus clocks for
BLK_G3D.
This patch adds next clocks:
- bus clocks in CMU_TOP for CMU_G3D
- all internal CMU_G3D clocks
- leaf clocks for GPU, TZPC (TrustZone Protection Controller) and
SysReg
G3D_CMU_G3D clock was marked as CLK_IGNORE_UNUSED, as system hangs on
boot otherwise.
Reviewed-by: Chanho Park <[email protected]>
Signed-off-by: Sam Protsenko <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Krzysztof Kozlowski <[email protected]>
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