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2023-10-05clk: renesas: rzg2l: Fix computation formulaClaudiu Beznea1-6/+6
According to the hardware manual for RZ/G2L (r01uh0914ej0130-rzg2l-rzg2lc.pdf), the computation formula for PLL rate is as follows: Fout = ((m + k/65536) * Fin) / (p * 2^s) and k has values in the range [-32768, 32767]. Dividing k by 65536 with integer arithmetic gives zero all the time, causing slight differences b/w what has been set vs. what is displayed. Thus, get rid of this and decompose the formula before dividing k by 65536. Fixes: ef3c613ccd68a ("clk: renesas: Add CPG core wrapper for RZ/G2L SoC") Signed-off-by: Claudiu Beznea <[email protected]> Reviewed-by: Geert Uytterhoeven <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Geert Uytterhoeven <[email protected]>
2023-10-05clk: renesas: rzg2l: Trust value returned by hardwareClaudiu Beznea1-7/+1
The onitial value of the CPG_PL2SDHI_DSEL bits 0..1 or 4..6 is 01b. The hardware user's manual (r01uh0914ej0130-rzg2l-rzg2lc.pdf) specifies that setting 0 is prohibited. Hence rzg2l_cpg_sd_clk_mux_get_parent() should just read CPG_PL2SDHI_DSEL, trust the value, and return the proper clock parent index based on the value read. Fixes: eaff33646f4cb ("clk: renesas: rzg2l: Add SDHI clk mux support") Signed-off-by: Claudiu Beznea <[email protected]> Reviewed-by: Geert Uytterhoeven <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Geert Uytterhoeven <[email protected]>
2023-10-05clk: renesas: rzg2l: Lock around writes to mux registerClaudiu Beznea2-11/+14
The SD MUX output (SD0) is further divided by 4 in G2{L,UL}. The divided clock is SD0_DIV4. SD0_DIV4 is registered with CLK_SET_RATE_PARENT which means a rate request for it is propagated to the MUX and could reach rzg2l_cpg_sd_clk_mux_set_parent() concurrently with the users of SD0. Add proper locking to avoid concurrent accesses on SD MUX set rate registers. Fixes: eaff33646f4cb ("clk: renesas: rzg2l: Add SDHI clk mux support") Signed-off-by: Claudiu Beznea <[email protected]> Reviewed-by: Geert Uytterhoeven <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Geert Uytterhoeven <[email protected]>
2023-10-05clk: renesas: rzg2l: Wait for status bit of SD mux before continuingClaudiu Beznea1-7/+10
The hardware user manual for RZ/G2L (r01uh0914ej0130-rzg2l-rzg2lc.pdf, chapter 7.4.7 Procedure for Switching Clocks by the Dynamic Switching Frequency Selectors) specifies that we need to check CPG_PL2SDHI_DSEL for SD clock switching status. Fixes: eaff33646f4cb ("clk: renesas: rzg2l: Add SDHI clk mux support") Signed-off-by: Claudiu Beznea <[email protected]> Reviewed-by: Geert Uytterhoeven <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Geert Uytterhoeven <[email protected]>
2023-10-05clk: renesas: rcar-gen3: Extend SDnH divider tableDirk Behme1-1/+14
The clock dividers might be used with clock stop bit enabled or not. Current tables only support recommended values from the datasheet. This might result in warnings like below because no valid clock divider is found. Resulting in a 0 divider. There are Renesas ARM Trusted Firmware version out there which e.g. configure 0x201 (shifted logical right by 2: 0x80) and with this match the added { STPnHCK | 0, 1 }: https://github.com/renesas-rcar/arm-trusted-firmware/blob/rcar_gen3_v2.3/drivers/renesas/rcar/emmc/emmc_init.c#L108 ------------[ cut here ]------------ sd1h: Zero divisor and CLK_DIVIDER_ALLOW_ZERO not set WARNING: CPU: 1 PID: 1 at drivers/clk/clk-divider.c:141 divider_recalc_rate+0x48/0x70 Modules linked in: CPU: 1 PID: 1 Comm: swapper/0 Not tainted 6.1.52 #1 Hardware name: Custom board based on r8a7796 (DT) pstate: 40000005 (nZcv daif -PAN -UAO -TCO -DIT -SSBS BTYPE=--) pc : divider_recalc_rate+0x48/0x70 ... ------------[ cut here ]------------ Fixes: bb6d3fa98a41 ("clk: renesas: rcar-gen3: Switch to new SD clock handling") Signed-off-by: Dirk Behme <[email protected]> [wsa: extended the table to 5 entries, added comments, reword commit message a little] Signed-off-by: Wolfram Sang <[email protected]> Tested-by: Dirk Behme <[email protected]> Reviewed-by: Geert Uytterhoeven <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Geert Uytterhoeven <[email protected]>
2023-10-04clk: imx: imx8qm/qxp: add more resources to whitelistPeng Fan2-0/+5
Add CAN_1/2 support for i.MX8QM Add M4_0, PI_0_PWM_0 and PI_0_I2C_0 for i.MX8QXP Signed-off-by: Peng Fan <[email protected]> Reviewed-by: Abel Vesa <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Abel Vesa <[email protected]>
2023-10-04clk: imx: scu: ignore clks not owned by Cortex-A partitionPeng Fan1-0/+20
Not register clks that not owned to current partition. CPU resources are specical resources, it is assigned in ATF, not non-secure OS, but we still need to allow cpu freq, so return true for non-secure OS for cpu resources. Otherwise there will be error log if the resources are owned by current partition: [ 19.387291] cm40_i2c_div: failed to attached the power domain -2 [ 19.389305] cm40_lpuart_div: failed to attached the power domain -2 Signed-off-by: Peng Fan <[email protected]> Reviewed-by: Abel Vesa <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Abel Vesa <[email protected]>
2023-10-04clk: imx8: remove MLB supportPeng Fan5-7/+3
MLB was de-featured, so drop MLB clk for i.MX8QM/QXP/DXL Signed-off-by: Peng Fan <[email protected]> Reviewed-by: Abel Vesa <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Abel Vesa <[email protected]>
2023-10-04clk: imx: imx8qm-rsrc: drop VPU_UART/VPUCOREPeng Fan1-2/+0
IMX_SC_R_VPU_UART and IMX_SC_R_VPUCORE was used in i.MX8QM A0 which not for mass production. i.MX8QM B0 not have the two resources, so drop it. Signed-off-by: Peng Fan <[email protected]> Reviewed-by: Abel Vesa <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Abel Vesa <[email protected]>
2023-10-04clk: imx: imx8qxp: correct the enet clocks for i.MX8DXLShenwei Wang1-2/+9
The SC_PM_CLK_MISC0 clock is not available for the resources of ENET0/1 on i.MX8DXL. Using the clock device compatible string to identify the platform and only initialize the enetX_rgmii_rx_clk clock for non i.MX8DXL platform. Signed-off-by: Shenwei Wang <[email protected]> Reviewed-by: Ranjani Vaidyanathan <[email protected]> Reviewed-by: Jacky Bai <[email protected]> Acked-by: Jason Liu <[email protected]> Signed-off-by: Peng Fan <[email protected]> Reviewed-by: Abel Vesa <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Abel Vesa <[email protected]>
2023-10-04clk: imx: imx8qxp: Fix elcdif_pll clockRobert Chiras1-1/+1
Move the elcdif_pll clock initialization before the lcd_clk, since the elcdif_clk needs to be initialized ahead of lcd_clk, being its parent. This change fixes issues with the LCD clocks during suspend/resume. Fixes: babfaa9556d7 ("clk: imx: scu: add more scu clocks") Suggested-by: Ranjani Vaidyanathan <[email protected]> Acked-by: Laurentiu Palcu <[email protected]> Signed-off-by: Robert Chiras <[email protected]> Signed-off-by: Peng Fan <[email protected]> Reviewed-by: Abel Vesa <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Abel Vesa <[email protected]>
2023-10-04clk: imx: imx8dxl-rsrc: keep sorted in the ascending orderViorel Suman1-1/+1
Entries in imx8dxl_clk_scu_rsrc_table must be kept in the ascending order, and IMX_SC_R_M4_0_UART < IMX_SC_R_M4_0_I2C. Fixes: 036a4b4b4dfa ("clk: imx: Add imx8dxl clk driver") Signed-off-by: Viorel Suman <[email protected]> Signed-off-by: Peng Fan <[email protected]> Reviewed-by: Abel Vesa <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Abel Vesa <[email protected]>
2023-10-04clk: imx: imx6sx: Allow a different LCDIF1 clock parentFabio Estevam1-3/+11
It is not a good idea to hardcode the LCDIF1 parent inside the clock driver because some users may want to use a different clock parent for LCDIF1. One of the reasons could be related to EMI tests. Remove the harcoded LCDIF1 parent when the LCDIF1 parent is described via devicetree. Old dtb's that do not describe the LCDIF1 parent via devicetree will use the same PLL5 clock as parent to keep the original behavior. Signed-off-by: Fabio Estevam <[email protected]> Reviewed-by: Abel Vesa <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Abel Vesa <[email protected]>
2023-10-04clk: imx: imx8mq: correct error handling pathPeng Fan1-7/+10
Avoid memory leak in error handling path. It does not make much sense for the SoC without clk driver, to make program behavior correct, let's fix it. Fixes: b80522040cd3 ("clk: imx: Add clock driver for i.MX8MQ CCM") Reported-by: kernel test robot <[email protected]> Reported-by: Dan Carpenter <[email protected]> Closes: https://lore.kernel.org/r/[email protected]/ Signed-off-by: Peng Fan <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Abel Vesa <[email protected]>
2023-10-04clk: imx: imx8: Simplify clk_imx_acm_detach_pm_domains()Christophe JAILLET1-5/+3
The return value of clk_imx_acm_detach_pm_domains() is never used. Simplify the code and turn it into a void function. Reviewed-by: Peng Fan <[email protected]> Signed-off-by: Christophe JAILLET <[email protected]> Signed-off-by: Abel Vesa <[email protected]>
2023-10-04clk: imx: imx8: Add a message in case of ↵Christophe JAILLET1-2/+1
devm_clk_hw_register_mux_parent_data_table() error If devm_clk_hw_register_mux_parent_data_table() fails, we branch to the error handling path and imx_check_clk_hws() is never called. Actually, imx_check_clk_hws() is a no-op because values in 'hws' are either valid, either NULL. Move the call to imx_check_clk_hws() in the error handling path, so that an error is logged. Fixes: d3a0946d7ac9 ("clk: imx: imx8: add audio clock mux driver") Reviewed-by: Peng Fan <[email protected]> Signed-off-by: Christophe JAILLET <[email protected]> Signed-off-by: Abel Vesa <[email protected]>
2023-10-04clk: imx: imx8: Fix an error handling path in imx8_acm_clk_probe()Christophe JAILLET1-3/+6
If an error occurs after a successful clk_imx_acm_attach_pm_domains() call, it must be undone. Add an explicit error handling path, re-order the code and add the missing clk_imx_acm_detach_pm_domains() call. Fixes: d3a0946d7ac9 ("clk: imx: imx8: add audio clock mux driver") Reviewed-by: Peng Fan <[email protected]> Signed-off-by: Christophe JAILLET <[email protected]> Signed-off-by: Abel Vesa <[email protected]>
2023-10-04clk: imx: imx8: Fix an error handling path if ↵Christophe JAILLET1-0/+1
devm_clk_hw_register_mux_parent_data_table() fails If a devm_clk_hw_register_mux_parent_data_table() call fails, it is likely that the probe should fail with an error code. Set 'ret' before leaving the function. Fixes: d3a0946d7ac9 ("clk: imx: imx8: add audio clock mux driver") Reviewed-by: Peng Fan <[email protected]> Signed-off-by: Christophe JAILLET <[email protected]> Signed-off-by: Abel Vesa <[email protected]>
2023-10-04clk: imx: imx8: Fix an error handling path in clk_imx_acm_attach_pm_domains()Christophe JAILLET1-2/+4
If a dev_pm_domain_attach_by_id() call fails, previously allocated resources need to be released. Fixes: d3a0946d7ac9 ("clk: imx: imx8: add audio clock mux driver") Reviewed-by: Peng Fan <[email protected]> Signed-off-by: Christophe JAILLET <[email protected]> Signed-off-by: Abel Vesa <[email protected]>
2023-10-04clk: imx: Select MXC_CLK for CLK_IMX8QXPAbel Vesa1-0/+1
If the i.MX8QXP clock provider is built-in but the MXC_CLK is built as module, build fails: aarch64-linux-ld: drivers/clk/imx/clk-imx8-acm.o: in function `imx8_acm_clk_probe': clk-imx8-acm.c:(.text+0x3d0): undefined reference to `imx_check_clk_hws' Fix that by selecting MXC_CLK in case of CLK_IMX8QXP. Fixes: c2cccb6d0b33 ("clk: imx: add imx8qxp clk driver") Closes: https://lore.kernel.org/all/[email protected]/ Reported-by: Randy Dunlap <[email protected]> Reviewed-by: Peng Fan <[email protected]> Acked-by: Randy Dunlap <[email protected]> Tested-by: Randy Dunlap <[email protected]> Signed-off-by: Abel Vesa <[email protected]>
2023-09-27clk: meson: S4: add support for Amlogic S4 SoC peripheral clock controllerYu Tu4-0/+3881
Add the peripherals clock controller driver in the S4 SoC family. [jbrunet: remove extra new line at end of s4-peripherals.h] Signed-off-by: Yu Tu <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Jerome Brunet <[email protected]>
2023-09-27clk: meson: S4: add support for Amlogic S4 SoC PLL clock driverYu Tu4-0/+918
Add the S4 PLL clock controller driver in the S4 SoC family. Signed-off-by: Yu Tu <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Jerome Brunet <[email protected]>
2023-09-26clk: renesas: r8a7795: Constify r8a7795_*_clksMarek Vasut1-2/+2
Make r8a7795_core_clks and r8a7795_mod_clks arrays const and align them with the other clock tables in other *cpg-mssr.c . No functional change. Signed-off-by: Marek Vasut <[email protected]> Reviewed-by: Geert Uytterhoeven <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Geert Uytterhoeven <[email protected]>
2023-09-20clk: qcom: gcc-sm8150: Fix gcc_sdcc2_apps_clk_srcDanila Tikhonov1-1/+1
Set .flags = CLK_OPS_PARENT_ENABLE to fix "gcc_sdcc2_apps_clk_src: rcg didn't update its configuration" error. Fixes: 2a1d7eb854bb ("clk: qcom: gcc: Add global clock controller driver for SM8150") Tested-by: Arseniy Velikanov <[email protected]> Signed-off-by: Danila Tikhonov <[email protected]> Reviewed-by: Konrad Dybcio <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Bjorn Andersson <[email protected]>
2023-09-20Merge branch '[email protected]' into clk-for-6.7Bjorn Andersson4-0/+2928
Merge the SM4450 RPMHCC and GCC through a topic branch, to allow reuse of the defines from the DeviceTree binding in the DeviceTree source.
2023-09-20clk: qcom: Add GCC driver support for SM4450Ajit Pandey3-0/+2907
Add Global Clock Controller (GCC) support for SM4450 platform. Signed-off-by: Ajit Pandey <[email protected]> Reviewed-by: Dmitry Baryshkov <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Bjorn Andersson <[email protected]>
2023-09-20clk: qcom: rpmh: Add RPMH clocks support for SM4450Ajit Pandey1-0/+21
Add support for RPMH clocks for SM4450 platform. Signed-off-by: Ajit Pandey <[email protected]> Reviewed-by: Dmitry Baryshkov <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Bjorn Andersson <[email protected]>
2023-09-20clk: qcom: mmcc-msm8974: remove ocmemcx_ahb_clkLuca Weiss1-18/+0
According to a commit in the 3.4 vendor kernel sources[0] the ocmemcx_ahb_clk clock "is controlled by RPM and should not be touched by APPS.". [0] https://git.codelinaro.org/clo/la/kernel/msm/-/commit/37df5f2d91b4d5768b37fcaacaeea958dd683ebc And indeed, when using MDSS+GPU+OCMEM on MSM8226 and not using clk_ignore_unused, when Linux tries to disable the clock the device crashes and reboots. And since there's also no evidence of this clock in msm8974 vendor kernel sources, remove the clock for msm8226 and msm8974. Fixes: d8b212014e69 ("clk: qcom: Add support for MSM8974's multimedia clock controller (MMCC)") Signed-off-by: Luca Weiss <[email protected]> Reviewed-by: Konrad Dybcio <[email protected]> Link: https://lore.kernel.org/r/20230902-msm8226-ocmemcx_ahb_clk-remove-v1-1-8124dbde83b9@z3ntu.xyz Signed-off-by: Bjorn Andersson <[email protected]>
2023-09-20clk: scmi: Add support for .is_enabled clk_opsCristian Marussi1-3/+20
Add support for .is_enabled atomic clk_ops using the related SCMI clock operation in atomic mode, if available. Note that the .is_enabled callback will be supported by this SCMI clock driver only if the configured underlying SCMI transport does support atomic operations. CC: Michael Turquette <[email protected]> CC: Stephen Boyd <[email protected]> CC: [email protected] Signed-off-by: Cristian Marussi <[email protected]> Acked-by: Stephen Boyd <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Sudeep Holla <[email protected]>
2023-09-20firmware: arm_scmi: Simplify enable/disable clock operationsCristian Marussi1-4/+7
SCMI clock enable/disable operations come in 2 different flavours which simply just differ in how the underlying SCMI transactions is carried on: atomic or not. Currently we expose such SCMI operations through 2 distinctly named wrappers, that, in turn, are wrapped into another couple of similarly and distinctly named callbacks inside SCMI clock driver user. Reduce the churn of duplicated wrappers by adding a param to SCMI clock enable/disable operations to ask for atomic operation while removing the _atomic version of such operations. No functional change. CC: Michael Turquette <[email protected]> CC: Stephen Boyd <[email protected]> CC: [email protected] Signed-off-by: Cristian Marussi <[email protected]> Acked-by: Stephen Boyd <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Sudeep Holla <[email protected]>
2023-09-20clk: qcom: mmcc-msm8998: Fix the SMMU GDSCKonrad Dybcio1-1/+3
The SMMU GDSC doesn't have to be ALWAYS-ON and shouldn't feature the HW_CTRL flag (it's separate from hw_ctrl_addr). In addition to that, it should feature a cxc entry for bimc_smmu_axi_clk and be marked as votable. Fix all of these issues. Fixes: d14b15b5931c ("clk: qcom: Add MSM8998 Multimedia Clock Controller (MMCC) driver") Signed-off-by: Konrad Dybcio <[email protected]> Reviewed-by: Jeffrey Hugo <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Bjorn Andersson <[email protected]>
2023-09-20clk: qcom: mmcc-msm8998: Don't check halt bit on some branch clksKonrad Dybcio1-0/+3
Some branch clocks are governed externally and we're only supposed to send a request concerning their shutdown, not actually ensure it happens. Use the BRANCH_HALT_SKIP define to skip checking the halt bit. Fixes: d14b15b5931c ("clk: qcom: Add MSM8998 Multimedia Clock Controller (MMCC) driver") Reviewed-by: Jeffrey Hugo <[email protected]> Signed-off-by: Konrad Dybcio <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Bjorn Andersson <[email protected]>
2023-09-19clk: qcom: clk-rcg2: Fix clock rate overflow for high parent frequenciesDevi Priya1-10/+4
If the parent clock rate is greater than unsigned long max/2 then integer overflow happens when calculating the clock rate on 32-bit systems. As RCG2 uses half integer dividers, the clock rate is first being multiplied by 2 which will overflow the unsigned long max value. Hence, replace the common pattern of doing 64-bit multiplication and then a do_div() call with simpler mult_frac call. Fixes: bcd61c0f535a ("clk: qcom: Add support for root clock generators (RCGs)") Signed-off-by: Devi Priya <[email protected]> Reviewed-by: Marijn Suijten <[email protected]> Link: https://lore.kernel.org/r/[email protected] [bjorn: Also drop unnecessary {} around single statements] Signed-off-by: Bjorn Andersson <[email protected]>
2023-09-19clk: qcom: gcc-msm8996: Remove RPM bus clocksKonrad Dybcio1-232/+5
The GCC driver contains clocks that are owned (meaning configured and scaled) by the RPM core. Remove them from Linux to stop interjecting the RPM's logic. Fixes: b1e010c0730a ("clk: qcom: Add MSM8996 Global Clock Control (GCC) driver") Signed-off-by: Konrad Dybcio <[email protected]> Reviewed-by: Dmitry Baryshkov <[email protected]> Tested-by: Dmitry Baryshkov <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Bjorn Andersson <[email protected]>
2023-09-19clk: qcom: ipq5332: Drop set rate parent from gpll0 dependent clocksVaradarajan Narayanan1-2/+0
IPQ5332's GPLL0's nominal/turbo frequency is 800MHz. This must not be scaled based on the requirement of dependent clocks. Hence remove the CLK_SET_RATE_PARENT flag. Fixes: 3d89d52970fd ("clk: qcom: add Global Clock controller (GCC) driver for IPQ5332 SoC") Signed-off-by: Varadarajan Narayanan <[email protected]> Reviewed-by: Kathiravan T <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Bjorn Andersson <[email protected]>
2023-09-19Merge branch '[email protected]' into clk-for-6.7Bjorn Andersson5-0/+3603
Merge the SM8550 camera clock controller patches through a topic branch, to make them available for the DeviceTree source as well.
2023-09-19clk: qcom: camcc-sm8550: Add support for qdss, sleep and xo clocksJagadeesh Kona1-0/+181
Add support for camera qdss, sleep and xo clocks. Co-developed-by: Taniya Das <[email protected]> Signed-off-by: Taniya Das <[email protected]> Signed-off-by: Jagadeesh Kona <[email protected]> Reviewed-by: Dmitry Baryshkov <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Bjorn Andersson <[email protected]>
2023-09-19clk: qcom: camcc-sm8550: Add camera clock controller driver for SM8550Jagadeesh Kona3-0/+3391
Add support for the camera clock controller for camera clients to be able to request for camcc clocks on SM8550 platform. Co-developed-by: Taniya Das <[email protected]> Signed-off-by: Taniya Das <[email protected]> Signed-off-by: Jagadeesh Kona <[email protected]> Reviewed-by: Konrad Dybcio <[email protected]> Reviewed-by: Dmitry Baryshkov <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Bjorn Andersson <[email protected]>
2023-09-19clk: qcom: clk-alpha-pll: Add support for lucid ole pll configureJagadeesh Kona2-0/+31
Lucid ole pll has as extra RINGOSC_CAL_L field in L register in addition to the fields that are part of lucid evo pll, hence add support for lucid ole pll configure function to configure the ole plls. Signed-off-by: Jagadeesh Kona <[email protected]> Reviewed-by: Dmitry Baryshkov <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Bjorn Andersson <[email protected]>
2023-09-18clk: renesas: r9a06g032: Name anonymous structsRalph Siemsen1-30/+33
Clarify the content of the r9a06g032_clkdesc structure by naming the remaining anonymous structures defined inside. Renaming each field and updating the doc then becomes necessary in order to avoid name duplications and kdoc warnings. Signed-off-by: Ralph Siemsen <[email protected]> Reviewed-by: Miquel Raynal <[email protected]> Reviewed-by: Geert Uytterhoeven <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Geert Uytterhoeven <[email protected]>
2023-09-18clk: renesas: r9a06g032: Fix kerneldoc warningRalph Siemsen1-0/+1
Mention the 'dual' structure in the kdoc. This fixes the following W=1 warning during build: > drivers/clk/renesas/r9a06g032-clocks.c:119: warning: Function parameter or member 'dual' not described in 'r9a06g032_clkdesc' Reported-by: kernel test robot <[email protected]> Closes: https://lore.kernel.org/oe-kbuild-all/[email protected]/ Signed-off-by: Ralph Siemsen <[email protected]> Reviewed-by: Miquel Raynal <[email protected]> Reviewed-by: Geert Uytterhoeven <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Geert Uytterhoeven <[email protected]>
2023-09-18clk: renesas: rzg2l: Use u32 for flag and mux_flagsClaudiu Beznea1-2/+2
flag and mux_flags are intended to keep bit masks. Use u32 type for it. Signed-off-by: Claudiu Beznea <[email protected]> Reviewed-by: Geert Uytterhoeven <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Geert Uytterhoeven <[email protected]>
2023-09-18clk: renesas: rzg2l: Use FIELD_GET() for PLL register fieldsClaudiu Beznea1-5/+5
Use FIELD_GET() for PLL register fields. This is its purpose. Signed-off-by: Claudiu Beznea <[email protected]> Reviewed-by: Geert Uytterhoeven <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Geert Uytterhoeven <[email protected]>
2023-09-18clk: renesas: rzg2l: Simplify the logic in rzg2l_mod_clock_endisable()Claudiu Beznea1-3/+2
The bitmask << 16 is anyway set on both branches of if thus move it before the if and set the lower bits of registers only in case clock is enabled. Signed-off-by: Claudiu Beznea <[email protected]> Reviewed-by: Geert Uytterhoeven <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Geert Uytterhoeven <[email protected]>
2023-09-18clk: renesas: rzg2l: Use core->name for clock nameClaudiu Beznea1-1/+1
core->name already contains the clock name thus, there is no need to check the GET_SHIFT(core->conf) to decide on it. Signed-off-by: Claudiu Beznea <[email protected]> Reviewed-by: Geert Uytterhoeven <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Geert Uytterhoeven <[email protected]>
2023-09-13clk: qcom: hfpll: Add MSM8976 PLL dataAdam Skladowski1-0/+54
Add PLL configuration for MSM8976 SoC, this SoC offers 3 HFPLL. Small cluster offers two presets for 652-902Mhz range and 902Mhz-1.47Ghz. For simplicity only add second range as smaller frequencies can be obtained via apcs divider or safe parent this also saves us a hassle of reconfiguring VCO bit and config_val. A72 and CCI cluster only use single frequency range with their outputs/post_dividers/vco_bits being static. Signed-off-by: Adam Skladowski <[email protected]> Reviewed-by: Konrad Dybcio <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Bjorn Andersson <[email protected]>
2023-09-13clk: qcom: hfpll: Allow matching pdataAdam Skladowski1-2/+3
HFPLL driver can be used to drive PLLs also on different SoCs like MSM8976 On MSM8976 each PLL gets it own different configuration, add matching pdata to driver to support multiple configurations. Signed-off-by: Adam Skladowski <[email protected]> Reviewed-by: Konrad Dybcio <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Bjorn Andersson <[email protected]>
2023-09-13clk: qcom: clk-hfpll: Configure l_val in init when requiredAdam Skladowski2-0/+5
Add support for pre-configuring default frequency multiplier, this appears to be required on some platforms like MSM8976. Without configuring L_VAL device reboots when trying to bring PLL up. Signed-off-by: Adam Skladowski <[email protected]> Reviewed-by: Konrad Dybcio <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Bjorn Andersson <[email protected]>
2023-09-12clk: tegra: fix error return case for recalc_rateTimo Alho1-1/+1
tegra-bpmp clocks driver makes implicit conversion of signed error code to unsigned value in recalc_rate operation. The behavior for recalc_rate, according to it's specification, should be that "If the driver cannot figure out a rate for this clock, it must return 0." Fixes: ca6f2796eef7 ("clk: tegra: Add BPMP clock driver") Signed-off-by: Timo Alho <[email protected]> Signed-off-by: Mikko Perttunen <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Stephen Boyd <[email protected]>
2023-09-11clk: si521xx: Fix regmap write accessorMarek Vasut1-3/+4
Rework the write operation such that the Byte Count register is written with a single raw i2c write outside of regmap using transfer which does specify the number of bytes to be transfered, one in this case, and which makes the expected subsequent write transfer look like address+register+data, and then make use of this method. Without this change, the Byte Count register write in probe() would succeed as it would provide the byte count as part of its write payload, but any subsequent writes would fail due to this Byte Count register programming. Such failing writes happens e.g. during resume, when restoring the regmap content. Fixes: edc12763a3a2 ("clk: si521xx: Clock driver for Skyworks Si521xx I2C PCIe clock generators") Signed-off-by: Marek Vasut <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Stephen Boyd <[email protected]>
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