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path: root/drivers/clk
AgeCommit message (Expand)AuthorFilesLines
2022-05-20clk: stm32mp13: add stm32_gate managementGabriel Fernandez3-0/+149
2022-05-20clk: stm32mp13: add stm32_mux clock managementGabriel Fernandez3-0/+114
2022-05-20clk: stm32: Introduce STM32MP13 RCC drivers (Reset Clock Controller)Gabriel Fernandez9-0/+2590
2022-05-20clk: ti: clkctrl: replace usage of found with dedicated list iterator variableJakob Koschel1-7/+6
2022-05-20clk: ti: composite: Prefer kcalloc over open coded arithmeticLen Baker1-1/+1
2022-05-19clk: mediatek: mt8173: Switch to clk_hw provider APIsChen-Yu Tsai1-5/+4
2022-05-19clk: mediatek: Switch to clk_hw provider APIsChen-Yu Tsai8-122/+123
2022-05-19clk: mediatek: Replace 'struct clk' with 'struct clk_hw'Chen-Yu Tsai94-444/+438
2022-05-19clk: mediatek: apmixed: Drop error message from clk_register() failureChen-Yu Tsai1-3/+1
2022-05-19clk: mediatek: Make mtk_clk_register_composite() staticChen-Yu Tsai2-4/+1
2022-05-19clk: qcom: rcg2: Cache CFG register updates for parked RCGsBjorn Andersson2-27/+101
2022-05-19clk: qcom: add sc8280xp GCC driverBjorn Andersson3-0/+7498
2022-05-19clk: renesas: r9a06g032: Probe possible childrenMiquel Raynal1-0/+5
2022-05-19clk: renesas: r9a06g032: Export function to set dmamuxMiquel Raynal1-1/+34
2022-05-18clk: mediatek: use en_mask as a pure div_en_maskChun-Jie Chen14-131/+127
2022-05-18clk: ingenic-tcu: Fix missing TCU clock for X1000 SoCsAidan MacDonald1-10/+25
2022-05-18clk: mediatek: update compatible string for MT7986 ethsysSam Shih1-1/+1
2022-05-18clk: ingenic: Mark critical clocks in Ingenic SoCsAidan MacDonald7-0/+76
2022-05-18clk: ingenic: Allow specifying common clock flagsAidan MacDonald2-1/+4
2022-05-18clk: ux500: fix a possible off-by-one in u8500_prcc_reset_base()Hangyu Hua1-1/+1
2022-05-17clk: at91: generated: consider range when calculating best rateCodrin Ciubotariu1-0/+4
2022-05-17clk: imx8mp: fix usb_root_clk parentPeng Fan1-1/+1
2022-05-17Revert "clk: sunxi-ng: sun6i-rtc: Add support for H6"Jernej Skrabec1-15/+0
2022-05-17clk: bcm2835: fix bcm2835_clock_choose_divStefan Wahren1-0/+1
2022-05-16clk: fixed-rate: Remove redundant if statementLi Zhengyu1-1/+1
2022-05-10clk: samsung: exynosautov9: add cmu_peric1 clock supportChanho Park1-0/+254
2022-05-10clk: samsung: exynosautov9: add cmu_peric0 clock supportChanho Park1-0/+254
2022-05-10clk: samsung: exynosautov9: add cmu_fsys2 clock supportChanho Park1-0/+69
2022-05-10clk: samsung: exynosautov9: add cmu_busmc clock supportChanho Park1-0/+55
2022-05-10clk: samsung: exynosautov9: add cmu_peris clock supportChanho Park1-0/+51
2022-05-10clk: samsung: exynosautov9: add cmu_core clock supportChanho Park1-0/+92
2022-05-10clk: samsung: add top clock support for Exynos Auto v9 SoCChanho Park2-0/+959
2022-05-07ARM: pxa: move clk register definitions to driverArnd Bergmann6-49/+196
2022-05-07ARM: pxa: move smemc register access from clk to platformArnd Bergmann5-63/+15
2022-05-07cpufreq: pxa3: move clk register access to clk driverArnd Bergmann1-0/+16
2022-05-06clk: sunxi-ng: h616: Add PLL derived 32KHz clockAndre Przywara2-1/+9
2022-05-06clk: sunxi-ng: h6-r: Add RTC gate clockAndre Przywara2-1/+6
2022-05-06clk: tegra: Update kerneldoc to match prototypesThierry Reding1-4/+4
2022-05-06clk: renesas: r9a09g011: Add eth clock and reset entriesPhil Edworthy1-5/+9
2022-05-06clk: renesas: Add RZ/V2M support using the rzg2l driverPhil Edworthy5-0/+181
2022-05-05clk: qcom: gcc-msm8976: Add modem resetAdam Skladowski1-0/+1
2022-05-05clk: qcom: gcc-msm8976: Set floor ops for SDCCAdam Skladowski1-3/+3
2022-05-05clk: renesas: rzg2l: Add support for RZ/V2M reset monitor regPhil Edworthy2-3/+17
2022-05-05clk: renesas: rzg2l: Make use of CLK_MON registers optionalPhil Edworthy4-1/+16
2022-05-05clk: renesas: rzg2l: Set HIWORD mask for all mux and dividersPhil Edworthy3-31/+19
2022-05-05clk: renesas: rzg2l: Add read only versions of the clk macrosPhil Edworthy3-6/+12
2022-05-05clk: renesas: rzg2l: Move the DEF_MUX array size calc into the macroPhil Edworthy3-22/+19
2022-05-05clk: renesas: r9a07g044: Fix OSTM1 module clock nameGeert Uytterhoeven1-1/+1
2022-05-05clk: renesas: r9a07g043: Add clock and reset entries for ADCBiju Das1-0/+6
2022-05-05clk: renesas: r9a07g043: Add TSU clock and reset entryBiju Das1-0/+6