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2023-10-18clk: mediatek: clk-mt6765: Add check for mtk_alloc_clk_dataJiasheng Jiang1-0/+6
Add the check for the return value of mtk_alloc_clk_data() in order to avoid NULL pointer dereference. Fixes: 1aca9939bf72 ("clk: mediatek: Add MT6765 clock support") Signed-off-by: Jiasheng Jiang <[email protected]> Link: https://lore.kernel.org/r/[email protected] Reviewed-by: AngeloGioacchino Del Regno <[email protected]> Signed-off-by: Stephen Boyd <[email protected]>
2023-10-18clk: npcm7xx: Fix incorrect kfreeJonathan Neuschäfer1-1/+1
The corresponding allocation is: > npcm7xx_clk_data = kzalloc(struct_size(npcm7xx_clk_data, hws, > NPCM7XX_NUM_CLOCKS), GFP_KERNEL); ... so, kfree should be applied to npcm7xx_clk_data, not npcm7xx_clk_data->hws. Fixes: fcfd14369856 ("clk: npcm7xx: add clock controller") Signed-off-by: Jonathan Neuschäfer <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Stephen Boyd <[email protected]>
2023-10-18clk: at91: remove unnecessary conditionsDan Carpenter1-7/+5
This code checks "if (parent_hw)" is non-NULL, but then it has more checks if parent_hw is non-NULL on the lines inside the if statement. It is a bit confusing. For the else statement, keep in mind that at the start of the function we checked: if (!(parent_name || parent_hw)) return ERR_PTR(-EINVAL); That check ensures that if parent_hw is NULL that means that parent_name is non-NULL. At least one must always be non-NULL. So here again, the checks inside the if statement can be removed. In the original code, it was a bit confusing and you could easily get the impression that "init.num_parents" could be zero. When we remove the unnecessary checking it's more obvious that it's always set to 1. Signed-off-by: Dan Carpenter <[email protected]> Link: https://lore.kernel.org/r/[email protected] Reviewed-by: Claudiu Beznea <[email protected]> Signed-off-by: Stephen Boyd <[email protected]>
2023-10-18clk: ti: fix double free in of_ti_divider_clk_setup()Dan Carpenter1-7/+1
The "div" pointer is freed in _register_divider() and again in of_ti_divider_clk_setup(). Delete the free in _register_divider() Fixes: fbbc18591585 ("clk: ti: divider: cleanup _register_divider and ti_clk_get_div_table") Signed-off-by: Dan Carpenter <[email protected]> Link: https://lore.kernel.org/r/[email protected] Reviewed-by: Tony Lindgren <[email protected]> Signed-off-by: Stephen Boyd <[email protected]>
2023-10-18clk: keystone: pll: fix a couple NULL vs IS_ERR() checksDan Carpenter1-6/+9
The clk_register_divider() and clk_register_mux() functions returns error pointers on error but this code checks for NULL. Fix that. Fixes: b9e0d40c0d83 ("clk: keystone: add Keystone PLL clock driver") Signed-off-by: Dan Carpenter <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Stephen Boyd <[email protected]>
2023-10-18clk: ralink: mtmips: quiet unused variable warningSergio Paracuellos1-15/+5
When CONFIG_OF is disabled then the matching table is not referenced and the following warning appears: drivers/clk/ralink/clk-mtmips.c:821:34: warning: unused variable 'mtmips_of_match' [-Wunused-const-variable] 821 | static const struct of_device_id mtmips_of_match[] = { | ^ There are two match tables in the driver: one for the clock driver and the other for the reset driver. The only difference between them is that the clock driver uses 'data' and does not have 'ralink,rt2880-reset' compatible. Both just can be merged into a single one just by adding the compatible 'ralink,rt2880-reset' entry to 'mtmips_of_match[]', which will allow it to be used for 'mtmips_clk_driver' (which doesn't use the data) as well as for 'mtmips_clk_init()' (which doesn't need get called for 'ralink,rt2880-reset'). Doing in this way ensures that 'CONFIG_OF' is not disabled anymore so the above warning disapears. Fixes: 6f3b15586eef ("clk: ralink: add clock and reset driver for MTMIPS SoCs") Reported-by: kernel test robot <[email protected]> Closes: https://lore.kernel.org/oe-kbuild-all/[email protected]/ Suggested-by: Arnd Bergmann <[email protected]> Signed-off-by: Sergio Paracuellos <[email protected]> Link: https://lore.kernel.org/r/[email protected] Reviewed-by: Nathan Chancellor <[email protected]> Signed-off-by: Stephen Boyd <[email protected]>
2023-10-18Merge tag 'omap-fixes-audio-clock-and-modem-signed' of ↵Arnd Bergmann2-0/+9
git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap into arm/fixes Few minor fixes for omaps Regression fixes for mcbsp audio clock, and for ams-delta modem. And two warning fixes. These all can be merged whenever and are not urgent by any means. Feel free to defer to the merge window unless other fixes are still pending. * tag 'omap-fixes-audio-clock-and-modem-signed' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap: clk: ti: Fix missing omap5 mcbsp functional clock and aliases clk: ti: Fix missing omap4 mcbsp functional clock and aliases ARM: OMAP1: ams-delta: Fix MODEM initialization failure ARM: OMAP: timer32K: fix all kernel-doc warnings ARM: omap2: fix a debug printk Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Arnd Bergmann <[email protected]>
2023-10-16Merge tag 'scmi-updates-6.7' of ↵Arnd Bergmann1-8/+88
git://git.kernel.org/pub/scm/linux/kernel/git/sudeep.holla/linux into soc/drivers Arm SCMI updates for v6.7 Main additions this time include: 1. SCMI v3.2 clock configuration support: This helps to retrieve the enabled state of a clock as well as allow to set OEM specific clock configurations. 2. Support for generic performance scaling(DVFS): The current SCMI DVFS support is limited to the CPUs in the kernel. This extension enables it to used for all kind of devices and not only for the CPUs. It updates the SCMI cpufreq to utilize the power domain bindings. It also adds a more generic SCMI performance domain based on the genpd framework that as be used for all the non-CPU devices. 3. Extend the generic performance scaling(DVFS) support for firmware driver OPPs: Consumer drivers for devices that are attached to the SCMI performance domain can't make use of the current OPP library to scale performance as the OPPs are firmware driven and often obtained from the firmware rather than the device tree. These changes extend the generic OPP and genpd PM domain frameworks to identify and utilise these firmware driven OPPs. 4. SCMI v3.2 clock parent support: This enables the support for discovering and changing parent clocks and extending the SCMI clk driver to use the same. 5. Qualcom SMC/HVC transport support: The Qualcomm virtual platforms require capability id in the hypervisor call to identify which doorbell to assert when supporting multiple SMC/HVC based SCMI transport channels. Extra parameter is added to support the same and the same is obtained at the fixed address in the shared memory which is initialised by the firmware. 6. Move the existing SCMI power domain driver under drivers/pmdomain Apart from the above main changes, it also include couple of minor fixes and cosmetic reworks. * tag 'scmi-updates-6.7' of git://git.kernel.org/pub/scm/linux/kernel/git/sudeep.holla/linux: (37 commits) firmware: arm_scmi: Add qcom smc/hvc transport support dt-bindings: arm: Add new compatible for smc/hvc transport for SCMI firmware: arm_scmi: Convert u32 to unsigned long to align with arm_smccc_1_1_invoke() clk: scmi: Add support for clock {set,get}_parent firmware: arm_scmi: Add support for clock parents clk: scmi: Free scmi_clk allocated when the clocks with invalid info are skipped firmware: arm_scpi: Use device_get_match_data() firmware: arm_scmi: Add generic OPP support to the SCMI performance domain firmware: arm_scmi: Specify the performance level when adding an OPP firmware: arm_scmi: Simplify error path in scmi_dvfs_device_opps_add() OPP: Extend support for the opp-level beyond required-opps OPP: Switch to use dev_pm_domain_set_performance_state() OPP: Extend dev_pm_opp_data with a level OPP: Add dev_pm_opp_add_dynamic() to allow more flexibility PM: domains: Implement the ->set_performance_state() callback for genpd PM: domains: Introduce dev_pm_domain_set_performance_state() firmware: arm_scmi: Rename scmi_{msg_,}clock_config_{get,set}_{2,21} firmware: arm_scmi: Do not use !! on boolean when setting msg->flags firmware: arm_scmi: Move power-domain driver to the pmdomain dir pmdomain: arm: Add the SCMI performance domain ... Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Arnd Bergmann <[email protected]>
2023-10-13clk: ti: Fix missing omap5 mcbsp functional clock and aliasesTony Lindgren1-0/+4
We are using a wrong mcbsp functional clock. The interconnect target module driver provided clock for mcbsp is not same as the mcbsp functional clock known as the gfclk main_clk. The mcbsp functional clocks for mcbsp should have been added before we dropped the legacy platform data. Additionally we are also missing the clock aliases for the clocks used by the audio driver if reparenting is needed. This causes audio driver errors like "CLKS: could not clk_get() prcm_fck" for mcbsp as reported by Andreas. The mcbsp clock aliases too should have been added before we dropped the legacy platform data. Let's add the clocks and aliases with a single patch to fix the issue similar to omap4. On omap5, there is no mcbsp4 instance on the l4_per interconnect. Fixes: b1da0fa21bd1 ("ARM: OMAP2+: Drop legacy platform data for omap5 mcbsp") Cc: H. Nikolaus Schaller <[email protected]> Reported-by: Andreas Kemnade <[email protected]> Reported-by: Péter Ujfalusi <[email protected]> Acked-by: Stephen Boyd <[email protected]> Signed-off-by: Tony Lindgren <[email protected]>
2023-10-13clk: ti: Fix missing omap4 mcbsp functional clock and aliasesTony Lindgren1-0/+5
We are using a wrong mcbsp functional clock. The interconnect target module driver provided clock for mcbsp is not same as the mcbsp functional clock known as the gfclk main_clk. The mcbsp functional clocks for mcbsp should have been added before we dropped the legacy platform data. Additionally we are also missing the clock aliases for the clocks used by the audio driver if reparenting is needed. This causes audio driver errors like "CLKS: could not clk_get() prcm_fck" for mcbsp as reported by Andreas. The mcbsp clock aliases too should have been added before we dropped the legacy platform data. Let's add the clocks and aliases with a single patch to fix the issue. Fixes: 349355ce3a05 ("ARM: OMAP2+: Drop legacy platform data for omap4 mcbsp") Reported-by: Andreas Kemnade <[email protected]> Reported-by: Péter Ujfalusi <[email protected]> Acked-by: Stephen Boyd <[email protected]> Signed-off-by: Tony Lindgren <[email protected]>
2023-10-12clk: stm32: Fix a signedness issue in clk_stm32_composite_determine_rate()Dan Carpenter1-1/+1
The divider_ro_round_rate() function could potentially return -EINVAL on error but the error handling doesn't work because "rate" is unsigned. It should be a type long. Fixes: 06ed0fc0fbac ("clk: stm32: composite: Switch to determine_rate") Signed-off-by: Dan Carpenter <[email protected]> Link: https://lore.kernel.org/r/[email protected] Acked-by: Maxime Ripard <[email protected]> Signed-off-by: Stephen Boyd <[email protected]>
2023-10-12clk: Sanitize possible_parent_show to Handle Return Value of ↵Alessandro Carminati1-9/+12
of_clk_get_parent_name In the possible_parent_show function, ensure proper handling of the return value from of_clk_get_parent_name to prevent potential issues arising from a NULL return. The current implementation invokes seq_puts directly on the result of of_clk_get_parent_name without verifying the return value, which can lead to kernel panic if the function returns NULL. This patch addresses the concern by introducing a check on the return value of of_clk_get_parent_name. If the return value is not NULL, the function proceeds to call seq_puts, providing the returned value as argument. However, if of_clk_get_parent_name returns NULL, the function provides a static string as argument, avoiding the panic. Fixes: 1ccc0ddf046a ("clk: Use seq_puts() in possible_parent_show()") Reported-by: Philip Daly <[email protected]> Signed-off-by: Alessandro Carminati (Red Hat) <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Stephen Boyd <[email protected]>
2023-10-12clk: socfpga: gate: Account for the divider in determine_rateMaxime Ripard1-4/+23
Commit 9607beb917df ("clk: socfpga: gate: Add a determine_rate hook") added a determine_rate implementation set to the clk_hw_determine_rate_no_reparent, but failed to account for the internal divider that wasn't used before anywhere but in recalc_rate. This led to inconsistencies between the clock rate stored in clk_core->rate and the one returned by clk_round_rate() that leverages determine_rate(). Since that driver seems to be widely used (and thus regression-prone) and not supporting rate changes (since it's missing a .set_rate implementation), we can just report the current divider programmed in the clock but not try to change it in any way. This should be good enough to fix the issues reported, and if someone ever wants to allow the divider to change then it should be easy enough using the clk-divider helpers. Link: https://lore.kernel.org/linux-clk/[email protected]/ Fixes: 9607beb917df ("clk: socfpga: gate: Add a determine_rate hook") Reported-by: Benedikt Spranger <[email protected]> Signed-off-by: Maxime Ripard <[email protected]> Link: https://lore.kernel.org/r/[email protected] [[email protected]: Fix hw -> hwclk] Signed-off-by: Stephen Boyd <[email protected]>
2023-10-12clk: fractional-divider: tests: Add test suite for edge casesFrank Oltmanns4-0/+156
In light of the recent discovery that the fractional divisor approximation does not utilize the full available range for clocks that are flagged CLK_FRAC_DIVIDER_ZERO_BASED [1], implement tests for the edge cases of this clock type. Signed-off-by: Frank Oltmanns <[email protected]> Link: https://lore.kernel.org/lkml/[email protected] [1] Link: https://lore.kernel.org/r/[email protected] [[email protected]: Rename suite and tests slightly, drop unused includes, store parent rate to compare instead of repeating equation] Signed-off-by: Stephen Boyd <[email protected]>
2023-10-12clk: fractional-divider: Improve approximation when zero based and exportFrank Oltmanns1-7/+20
Consider the CLK_FRAC_DIVIDER_ZERO_BASED flag when finding the best approximation for m and n. By doing so, increase the range of valid values for the numerator and denominator by 1. Furthermore, export the approximation function so that users of this function can be compiled as modules. Cc: A.s. Dong <[email protected]> Signed-off-by: Frank Oltmanns <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Stephen Boyd <[email protected]>
2023-10-12clk: renesas: r9a08g045: Add clock and reset support for SDHI1 and SDHI2Claudiu Beznea1-0/+34
Add clock and reset support for the SDHI1 and SDHI2 blocks on the RZ/G3S (R9A08G045) SoC. Signed-off-by: Claudiu Beznea <[email protected]> Reviewed-by: Geert Uytterhoeven <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Geert Uytterhoeven <[email protected]>
2023-10-12clk: renesas: rzg2l: Use %x format specifier to print CLK_ON_R()Claudiu Beznea1-1/+1
Use the %x format specifier to print CLK_ON_R(). This makes debugging easier as the value printed will be hexadecimal like in the hardware manual. Along with it add "0x" in front of the printed value. Signed-off-by: Claudiu Beznea <[email protected]> Reviewed-by: Geert Uytterhoeven <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Geert Uytterhoeven <[email protected]>
2023-10-10clk: renesas: Add minimal boot support for RZ/G3S SoCClaudiu Beznea5-1/+228
Add minimal clock and reset support for the RZ/G3S SoC to be able to boot Linux from SD Card/eMMC. This includes necessary core clocks for booting and GIC, SCIF, GPIO, and SD0 module clocks and resets. Signed-off-by: Claudiu Beznea <[email protected]> Reviewed-by: Geert Uytterhoeven <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Geert Uytterhoeven <[email protected]>
2023-10-10clk: renesas: rzg2l: Add divider clock for RZ/G3SClaudiu Beznea2-0/+197
Add a divider clock driver for RZ/G3S. This will be used on RZ/G3S for the SDHI, SPI, OCTA, I, I2, I3, P0, P1, P2, and P3 core clocks. The divider has some limitation for SDHI, OCTA and SPI clocks: - SDHI div cannot be 1 if parent rate is 800MHz, - OCTA, SPI div cannot be 1 if parent rate is 400MHz. To handle these limitations, a notifier is registered from platform specific clock driver, which makes sure proper actions are taken before the clock rate is changed, when needed. Signed-off-by: Claudiu Beznea <[email protected]> Reviewed-by: Geert Uytterhoeven <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Geert Uytterhoeven <[email protected]>
2023-10-10clk: renesas: rzg2l: Refactor SD mux driverClaudiu Beznea4-51/+139
Refactor SD MUX driver to be able to reuse the same code on RZ/G3S. RZ/G2{L,UL} has a limitation with regards to switching the clock source for SD MUX (MUX clock source has to be switched to 266MHz before switching b/w 533MHz and 400MHz). Rework the handling of this limitation to use a clock notifier that is registered according to platform based initialization data, so the SD MUX code can be reused on RZ/G3S. As RZ/G2{L,UL} and RZ/G3S use different bits in different registers to check if the clock switching has been done, this configuration (register offset, register bits and bitfield width) is now passed through struct cpg_core_clk::sconf (status configuration) from platform specific initialization code. Along with struct cpg_core_clk::sconf the mux table indices are also passed from platform specific initialization code. Also, mux flags are now passed to DEF_SD_MUX() as they will be used later by RZ/G3S. CPG_WEN_BIT macro has been introduced to select properly the WEN bit of various registers. Signed-off-by: Claudiu Beznea <[email protected]> Reviewed-by: Geert Uytterhoeven <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Geert Uytterhoeven <[email protected]>
2023-10-09clk: versaclock7: Convert to use maple tree register cacheMark Brown1-1/+1
The maple tree register cache is based on a much more modern data structure than the rbtree cache and makes optimisation choices which are probably more appropriate for modern systems than those made by the rbtree cache. Signed-off-by: Mark Brown <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Stephen Boyd <[email protected]>
2023-10-09clk: versaclock5: Convert to use maple tree register cacheMark Brown1-1/+1
The maple tree register cache is based on a much more modern data structure than the rbtree cache and makes optimisation choices which are probably more appropriate for modern systems than those made by the rbtree cache. Signed-off-by: Mark Brown <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Stephen Boyd <[email protected]>
2023-10-09clk: versaclock3: Convert to use maple tree register cacheMark Brown1-1/+1
The maple tree register cache is based on a much more modern data structure than the rbtree cache and makes optimisation choices which are probably more appropriate for modern systems than those made by the rbtree cache. Signed-off-by: Mark Brown <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Stephen Boyd <[email protected]>
2023-10-09clk: versaclock3: Remove redundant _is_writeable()Mark Brown1-6/+0
The versaclock3 driver provides an _is_writeable() function which returns true for all registers. This is the default assumption for regmaps so we can remove the function for a very minor improvement in performance and code size. Signed-off-by: Mark Brown <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Stephen Boyd <[email protected]>
2023-10-09clk: si570: Convert to use maple tree register cacheMark Brown1-1/+1
The maple tree register cache is based on a much more modern data structure than the rbtree cache and makes optimisation choices which are probably more appropriate for modern systems than those made by the rbtree cache. Signed-off-by: Mark Brown <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Stephen Boyd <[email protected]>
2023-10-09clk: si544: Convert to use maple tree register cacheMark Brown1-1/+1
The maple tree register cache is based on a much more modern data structure than the rbtree cache and makes optimisation choices which are probably more appropriate for modern systems than those made by the rbtree cache. Signed-off-by: Mark Brown <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Stephen Boyd <[email protected]>
2023-10-09clk: si5351: Convert to use maple tree register cacheMark Brown1-1/+1
The maple tree register cache is based on a much more modern data structure than the rbtree cache and makes optimisation choices which are probably more appropriate for modern systems than those made by the rbtree cache. Signed-off-by: Mark Brown <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Stephen Boyd <[email protected]>
2023-10-09clk: si5341: Convert to use maple tree register cacheMark Brown1-1/+1
The maple tree register cache is based on a much more modern data structure than the rbtree cache and makes optimisation choices which are probably more appropriate for modern systems than those made by the rbtree cache. Signed-off-by: Mark Brown <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Stephen Boyd <[email protected]>
2023-10-09clk: si514: Convert to use maple tree register cacheMark Brown1-1/+1
The maple tree register cache is based on a much more modern data structure than the rbtree cache and makes optimisation choices which are probably more appropriate for modern systems than those made by the rbtree cache. Signed-off-by: Mark Brown <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Stephen Boyd <[email protected]>
2023-10-09clk: cdce925: Convert to use maple tree register cacheMark Brown1-1/+1
The maple tree register cache is based on a much more modern data structure than the rbtree cache and makes optimisation choices which are probably more appropriate for modern systems than those made by the rbtree cache. Signed-off-by: Mark Brown <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Stephen Boyd <[email protected]>
2023-10-09clk: Parameterize clk_leaf_mux_set_rate_parentStephen Boyd1-8/+73
Transform the existing clk_leaf_mux_set_rate_parent test into a parameterized test that calls the various determine rate APIs that exist for clk providers. This ensures that whatever determine rate API is used by a clk provider will return the correct parent in the best_parent_hw pointer of the clk_rate_request because clk_rate_requests are forwarded properly. Cc: Guenter Roeck <[email protected]> Cc: Maxime Ripard <[email protected]> Link: https://lore.kernel.org/r/[email protected] Acked-by: Maxime Ripard <[email protected]> Signed-off-by: Stephen Boyd <[email protected]>
2023-10-09clk: Drive clk_leaf_mux_set_rate_parent test from clk_opsStephen Boyd1-17/+48
Running this kunit test with lockdep enabled leads to warning splats about calling clk provider APIs without the clk_prepare lock held. I proposed adding a wrapper around these APIs to grab the prepare lock so we can call them from anywhere, and Maxime implemented that approach[1], but it didn't look great. That's because we had to make more kunit testing APIs just to call code from a place that isn't a clk provider when the prepare lock isn't held. Instead of doing that, let's implement a determine_rate clk_op for a new leaf clk that is the child of the existing leaf clk. We can call __clk_determine_rate() on the existing leaf clk from there, and stash away the clk_rate_request struct to check once the clk_op returns. Drive that clk_op by calling clk_round_rate() to keep things similar to how it was before (i.e. nothing actually changes rate, just the new rate is determined). This silences the warning by driving the test from a clk_op where we know the prepare lock is held. While looking at this in more detail, it was determined that the code we intended to test in commit 262ca38f4b6e ("clk: Stop forwarding clk_rate_requests to the parent") wasn't actually tested. The call to __clk_determine_rate() wasn't actually getting to the newly introduced code under the CLK_SET_RATE_PARENT if condition in clk_core_round_rate_nolock() because the parent clk (the mux) could round rates. We introduce a new leaf and make sure the parent of that clk has no clk_ops so that we can be certain that the CLK_SET_RATE_PARENT condition in clk_core_round_rate_nolock() is evaluated. Reported-by: Guenter Roeck <[email protected]> Closes: https://lore.kernel.org/linux-clk/[email protected]/ Reported-by: kernel test robot <[email protected]> Closes: https://lore.kernel.org/oe-lkp/[email protected] Cc: Maxime Ripard <[email protected]> Link: https://lore.kernel.org/r/[email protected] [1] Fixes: 262ca38f4b6e ("clk: Stop forwarding clk_rate_requests to the parent") Link: https://lore.kernel.org/r/[email protected] Acked-by: Maxime Ripard <[email protected]> Signed-off-by: Stephen Boyd <[email protected]>
2023-10-08clk: scmi: Add support for clock {set,get}_parentPeng Fan1-1/+60
SCMI v3.2 adds set/get parent clock commands, so update the SCMI clock driver to support them. Signed-off-by: Peng Fan <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Sudeep Holla <[email protected]>
2023-10-08clk: scmi: Free scmi_clk allocated when the clocks with invalid info are skippedSudeep Holla1-0/+1
Add the missing devm_kfree() when we skip the clocks with invalid or missing information from the firmware. Cc: Cristian Marussi <[email protected]> Cc: Michael Turquette <[email protected]> Cc: Stephen Boyd <[email protected]> Cc: [email protected] Fixes: 6d6a1d82eaef ("clk: add support for clocks provided by SCMI") Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Sudeep Holla <[email protected]>
2023-10-05clk: renesas: rzg2l: Remove CPG_SDHI_DSEL from generic headerClaudiu Beznea3-4/+14
Remove CPG_SDHI_DSEL and its bits from the generic header as RZ/G3S has different offset registers and bits for this, thus avoid mixing them. Signed-off-by: Claudiu Beznea <[email protected]> Reviewed-by: Geert Uytterhoeven <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Geert Uytterhoeven <[email protected]>
2023-10-05clk: renesas: rzg2l: Add struct clk_hw_dataClaudiu Beznea1-18/+34
Add clk_hw_data struct that keeps the core part of the clock data. sd_hw_data embeds a member of type struct clk_hw_data along with other members (in the next commits). This commit prepares the field for refactoring the SD MUX clock driver. Signed-off-by: Claudiu Beznea <[email protected]> Reviewed-by: Geert Uytterhoeven <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Geert Uytterhoeven <[email protected]>
2023-10-05clk: renesas: rzg2l: Add support for RZ/G3S PLLClaudiu Beznea2-4/+48
Add support for reading the frequency of PLL1/4/6 as available on RZ/G3S. The computation formula for the PLL frequency is as follows: Fout = (nir + nfr / 4096) * Fin / (mr * pr) Signed-off-by: Claudiu Beznea <[email protected]> Reviewed-by: Geert Uytterhoeven <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Geert Uytterhoeven <[email protected]>
2023-10-05clk: renesas: rzg2l: Remove critical areaClaudiu Beznea1-4/+1
The spinlock in rzg2l_mod_clock_endisable() is intended to protect RMW-accesses to the hardware register. There is no need to protect instructions that set temporary variables which will be written afterwards to a hardware register. With this only one write to one clock register is executed thus locking/unlocking rmw_lock is removed. Signed-off-by: Claudiu Beznea <[email protected]> Reviewed-by: Geert Uytterhoeven <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Geert Uytterhoeven <[email protected]>
2023-10-05clk: renesas: rzg2l: Fix computation formulaClaudiu Beznea1-6/+6
According to the hardware manual for RZ/G2L (r01uh0914ej0130-rzg2l-rzg2lc.pdf), the computation formula for PLL rate is as follows: Fout = ((m + k/65536) * Fin) / (p * 2^s) and k has values in the range [-32768, 32767]. Dividing k by 65536 with integer arithmetic gives zero all the time, causing slight differences b/w what has been set vs. what is displayed. Thus, get rid of this and decompose the formula before dividing k by 65536. Fixes: ef3c613ccd68a ("clk: renesas: Add CPG core wrapper for RZ/G2L SoC") Signed-off-by: Claudiu Beznea <[email protected]> Reviewed-by: Geert Uytterhoeven <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Geert Uytterhoeven <[email protected]>
2023-10-05clk: renesas: rzg2l: Trust value returned by hardwareClaudiu Beznea1-7/+1
The onitial value of the CPG_PL2SDHI_DSEL bits 0..1 or 4..6 is 01b. The hardware user's manual (r01uh0914ej0130-rzg2l-rzg2lc.pdf) specifies that setting 0 is prohibited. Hence rzg2l_cpg_sd_clk_mux_get_parent() should just read CPG_PL2SDHI_DSEL, trust the value, and return the proper clock parent index based on the value read. Fixes: eaff33646f4cb ("clk: renesas: rzg2l: Add SDHI clk mux support") Signed-off-by: Claudiu Beznea <[email protected]> Reviewed-by: Geert Uytterhoeven <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Geert Uytterhoeven <[email protected]>
2023-10-05clk: renesas: rzg2l: Lock around writes to mux registerClaudiu Beznea2-11/+14
The SD MUX output (SD0) is further divided by 4 in G2{L,UL}. The divided clock is SD0_DIV4. SD0_DIV4 is registered with CLK_SET_RATE_PARENT which means a rate request for it is propagated to the MUX and could reach rzg2l_cpg_sd_clk_mux_set_parent() concurrently with the users of SD0. Add proper locking to avoid concurrent accesses on SD MUX set rate registers. Fixes: eaff33646f4cb ("clk: renesas: rzg2l: Add SDHI clk mux support") Signed-off-by: Claudiu Beznea <[email protected]> Reviewed-by: Geert Uytterhoeven <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Geert Uytterhoeven <[email protected]>
2023-10-05clk: renesas: rzg2l: Wait for status bit of SD mux before continuingClaudiu Beznea1-7/+10
The hardware user manual for RZ/G2L (r01uh0914ej0130-rzg2l-rzg2lc.pdf, chapter 7.4.7 Procedure for Switching Clocks by the Dynamic Switching Frequency Selectors) specifies that we need to check CPG_PL2SDHI_DSEL for SD clock switching status. Fixes: eaff33646f4cb ("clk: renesas: rzg2l: Add SDHI clk mux support") Signed-off-by: Claudiu Beznea <[email protected]> Reviewed-by: Geert Uytterhoeven <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Geert Uytterhoeven <[email protected]>
2023-10-05clk: renesas: rcar-gen3: Extend SDnH divider tableDirk Behme1-1/+14
The clock dividers might be used with clock stop bit enabled or not. Current tables only support recommended values from the datasheet. This might result in warnings like below because no valid clock divider is found. Resulting in a 0 divider. There are Renesas ARM Trusted Firmware version out there which e.g. configure 0x201 (shifted logical right by 2: 0x80) and with this match the added { STPnHCK | 0, 1 }: https://github.com/renesas-rcar/arm-trusted-firmware/blob/rcar_gen3_v2.3/drivers/renesas/rcar/emmc/emmc_init.c#L108 ------------[ cut here ]------------ sd1h: Zero divisor and CLK_DIVIDER_ALLOW_ZERO not set WARNING: CPU: 1 PID: 1 at drivers/clk/clk-divider.c:141 divider_recalc_rate+0x48/0x70 Modules linked in: CPU: 1 PID: 1 Comm: swapper/0 Not tainted 6.1.52 #1 Hardware name: Custom board based on r8a7796 (DT) pstate: 40000005 (nZcv daif -PAN -UAO -TCO -DIT -SSBS BTYPE=--) pc : divider_recalc_rate+0x48/0x70 ... ------------[ cut here ]------------ Fixes: bb6d3fa98a41 ("clk: renesas: rcar-gen3: Switch to new SD clock handling") Signed-off-by: Dirk Behme <[email protected]> [wsa: extended the table to 5 entries, added comments, reword commit message a little] Signed-off-by: Wolfram Sang <[email protected]> Tested-by: Dirk Behme <[email protected]> Reviewed-by: Geert Uytterhoeven <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Geert Uytterhoeven <[email protected]>
2023-10-04clk: imx: imx8qm/qxp: add more resources to whitelistPeng Fan2-0/+5
Add CAN_1/2 support for i.MX8QM Add M4_0, PI_0_PWM_0 and PI_0_I2C_0 for i.MX8QXP Signed-off-by: Peng Fan <[email protected]> Reviewed-by: Abel Vesa <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Abel Vesa <[email protected]>
2023-10-04clk: imx: scu: ignore clks not owned by Cortex-A partitionPeng Fan1-0/+20
Not register clks that not owned to current partition. CPU resources are specical resources, it is assigned in ATF, not non-secure OS, but we still need to allow cpu freq, so return true for non-secure OS for cpu resources. Otherwise there will be error log if the resources are owned by current partition: [ 19.387291] cm40_i2c_div: failed to attached the power domain -2 [ 19.389305] cm40_lpuart_div: failed to attached the power domain -2 Signed-off-by: Peng Fan <[email protected]> Reviewed-by: Abel Vesa <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Abel Vesa <[email protected]>
2023-10-04clk: imx8: remove MLB supportPeng Fan5-7/+3
MLB was de-featured, so drop MLB clk for i.MX8QM/QXP/DXL Signed-off-by: Peng Fan <[email protected]> Reviewed-by: Abel Vesa <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Abel Vesa <[email protected]>
2023-10-04clk: imx: imx8qm-rsrc: drop VPU_UART/VPUCOREPeng Fan1-2/+0
IMX_SC_R_VPU_UART and IMX_SC_R_VPUCORE was used in i.MX8QM A0 which not for mass production. i.MX8QM B0 not have the two resources, so drop it. Signed-off-by: Peng Fan <[email protected]> Reviewed-by: Abel Vesa <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Abel Vesa <[email protected]>
2023-10-04clk: imx: imx8qxp: correct the enet clocks for i.MX8DXLShenwei Wang1-2/+9
The SC_PM_CLK_MISC0 clock is not available for the resources of ENET0/1 on i.MX8DXL. Using the clock device compatible string to identify the platform and only initialize the enetX_rgmii_rx_clk clock for non i.MX8DXL platform. Signed-off-by: Shenwei Wang <[email protected]> Reviewed-by: Ranjani Vaidyanathan <[email protected]> Reviewed-by: Jacky Bai <[email protected]> Acked-by: Jason Liu <[email protected]> Signed-off-by: Peng Fan <[email protected]> Reviewed-by: Abel Vesa <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Abel Vesa <[email protected]>
2023-10-04clk: imx: imx8qxp: Fix elcdif_pll clockRobert Chiras1-1/+1
Move the elcdif_pll clock initialization before the lcd_clk, since the elcdif_clk needs to be initialized ahead of lcd_clk, being its parent. This change fixes issues with the LCD clocks during suspend/resume. Fixes: babfaa9556d7 ("clk: imx: scu: add more scu clocks") Suggested-by: Ranjani Vaidyanathan <[email protected]> Acked-by: Laurentiu Palcu <[email protected]> Signed-off-by: Robert Chiras <[email protected]> Signed-off-by: Peng Fan <[email protected]> Reviewed-by: Abel Vesa <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Abel Vesa <[email protected]>
2023-10-04clk: imx: imx8dxl-rsrc: keep sorted in the ascending orderViorel Suman1-1/+1
Entries in imx8dxl_clk_scu_rsrc_table must be kept in the ascending order, and IMX_SC_R_M4_0_UART < IMX_SC_R_M4_0_I2C. Fixes: 036a4b4b4dfa ("clk: imx: Add imx8dxl clk driver") Signed-off-by: Viorel Suman <[email protected]> Signed-off-by: Peng Fan <[email protected]> Reviewed-by: Abel Vesa <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Abel Vesa <[email protected]>
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