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2023-08-04clk: tegra: Replace kstrdup() + strreplace() with kstrdup_and_replace()Andy Shevchenko1-4/+2
Replace open coded functionality of kstrdup_and_replace() with a call. Signed-off-by: Andy Shevchenko <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Stephen Boyd <[email protected]>
2023-08-04clk: keystone: syscon-clk: Fix audio refclkFrancesco Dolcini1-2/+4
Audio REFCLK's are not working correctly, trying to use them lead to the following errors: [ 6.575277] of_clk_hw_onecell_get: invalid index 4294934528 [ 6.581515] wm8904 1-001a: Failed to get MCLK [ 6.586290] wm8904: probe of 1-001a failed with error -2 The issue is that Audio REFCLK has #clock-cells = 0 [1], while the driver is registering those clocks assuming they have one cells. Fix this by registering the clock with of_clk_hw_simple_get() when there is only one instance, e.g. "audio_refclk". [1] Documentation/devicetree/bindings/clock/ti,am62-audio-refclk.yaml Fixes: 6acab96ee337 ("clk: keystone: syscon-clk: Add support for audio refclk") Signed-off-by: Francesco Dolcini <[email protected]> Link: https://lore.kernel.org/r/[email protected] [[email protected]: Simplify if-return-else logic] Signed-off-by: Stephen Boyd <[email protected]>
2023-08-04clk: qcom: gcc-sm6350: Fix gcc_sdcc2_apps_clk_srcLuca Weiss1-0/+1
GPLL7 is not on by default, which causes a "gcc_sdcc2_apps_clk_src: rcg didn't update its configuration" error when booting. Set .flags = CLK_OPS_PARENT_ENABLE to fix the error. Fixes: 131abae905df ("clk: qcom: Add SM6350 GCC driver") Signed-off-by: Luca Weiss <[email protected]> Reviewed-by: Konrad Dybcio <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Bjorn Andersson <[email protected]>
2023-08-03clk: qcom: reset: Use the correct type of sleep/delay based on lengthKonrad Dybcio1-1/+2
Use the fsleep() helper that (based on the length of the delay, see: [1]) chooses the correct sleep/delay functions. [1] https://www.kernel.org/doc/Documentation/timers/timers-howto.txt Fixes: 2cb8a39b6781 ("clk: qcom: reset: Allow specifying custom reset delay") Signed-off-by: Konrad Dybcio <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Bjorn Andersson <[email protected]>
2023-08-03clk: qcom: fix some Kconfig corner casesArnd Bergmann1-0/+4
The SM_GCC_8550 symbol and others can only be built for ARM64 or when compile testing, but it gets selected by other drivers that can also be built for 32-bit ARCH_QCOM when not compile testing, which results in a Kconfig warning: WARNING: unmet direct dependencies detected for SM_GCC_8550 Depends on [n]: COMMON_CLK [=y] && COMMON_CLK_QCOM [=m] && (ARM64 || COMPILE_TEST [=n]) Selected by [m]: - SM_GPUCC_8550 [=m] && COMMON_CLK [=y] && COMMON_CLK_QCOM [=m] - SM_VIDEOCC_8550 [=m] && COMMON_CLK [=y] && COMMON_CLK_QCOM [=m] Add further 'depends on' statements to tighten this in a way that avoids the missing dependencies. Fixes: fd0b5b106fcab ("clk: qcom: Introduce SM8350 VIDEOCC") Fixes: 441fe711be384 ("clk: qcom: videocc-sm8450: Add video clock controller driver for SM8450") Fixes: f53153a37969c ("clk: qcom: videocc-sm8550: Add video clock controller driver for SM8550") Signed-off-by: Arnd Bergmann <[email protected]> Reviewed-by: Konrad Dybcio <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Bjorn Andersson <[email protected]>
2023-08-03clk: qcom: gcc-sm8250: Fix gcc_sdcc2_apps_clk_srcPatrick Whewell1-0/+1
GPLL9 is not on by default, which causes a "gcc_sdcc2_apps_clk_src: rcg didn't update its configuration" error when booting. Set .flags = CLK_OPS_PARENT_ENABLE to fix the error. Fixes: 3e5770921a88 ("clk: qcom: gcc: Add global clock controller driver for SM8250") Reviewed-by: Konrad Dybcio <[email protected]> Reviewed-by: Bryan O'Donoghue <[email protected]> Signed-off-by: Patrick Whewell <[email protected]> Reviewed-by: Vinod Koul <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Bjorn Andersson <[email protected]>
2023-08-03clk: qcom: lcc-msm8960: change pxo_parent_data to staticYang Yingliang1-1/+1
The pxo_parent_data inroduced in commit bac4675a4d1b ("clk: qcom: drop lcc-mdm9615 in favour of lcc-msm8960") is only used in lcc-msm8960.c now, change it to static. Signed-off-by: Yang Yingliang <[email protected]> Reviewed-by: Konrad Dybcio <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Bjorn Andersson <[email protected]>
2023-08-01clk: versaclock3: Switch to use i2c_driver's probe callbackUwe Kleine-König1-1/+1
The previous mass switch of clk drivers done in commit 62279db5a323 ("clk: Switch i2c drivers back to use .probe()") was based on v6.4-rc1 Since then this driver was added which needs to be converted back in the same way before eventually .probe_new() can be dropped from struct i2c_driver. Signed-off-by: Uwe Kleine-König <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Stephen Boyd <[email protected]>
2023-07-31clk: qcom: gcc-sc7180: Fix up gcc_sdcc2_apps_clk_srcDavid Wronek1-0/+1
Set .flags = CLK_OPS_PARENT_ENABLE to fix "gcc_sdcc2_apps_clk_src: rcg didn't update its configuration" error. Fixes: 17269568f726 ("clk: qcom: Add Global Clock controller (GCC) driver for SC7180") Signed-off-by: David Wronek <[email protected]> Reviewed-by: Konrad Dybcio <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Bjorn Andersson <[email protected]>
2023-07-31clk: qcom: cbf-msm8996: Add support for MSM8996 ProYassine Oudjana1-2/+8
The CBF PLL on MSM8996 Pro has a /4 post divisor instead of /2. Handle the difference accordingly. Signed-off-by: Yassine Oudjana <[email protected]> Reviewed-by: Konrad Dybcio <[email protected]> Reviewed-by: Dmitry Baryshkov <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Bjorn Andersson <[email protected]>
2023-07-31clk: qcom: gcc-mdm9615: drop the cxo clockDmitry Baryshkov1-17/+0
The gcc and lcc devices have been switched to the DT-defined cxo_board clock. Now we can drop the manually defined cxo clock. Reviewed-by: Neil Armstrong <[email protected]> Signed-off-by: Dmitry Baryshkov <[email protected]> Reviewed-by: Konrad Dybcio <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Bjorn Andersson <[email protected]>
2023-07-31clk: qcom: gcc-mdm9615: use parent_hws/_data instead of parent_namesDmitry Baryshkov1-82/+124
Convert the clock driver to specify parent data rather than parent names, to actually bind using 'clock-names' specified in the DTS rather than global clock names. Use parent_hws where possible to refer parent clocks directly, skipping the lookup. Note, the system names for xo clocks were changed from "cxo" to "cxo_board" to follow the example of other platforms. This switches the clocks to use DT-provided "cxo_board" clock instead of manually registered "cxo" clock and allows us to drop the cxo clock. Reviewed-by: Neil Armstrong <[email protected]> Signed-off-by: Dmitry Baryshkov <[email protected]> Reviewed-by: Konrad Dybcio <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Bjorn Andersson <[email protected]>
2023-07-31clk: qcom: gcc-mdm9615: use proper parent for pll0_vote clockDmitry Baryshkov1-1/+1
The pll0_vote clock definitely should have pll0 as a parent (instead of pll8). Fixes: 7792a8d6713c ("clk: mdm9615: Add support for MDM9615 Clock Controllers") Cc: [email protected] Reviewed-by: Neil Armstrong <[email protected]> Signed-off-by: Dmitry Baryshkov <[email protected]> Reviewed-by: Konrad Dybcio <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Bjorn Andersson <[email protected]>
2023-07-31clk: qcom: drop lcc-mdm9615 in favour of lcc-msm8960Dmitry Baryshkov4-589/+18
The two LCC drivers, msm8960 and mdm9615 are almost the same. The only difference is the platform clock: msm8960/apq8064 use pxo, while mdm9615 uses cxo. Drop the lcc-mdm9615 in favour of using lcc-msm8960 instead. Reviewed-by: Neil Armstrong <[email protected]> Signed-off-by: Dmitry Baryshkov <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Bjorn Andersson <[email protected]>
2023-07-31clk: qcom: gcc-mdm9615: use ARRAY_SIZE instead of specifying num_parentsDmitry Baryshkov1-21/+21
Use ARRAY_SIZE() instead of manually specifying num_parents. This makes adding/removing entries to/from parent_data easy and errorproof. Reviewed-by: Neil Armstrong <[email protected]> Signed-off-by: Dmitry Baryshkov <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Bjorn Andersson <[email protected]>
2023-07-31dt-bindings: clock: drop qcom,lcc-mdm9615 header fileDmitry Baryshkov1-1/+1
The header file for qcom,lcc-mdm9615 and qcom,lcc-msm8960 is the same (as well as the drivers). Drop the qcom,lcc-mdm9615.h in favour of qcom,lcc-msm8960.h Reviewed-by: Krzysztof Kozlowski <[email protected]> Signed-off-by: Dmitry Baryshkov <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Bjorn Andersson <[email protected]>
2023-07-31clk: qcom: videocc-sm8350: Add SC8280XP supportKonrad Dybcio1-1/+41
SC8280XP, being a partial derivative of SM8350, shares almost the exact same videocc block. Extend the 8350 driver to support the bigger brother. The only notable changes are higher possible frequencies on some clocks and some switcheroo within the XO/sleep registers (probably due to some different board crystal configuration). Reviewed-by: Dmitry Baryshkov <[email protected]> Signed-off-by: Konrad Dybcio <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Bjorn Andersson <[email protected]>
2023-07-31clk: sunxi-ng: Modify mismatched function nameZhang Jianhua1-1/+1
No functional modification involved. drivers/clk/sunxi-ng/ccu_mmc_timing.c:54: warning: expecting prototype for sunxi_ccu_set_mmc_timing_mode(). Prototype was for sunxi_ccu_get_mmc_timing_mode() instead Fixes: f6f64ed868d3 ("clk: sunxi-ng: Add interface to query or configure MMC timing modes.") Signed-off-by: Zhang Jianhua <[email protected]> Reviewed-by: Randy Dunlap <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Jernej Skrabec <[email protected]>
2023-07-31clk: sunxi: sun9i-mmc: Use devm_platform_get_and_ioremap_resource()Yangtao Li1-6/+4
Convert platform_get_resource(), devm_ioremap_resource() to a single call to devm_platform_get_and_ioremap_resource(), as this is exactly what this function does. Signed-off-by: Yangtao Li <[email protected]> Acked-by: Jernej Skrabec <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Jernej Skrabec <[email protected]>
2023-07-27clk: qcom: dispcc-sc8280xp: Use ret registers on GDSCsKonrad Dybcio1-4/+4
The DISP_CC GDSCs have not been instructed to use the ret registers. Fix that. Fixes: 4a66e76fdb6d ("clk: qcom: Add SC8280XP display clock controller") Signed-off-by: Konrad Dybcio <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Bjorn Andersson <[email protected]>
2023-07-27clk: renesas: r8a77965: Add 3DGE and ZG supportGeert Uytterhoeven1-0/+2
The 3DGE and ZG clocks are necessary to support the 3D graphics. Signed-off-by: Geert Uytterhoeven <[email protected]> Link: https://lore.kernel.org/r/1767d01cfffd7490861f2cf6ad6c0df100916907.1689599217.git.geert+renesas@glider.be
2023-07-27clk: renesas: r8a7796: Add 3DGE and ZG supportGeert Uytterhoeven1-0/+2
The 3DGE and ZG clocks are necessary to support the 3D graphics. Signed-off-by: Geert Uytterhoeven <[email protected]> Link: https://lore.kernel.org/r/291462bea7ffc13f8218c1901dc384b576bfc2d6.1689599217.git.geert+renesas@glider.be
2023-07-27clk: renesas: r8a7795: Add 3DGE and ZG supportGeert Uytterhoeven1-0/+2
The 3DGE and ZG clocks are necessary to support the 3D graphics. Signed-off-by: Geert Uytterhoeven <[email protected]> Link: https://lore.kernel.org/r/36096e2df2a54516fadd1978c47fc7de354abc26.1689599217.git.geert+renesas@glider.be
2023-07-27clk: renesas: emev2: Remove obsolete clkdev registrationGeert Uytterhoeven1-3/+0
EMMA Mobile EV2 is a multi-platform/CCF-only platform, registering all devices from DT, so we can remove the registration of clkdevs. Signed-off-by: Geert Uytterhoeven <[email protected]> Acked-by: Niklas Söderlund <[email protected]> Link: https://lore.kernel.org/r/f54a30d7a9e2aa075d462db701a60b0b59c6ad0b.1686325857.git.geert+renesas@glider.be
2023-07-26Merge tag 'clk-meson-fixes-v6.5-1' of https://github.com/BayLibre/clk-meson ↵Stephen Boyd1-2/+2
into clk-fixes Pull an Amlogic clk driver fix from Jerome Brunet: - Fix PLL scheduling while atomic following a1 locking sequence update * tag 'clk-meson-fixes-v6.5-1' of https://github.com/BayLibre/clk-meson: clk: meson: change usleep_range() to udelay() for atomic context
2023-07-25clk: renesas: r9a07g043: Add MTU3a clock and reset entryBiju Das1-0/+3
Add MTU3a clock and reset entry to CPG driver. Signed-off-by: Biju Das <[email protected]> Reviewed-by: Geert Uytterhoeven <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Geert Uytterhoeven <[email protected]>
2023-07-25clk: imx: clk-gpr-mux: Simplify .determine_rate()Christophe JAILLET1-7/+1
imx_clk_gpr_mux_determine_rate() is the same as __clk_mux_determine_rate(), so use the latter to save some LoC. Signed-off-by: Christophe JAILLET <[email protected]> Reviewed-by: Peng Fan <[email protected]> Link: https://lore.kernel.org/r/ac8bd50c41b84f244bb0ec94e8aed25c513c9037.1688760152.git.christophe.jaillet@wanadoo.fr Signed-off-by: Abel Vesa <[email protected]>
2023-07-25clk: imx: Add 519.75MHz frequency support for imx9 pllJacky Bai1-0/+1
For video pll, it may need 519.75MHz clock frequency for the LVDS display usage. So add 519.75MHz frequency config support for video pll. Signed-off-by: Jacky Bai <[email protected]> Reviewed-by: Peng Fan <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Abel Vesa <[email protected]>
2023-07-25clk: imx93: Add PDM IPG clkChancel Liu1-1/+3
The IPG clk and MCLK of PDM share the same control gate. Reviewed-by: Shengjiu Wang <[email protected]> Signed-off-by: Chancel Liu <[email protected]> Signed-off-by: Jacky Bai <[email protected]> Reviewed-by: Peng Fan <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Abel Vesa <[email protected]>
2023-07-19clk: Add support for versa3 clock driverBiju Das3-0/+1153
Add support for Renesas versa3 clock driver(5p35023). The clock generator provides 6 output clocks. Signed-off-by: Biju Das <[email protected]> Link: https://lore.kernel.org/r/[email protected] [[email protected]: Add newline to printk] Signed-off-by: Stephen Boyd <[email protected]>
2023-07-19clk: oxnas: remove obsolete clock driverNeil Armstrong3-259/+0
Due to lack of maintenance and stall of development for a few years now, and since no new features will ever be added upstream, remove support for OX810 and OX820 clock driver. Acked-by: Linus Walleij <[email protected]> Acked-by: Arnd Bergmann <[email protected]> Acked-by: Daniel Golle <[email protected]> Signed-off-by: Neil Armstrong <[email protected]> Link: https://lore.kernel.org/r/20230630-topic-oxnas-upstream-remove-v2-1-fb6ab3dea87c@linaro.org Signed-off-by: Stephen Boyd <[email protected]>
2023-07-19clk: fixed-mmio: make COMMON_CLK_FIXED_MMIO depend on HAS_IOMEMBaoquan He1-0/+1
On s390 systems (aka mainframes), it has classic channel devices for networking and permanent storage that are currently even more common than PCI devices. Hence it could have a fully functional s390 kernel with CONFIG_PCI=n, then the relevant iomem mapping functions [including ioremap(), devm_ioremap(), etc.] are not available. Here let COMMON_CLK_FIXED_MMIO depend on HAS_IOMEM so that it won't be built to cause below compiling error if PCI is unset: ------ ld: drivers/clk/clk-fixed-mmio.o: in function `fixed_mmio_clk_setup': clk-fixed-mmio.c:(.text+0x5e): undefined reference to `of_iomap' ld: clk-fixed-mmio.c:(.text+0xba): undefined reference to `iounmap' ------ Reported-by: kernel test robot <[email protected]> Closes: https://lore.kernel.org/oe-kbuild-all/[email protected]/ Signed-off-by: Baoquan He <[email protected]> Cc: Michael Turquette <[email protected]> Cc: Stephen Boyd <[email protected]> Cc: [email protected] Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Stephen Boyd <[email protected]>
2023-07-19drivers: clk: keystone: Fix parameter judgment in _of_pll_clk_init()Minjie Du1-1/+1
The function clk_register_pll() may return NULL or an ERR_PTR. Don't treat an ERR_PTR as valid. Signed-off-by: Minjie Du <[email protected]> Link: https://lore.kernel.org/r/[email protected] Fixes: b9e0d40c0d83 ("clk: keystone: add Keystone PLL clock driver") [[email protected]: Reword commit text] Signed-off-by: Stephen Boyd <[email protected]>
2023-07-19clk: imx93: Propagate correct error in imx93_clocks_probe()Geert Uytterhoeven1-1/+1
smatch reports: drivers/clk/imx/clk-imx93.c:294 imx93_clocks_probe() error: uninitialized symbol 'base'. Indeed, in case of an error, the wrong (yet uninitialized) variable is converted to an error code and returned. Fix this by propagating the error code in the correct variable. Fixes: e02ba11b45764705 ("clk: imx93: fix memory leak and missing unwind goto in imx93_clocks_probe") Reported-by: Dan Carpenter <[email protected]> Closes: https://lore.kernel.org/all/[email protected] Reported-by: kernel test robot <[email protected]> Closes: https://lore.kernel.org/all/[email protected]/ Signed-off-by: Geert Uytterhoeven <[email protected]> Link: https://lore.kernel.org/r/[email protected] Reviewed-by: Peng Fan <[email protected]> Signed-off-by: Stephen Boyd <[email protected]>
2023-07-19clk: Explicitly include correct DT includesRob Herring205-277/+162
The DT of_device.h and of_platform.h date back to the separate of_platform_bus_type before it as merged into the regular platform bus. As part of that merge prepping Arm DT support 13 years ago, they "temporarily" include each other. They also include platform_device.h and of.h. As a result, there's a pretty much random mix of those include files used throughout the tree. In order to detangle these headers and replace the implicit includes with struct declarations, users need to explicitly include the correct includes. Acked-by: Dinh Nguyen <[email protected]> Acked-by: Krzysztof Kozlowski <[email protected]> # samsung Acked-by: Heiko Stuebner <[email protected]> #rockchip Acked-by: Chanwoo Choi <[email protected]> Acked-by: Geert Uytterhoeven <[email protected]> Reviewed-by: AngeloGioacchino Del Regno <[email protected]> Reviewed-by: Luca Ceresoli <[email protected]> # versaclock5 Signed-off-by: Rob Herring <[email protected]> Link: https://lore.kernel.org/r/[email protected] Acked-by: Abel Vesa <[email protected]> #imx Signed-off-by: Stephen Boyd <[email protected]>
2023-07-19clk: starfive: Simplify .determine_rate()Christophe JAILLET1-8/+2
jh71x0_clk_mux_determine_rate() is the same as __clk_mux_determine_rate(), so use the latter to save some LoC. Signed-off-by: Christophe JAILLET <[email protected]> Link: https://lore.kernel.org/r/085541814ebe2543cb7e8a31004c0da3e7d5b6eb.1688760111.git.christophe.jaillet@wanadoo.fr Reviewed-by: Emil Renner Berthing <[email protected]> Signed-off-by: Stephen Boyd <[email protected]>
2023-07-19clk: mediatek: mt8183: Add back SSPM related clocksChen-Yu Tsai1-0/+27
This reverts commit 860690a93ef23b567f781c1b631623e27190f101. On the MT8183, the SSPM related clocks were removed claiming a lack of usage. This however causes some issues when the driver was converted to the new simple-probe mechanism. This mechanism allocates enough space for all the clocks defined in the clock driver, not the highest index in the DT binding. This leads to out-of-bound writes if their are holes in the DT binding or the driver (due to deprecated or unimplemented clocks). These errors can go unnoticed and cause memory corruption, leading to crashes in unrelated areas, or nothing at all. KASAN will detect them. Add the SSPM related clocks back to the MT8183 clock driver to fully implement the DT binding. The SSPM clocks are for the power management co-processor, and should never be turned off. They are marked as such. Fixes: 3f37ba7cc385 ("clk: mediatek: mt8183: Convert all remaining clocks to common probe") Signed-off-by: Chen-Yu Tsai <[email protected]> Link: https://lore.kernel.org/r/[email protected] Reviewed-by: AngeloGioacchino Del Regno <[email protected]> Signed-off-by: Stephen Boyd <[email protected]>
2023-07-19clk: starfive: Add StarFive JH7110 Video-Output clock driverXingyu Wu3-0/+248
Add driver for the StarFive JH7110 Video-Output clock controller. And these clock controllers should power on and enable the clocks from SYSCRG first before registering. Acked-by: Palmer Dabbelt <[email protected]> Reviewed-by: Emil Renner Berthing <[email protected]> Reviewed-by: Hal Feng <[email protected]> Signed-off-by: Xingyu Wu <[email protected]> Signed-off-by: Conor Dooley <[email protected]>
2023-07-19clk: starfive: Add StarFive JH7110 Image-Signal-Process clock driverXingyu Wu4-0/+247
Add driver for the StarFive JH7110 Image-Signal-Process clock controller. And these clock controllers should power on and enable the clocks from SYSCRG before registering. Acked-by: Palmer Dabbelt <[email protected]> Reviewed-by: Emil Renner Berthing <[email protected]> Reviewed-by: Hal Feng <[email protected]> Signed-off-by: Xingyu Wu <[email protected]> Signed-off-by: Conor Dooley <[email protected]>
2023-07-19clk: starfive: Add StarFive JH7110 System-Top-Group clock driverEmil Renner Berthing3-0/+182
Add driver for the StarFive JH7110 System-Top-Group clock controller. Acked-by: Palmer Dabbelt <[email protected]> Reviewed-by: Hal Feng <[email protected]> Co-developed-by: Xingyu Wu <[email protected]> Signed-off-by: Xingyu Wu <[email protected]> Signed-off-by: Emil Renner Berthing <[email protected]> Signed-off-by: Conor Dooley <[email protected]>
2023-07-19clk: starfive: jh7110-sys: Add PLL clocks source from DTSXingyu Wu2-22/+45
Modify PLL clocks source to be got from DTS or the fixed factor clocks. Signed-off-by: Xingyu Wu <[email protected]> Reviewed-by: Emil Renner Berthing <[email protected]> Signed-off-by: Conor Dooley <[email protected]>
2023-07-19clk: starfive: Add StarFive JH7110 PLL clock driverXingyu Wu3-0/+516
Add driver for the StarFive JH7110 PLL clock controller and they work by reading and setting syscon registers. Co-developed-by: Emil Renner Berthing <[email protected]> Signed-off-by: Emil Renner Berthing <[email protected]> Signed-off-by: Xingyu Wu <[email protected]> Signed-off-by: Conor Dooley <[email protected]>
2023-07-18clk: qcom: turingcc-qcs404: fix missing resume during probeJohan Hovold1-1/+12
Drivers that enable runtime PM must make sure that the controller is runtime resumed before accessing its registers to prevent the power domain from being disabled. Fixes: 892df0191b29 ("clk: qcom: Add QCS404 TuringCC") Cc: [email protected] # 5.2 Cc: Bjorn Andersson <[email protected]> Signed-off-by: Johan Hovold <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Bjorn Andersson <[email protected]>
2023-07-18clk: qcom: mss-sc7180: fix missing resume during probeJohan Hovold1-1/+12
Drivers that enable runtime PM must make sure that the controller is runtime resumed before accessing its registers to prevent the power domain from being disabled. Fixes: 8def929c4097 ("clk: qcom: Add modem clock controller driver for SC7180") Cc: [email protected] # 5.7 Cc: Taniya Das <[email protected]> Signed-off-by: Johan Hovold <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Bjorn Andersson <[email protected]>
2023-07-18clk: qcom: q6sstop-qcs404: fix missing resume during probeJohan Hovold1-2/+13
Drivers that enable runtime PM must make sure that the controller is runtime resumed before accessing its registers to prevent the power domain from being disabled. Fixes: 6cdef2738db0 ("clk: qcom: Add Q6SSTOP clock controller for QCS404") Cc: [email protected] # 5.5 Signed-off-by: Johan Hovold <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Bjorn Andersson <[email protected]>
2023-07-18clk: qcom: lpasscc-sc7280: fix missing resume during probeJohan Hovold1-4/+12
Drivers that enable runtime PM must make sure that the controller is runtime resumed before accessing its registers to prevent the power domain from being disabled. Fixes: 4ab43d171181 ("clk: qcom: Add lpass clock controller driver for SC7280") Cc: [email protected] # 5.16 Cc: Taniya Das <[email protected]> Signed-off-by: Johan Hovold <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Bjorn Andersson <[email protected]>
2023-07-18clk: qcom: gcc-sc8280xp: fix runtime PM imbalance on probe errorsJohan Hovold1-3/+11
Make sure to decrement the runtime PM usage count before returning in case RCG dynamic frequency switch initialisation fails. Fixes: 2a541abd9837 ("clk: qcom: gcc-sc8280xp: Add runtime PM") Cc: Konrad Dybcio <[email protected]> Signed-off-by: Johan Hovold <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Bjorn Andersson <[email protected]>
2023-07-18clk: qcom: dispcc-sm8550: fix runtime PM imbalance on probe errorsJohan Hovold1-2/+11
Make sure to decrement the runtime PM usage count before returning in case regmap initialisation fails. Fixes: 90114ca11476 ("clk: qcom: add SM8550 DISPCC driver") Cc: [email protected] # 6.3 Cc: Neil Armstrong <[email protected]> Signed-off-by: Johan Hovold <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Bjorn Andersson <[email protected]>
2023-07-18clk: qcom: dispcc-sm8450: fix runtime PM imbalance on probe errorsJohan Hovold1-2/+11
Make sure to decrement the runtime PM usage count before returning in case regmap initialisation fails. Fixes: 16fb89f92ec4 ("clk: qcom: Add support for Display Clock Controller on SM8450") Cc: [email protected] # 6.1 Cc: Dmitry Baryshkov <[email protected]> Signed-off-by: Johan Hovold <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Bjorn Andersson <[email protected]>
2023-07-18clk: qcom: camcc-sc7180: fix async resume during probeJohan Hovold1-1/+1
To make sure that the controller is runtime resumed and its power domain is enabled before accessing its registers during probe, the synchronous runtime PM interface must be used. Fixes: 8d4025943e13 ("clk: qcom: camcc-sc7180: Use runtime PM ops instead of clk ones") Cc: [email protected] # 5.11 Cc: Stephen Boyd <[email protected]> Signed-off-by: Johan Hovold <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Bjorn Andersson <[email protected]>
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