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2023-08-14clk: imx: imx8: add audio clock mux driverShengjiu Wang2-1/+478
The Audio Clock Mux (ACM) is a collection of control registers and multiplexers that are used to route the audio source clocks to the audio peripherals. Each audio peripheral has its dedicated audio clock mux (which differ based on usage) and control register. Signed-off-by: Shengjiu Wang <[email protected]> Reviewed-by: Peng Fan <[email protected]> Reviewed-by: Abel Vesa <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Abel Vesa <[email protected]>
2023-08-14clk: imx: clk-imx8qxp-lpcg: Convert to devm_platform_ioremap_resource()Yangtao Li1-3/+1
Use devm_platform_ioremap_resource() to simplify code. Signed-off-by: Yangtao Li <[email protected]> Reviewed-by: Abel Vesa <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Abel Vesa <[email protected]>
2023-08-13clk: qcom: gcc-msm8917: Enable GPLL0_SLEEP_CLK_SRCOtto Pflüger1-1/+2
This is the parent clock of gpll0_early, so it needs to be enabled for gpll0_early to return the correct rate. Enable GPLL0_SLEEP_CLK_SRC by adding its existing definition to the clock list. This clock also doesn't work with clk_alpha_pll_ops, use clk_branch_simple_ops instead to make it enable and disable correctly. Signed-off-by: Otto Pflüger <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Bjorn Andersson <[email protected]>
2023-08-13clk: qcom: gcc-qdu1000: Update the RCGs opsImran Shaik1-29/+29
The clock RCGs are required to be parked at safe clock source(XO) during disable as per the hardware expectation and clk_rcg2_shared_ops are the closest implementation for the same. Hence update the clock RCG ops to clk_rcg2_shared_ops. Signed-off-by: Imran Shaik <[email protected]> Reviewed-by: Konrad Dybcio <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Bjorn Andersson <[email protected]>
2023-08-13clk: qcom: gcc-qdu1000: Update the SDCC clock RCG opsImran Shaik1-2/+2
Update the GCC SDCC clock RCG ops to clk_rcg2_floor_ops to avoid the overclocking issues on QDU1000 and QRU1000 SoCs. Signed-off-by: Imran Shaik <[email protected]> Reviewed-by: Konrad Dybcio <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Bjorn Andersson <[email protected]>
2023-08-13clk: qcom: gcc-qdu1000: Add support for GDSCsImran Shaik1-0/+42
Add the GDSCs support for QDU1000 and QRU1000 SoCs. Co-developed-by: Taniya Das <[email protected]> Signed-off-by: Taniya Das <[email protected]> Signed-off-by: Imran Shaik <[email protected]> Reviewed-by: Konrad Dybcio <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Bjorn Andersson <[email protected]>
2023-08-13clk: qcom: gcc-qdu1000: Add gcc_ddrss_ecpri_gsi_clk supportImran Shaik1-0/+21
Add the gcc_ddrss_ecpri_gsi_clk support as per the latest hardware version of QDU1000 and QRU100 SoCs. Signed-off-by: Imran Shaik <[email protected]> Reviewed-by: Konrad Dybcio <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Bjorn Andersson <[email protected]>
2023-08-13clk: qcom: gcc-qdu1000: Register gcc_gpll1_out_even clockImran Shaik1-0/+1
gcc_gpll1_out_even clock is referenced as a parent, but not registered with the clock framework. Hence add support to register the same. Fixes: 1c9efb0bc040 ("clk: qcom: Add QDU1000 and QRU1000 GCC support") Signed-off-by: Imran Shaik <[email protected]> Reviewed-by: Konrad Dybcio <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Bjorn Andersson <[email protected]>
2023-08-13clk: qcom: gcc-qdu1000: Fix clkref clocks handlingImran Shaik1-6/+4
Update the GCC clkref clock's halt_check to BRANCH_HALT, as it's status bit is not inverted in the latest hardware version of QDU1000 and QRU1000 SoCs. While at it, fix the gcc clkref clock ops as well. Fixes: 1c9efb0bc040 ("clk: qcom: Add QDU1000 and QRU1000 GCC support") Signed-off-by: Imran Shaik <[email protected]> Reviewed-by: Konrad Dybcio <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Bjorn Andersson <[email protected]>
2023-08-13clk: qcom: gcc-qdu1000: Fix gcc_pcie_0_pipe_clk_src clock handlingImran Shaik1-17/+6
Fix the gcc pcie pipe clock handling as per the clk_regmap_phy_mux_ops implementation to let the clock framework automatically park the clock at XO when the clock is switched off and restore the parent when the clock is switched on. Fixes: 1c9efb0bc040 ("clk: qcom: Add QDU1000 and QRU1000 GCC support") Co-developed-by: Taniya Das <[email protected]> Signed-off-by: Taniya Das <[email protected]> Signed-off-by: Imran Shaik <[email protected]> Reviewed-by: Konrad Dybcio <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Bjorn Andersson <[email protected]>
2023-08-13clk: qcom: gcc-sm8450: Use floor ops for SDCC RCGsKonrad Dybcio1-2/+2
Use the floor ops to prevent warnings like this at suspend exit and boot: mmc0: Card appears overclocked; req 800000 Hz, actual 25000000 Hz Fixes: db0c944ee92b ("clk: qcom: Add clock driver for SM8450") Signed-off-by: Konrad Dybcio <[email protected]> Reviewed-by: Vinod Koul <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Bjorn Andersson <[email protected]>
2023-08-13clk: qcom: ipq5332: drop the gcc_apss_axi_clk_src clockKathiravan T1-72/+39
With the removal of the mem noc clocks in the commit e224dc703521 ("clk: qcom: gcc-ipq5332: drop the mem noc clocks"), we can drop the gcc_apss_axi_clk_src clock as well, since there are no clocks uses this clock as a parent. Signed-off-by: Kathiravan T <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Bjorn Andersson <[email protected]>
2023-08-13clk: qcom: ipq5332: drop the mem noc clocksKathiravan T1-95/+0
Due to the recent design changes, all the mem noc clocks will be configured by the bootloaders and it will be access protected by the TZ firmware. So drop these clocks from the GCC driver. Signed-off-by: Kathiravan T <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Bjorn Andersson <[email protected]>
2023-08-13clk: qcom: gcc-msm8998: Don't check halt bit on some branch clksKonrad Dybcio1-3/+3
Some branch clocks are governed externally and we're only supposed to send a request concerning their shutdown, not actually ensure it happens. Use the BRANCH_HALT_SKIP define to skip checking the halt bit. Reviewed-by: Jeffrey Hugo <[email protected]> Signed-off-by: Konrad Dybcio <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Bjorn Andersson <[email protected]>
2023-08-13clk: qcom: gpucc-msm8998: Use the correct GPLL0 leg with old DTsKonrad Dybcio1-1/+1
GPUCC has its own GPLL0 legs - one for 1-1 and one for div-2 output. Add .name lookup to make sure older DTs consume the correct clock. Reviewed-by: Jeffrey Hugo <[email protected]> Tested-by: Jeffrey Hugo <[email protected]> Signed-off-by: Konrad Dybcio <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Bjorn Andersson <[email protected]>
2023-08-13clk: qcom: mmcc-msm8998: Properly consume GPLL0 inputsKonrad Dybcio1-27/+8
Up until now, the GPLL0_DIV MMSS input has been modeled as a fixed child of MMSS_GPLL0_DIV that's always-on. Properly representing the former in the GCC driver makes us unable to keep doing so. Consume MSS_GPLL0_DIV through fw_name ("gpll0_div") as well as add a fixed .name link to keep backwards compatibility. Reviewed-by: Jeffrey Hugo <[email protected]> Tested-by: Jeffrey Hugo <[email protected]> Signed-off-by: Konrad Dybcio <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Bjorn Andersson <[email protected]>
2023-08-13clk: qcom: gcc-msm8998: Control MMSS and GPUSS GPLL0 outputs properlyKonrad Dybcio1-0/+58
Up until now, we've been relying on some non-descript hardware magic to pinkypromise turn the clocks on for us. While new SoCs shine with that feature, MSM8998 can not always be fully trusted. Register the MMSS and GPUSS GPLL0 legs with the CCF to allow for manual enable voting. Reviewed-by: Jeffrey Hugo <[email protected]> Tested-by: Jeffrey Hugo <[email protected]> Signed-off-by: Konrad Dybcio <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Bjorn Andersson <[email protected]>
2023-08-11clk: qcom: Add Global Clock controller (GCC) driver for IPQ5018Sricharan Ramabadhran3-0/+3733
Add support for the global clock controller found on IPQ5018 based devices. Acked-by: Konrad Dybcio <[email protected]> Co-developed-by: Varadarajan Narayanan <[email protected]> Signed-off-by: Varadarajan Narayanan <[email protected]> Co-developed-by: Gokul Sriram Palanisamy <[email protected]> Signed-off-by: Gokul Sriram Palanisamy <[email protected]> Signed-off-by: Sricharan Ramabadhran <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Bjorn Andersson <[email protected]>
2023-08-10clk: rockchip: rv1126: Add PD_VO clock treeJagan Teki1-0/+59
PD_VO clock tree diagram in RV1126 is connected to - BIU_VO - VOP - RGA - IEP - DSIHOST Add entire PD_VO clock tree for rv1126. Signed-off-by: Jagan Teki <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Heiko Stuebner <[email protected]>
2023-08-09clk: sunxi-ng: nkm: Prefer current parent rateFrank Oltmanns1-1/+2
Similar to ccu_mp, if the current parent rate allows getting the ideal rate, prefer to not change the parent clock's rate. Reviewed-by: Jernej Skrabec <[email protected]> Signed-off-by: Frank Oltmanns <[email protected]> Link: https://lore.kernel.org/r/20230807-pll-mipi_set_rate_parent-v6-11-f173239a4b59@oltmanns.dev Signed-off-by: Chen-Yu Tsai <[email protected]>
2023-08-09clk: sunxi-ng: a64: select closest rate for pll-video0Frank Oltmanns1-22/+16
Selecting the closest rate for pll-video0 instead of the closest rate that is less than the requested rate has no downside for this clock, while allowing for selecting a more suitable rate, e.g. for the connected panels. Furthermore, the algorithm that sets an NKM clock's parent benefits from the closest rate. Without it, the NKM clock's rate might drift away from the requested rate in the multiple successive calls to ccu_nkm_determine_rate that the clk framework performs when setting a clock rate. Therefore, configure pll-video0 and, in consequence, all of its descendents to select the closest rate. Acked-by: Maxime Ripard <[email protected]> Reviewed-by: Jernej Skrabec <[email protected]> Signed-off-by: Frank Oltmanns <[email protected]> Link: https://lore.kernel.org/r/20230807-pll-mipi_set_rate_parent-v6-10-f173239a4b59@oltmanns.dev Signed-off-by: Chen-Yu Tsai <[email protected]>
2023-08-09clk: sunxi-ng: div: Support finding closest rateFrank Oltmanns1-0/+30
Add initalization macros for divisor clocks with mux (SUNXI_CCU_M_WITH_MUX) to support finding the closest rate. This clock type requires the appropriate flags to be set in the .common structure (for the mux part of the clock) and the .div part. Acked-by: Maxime Ripard <[email protected]> Reviewed-by: Jernej Skrabec <[email protected]> Signed-off-by: Frank Oltmanns <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Chen-Yu Tsai <[email protected]>
2023-08-09clk: sunxi-ng: mux: Support finding closest rateFrank Oltmanns2-12/+39
When finding the best rate for a mux clock, consider rates that are higher than the requested rate when CCU_FEATURE_ROUND_CLOSEST is used. Furthermore, introduce an initialization macro that sets this flag. Acked-by: Maxime Ripard <[email protected]> Reviewed-by: Jernej Skrabec <[email protected]> Signed-off-by: Frank Oltmanns <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Chen-Yu Tsai <[email protected]>
2023-08-09clk: sunxi-ng: nkm: Support finding closest rateFrank Oltmanns2-12/+10
When finding the best rate for a NKM clock, consider rates that are higher than the requested rate, if the CCU_FEATURE_CLOSEST_RATE flag is set by using the helper function ccu_is_better_rate(). Accommodate ccu_mux_helper_determine_rate to this change. Acked-by: Maxime Ripard <[email protected]> Reviewed-by: Jernej Skrabec <[email protected]> Signed-off-by: Frank Oltmanns <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Chen-Yu Tsai <[email protected]>
2023-08-09clk: sunxi-ng: nm: Support finding closest rateFrank Oltmanns2-11/+50
Use the helper function ccu_is_better_rate() to determine the rate that is closest to the requested rate, thereby supporting rates that are higher than the requested rate if the clock uses the CCU_FEATURE_CLOSEST_RATE. Add the macro SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK_MIN_MAX_CLOSEST which sets CCU_FEATURE_CLOSEST_RATE. To avoid code duplication, add the macros SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK_MIN_MAX_FEAT that allows selecting arbitrary features and use it in the original SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK_MIN_MAX as well as the newly introduced SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK_MIN_MAX_CLOSEST macros. Acked-by: Maxime Ripard <[email protected]> Reviewed-by: Jernej Skrabec <[email protected]> Signed-off-by: Frank Oltmanns <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Chen-Yu Tsai <[email protected]>
2023-08-09clk: sunxi-ng: Add helper function to find closest rateFrank Oltmanns2-0/+17
The default behaviour of clocks in the sunxi-ng driver is to select a clock rate that is closest to but less than the requested rate. Add the ccu_is_better_rate() helper function that - depending on the fact if thc CCU_FEATURE_CLOSEST_RATE flag is set - decides if a rate is closer than another rate. Acked-by: Maxime Ripard <[email protected]> Reviewed-by: Jernej Skrabec <[email protected]> Signed-off-by: Frank Oltmanns <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Chen-Yu Tsai <[email protected]>
2023-08-09clk: sunxi-ng: Add feature to find closest rateFrank Oltmanns1-0/+1
The default behaviour of clocks in the sunxi-ng driver is to select a clock rate that is closest to but less than the requested rate. Add the CCU_FEATURE_CLOSEST_RATE flag, which can be used to allow clocks to find the closest rate instead. Acked-by: Maxime Ripard <[email protected]> Acked-by: Jernej Skrabec <[email protected]> Signed-off-by: Frank Oltmanns <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Chen-Yu Tsai <[email protected]>
2023-08-09clk: sunxi-ng: a64: allow pll-mipi to set parent's rateFrank Oltmanns1-1/+2
The nkm clock now supports setting the parent's rate. Utilize this option to find the optimal rate for pll-mipi. Acked-by: Maxime Ripard <[email protected]> Reviewed-by: Jernej Skrabec <[email protected]> Signed-off-by: Frank Oltmanns <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Chen-Yu Tsai <[email protected]>
2023-08-09clk: sunxi-ng: nkm: consider alternative parent rates when determining rateFrank Oltmanns1-1/+43
In case the CLK_SET_RATE_PARENT flag is set, consider using a different parent rate when determining a new rate. To find the best match for the requested rate, perform the following steps for each NKM combination: - calculate the optimal parent rate, - find the best parent rate that the parent clock actually supports - use that parent rate to calculate the effective rate. In case the clk does not support setting the parent rate, use the same algorithm as before. Acked-by: Maxime Ripard <[email protected]> Signed-off-by: Frank Oltmanns <[email protected]> Reviewed-by: Chen-Yu Tsai <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Chen-Yu Tsai <[email protected]>
2023-08-09clk: sunxi-ng: nkm: Use correct parameter name for parent HWFrank Oltmanns1-1/+1
ccu_nkm_round_rate() takes a clk_hw as parameter "hw". Since "hw" is the nkm clock's parent clk_hw, not the clk_hw of the nkm clock itself, change the parameter name to "parent_hw" to make it more clear what we're dealing with. Acked-by: Maxime Ripard <[email protected]> Reviewed-by: Jernej Skrabec <[email protected]> Signed-off-by: Frank Oltmanns <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Chen-Yu Tsai <[email protected]>
2023-08-08clk: meson: axg-audio: move bindings include to main driverNeil Armstrong2-3/+2
Now the clock ids are no more defined in private headers, cleanup and include the dt-bindings headers from the main driver file. Signed-off-by: Neil Armstrong <[email protected]> Link: https://lore.kernel.org/r/20230607-topic-amlogic-upstream-clkid-public-migration-v2-19-38172d17c27a@linaro.org Signed-off-by: Jerome Brunet <[email protected]>
2023-08-08clk: meson: meson8b: move bindings include to main driverNeil Armstrong2-7/+3
Now the clock ids are no more defined in private headers, cleanup and include the dt-bindings headers from the main driver file. Signed-off-by: Neil Armstrong <[email protected]> Link: https://lore.kernel.org/r/20230607-topic-amlogic-upstream-clkid-public-migration-v2-18-38172d17c27a@linaro.org Signed-off-by: Jerome Brunet <[email protected]>
2023-08-08clk: meson: a1: move bindings include to main driverNeil Armstrong4-6/+4
Now the clock ids are no more defined in private headers, cleanup and include the dt-bindings headers from the main driver file. Signed-off-by: Neil Armstrong <[email protected]> Reviewed-by: Dmitry Rokosov <[email protected]> Link: https://lore.kernel.org/r/20230607-topic-amlogic-upstream-clkid-public-migration-v2-17-38172d17c27a@linaro.org Signed-off-by: Jerome Brunet <[email protected]>
2023-08-08clk: meson: eeclk: move bindings include to main driverNeil Armstrong6-9/+6
Now the clock ids are no more defined in private headers, cleanup and include the dt-bindings headers from the main driver file. Signed-off-by: Neil Armstrong <[email protected]> Link: https://lore.kernel.org/r/20230607-topic-amlogic-upstream-clkid-public-migration-v2-16-38172d17c27a@linaro.org Signed-off-by: Jerome Brunet <[email protected]>
2023-08-08clk: meson: aoclk: move bindings include to main driverNeil Armstrong6-45/+9
Now the clock ids are no more defined in private headers, cleanup and include the dt-bindings headers from the main driver file. Signed-off-by: Neil Armstrong <[email protected]> Link: https://lore.kernel.org/r/20230607-topic-amlogic-upstream-clkid-public-migration-v2-15-38172d17c27a@linaro.org Signed-off-by: Jerome Brunet <[email protected]>
2023-08-08dt-bindings: clk: axg-audio-clkc: expose all clock idsNeil Armstrong1-70/+0
Due to a policy change in clock ID bindings handling, expose all the "private" clock IDs to the public clock dt-bindings to move out of the previous maintenance scheme. This refers to a discussion at [1] & [2] with Krzysztof about the issue with the current maintenance. It was decided to move every axg-audio-clkc ID to the public clock dt-bindings headers to be merged in a single tree so we can safely add new clocks without having merge issues. [1] https://lore.kernel.org/all/[email protected]/ [2] https://lore.kernel.org/all/[email protected]/ Acked-by: Krzysztof Kozlowski <[email protected]> Signed-off-by: Neil Armstrong <[email protected]> Link: https://lore.kernel.org/r/20230607-topic-amlogic-upstream-clkid-public-migration-v2-14-38172d17c27a@linaro.org Signed-off-by: Jerome Brunet <[email protected]>
2023-08-08dt-bindings: clk: amlogic,a1-pll-clkc: expose all clock idsNeil Armstrong1-15/+0
Due to a policy change in clock ID bindings handling, expose all the "private" clock IDs to the public clock dt-bindings to move out of the previous maintenance scheme. This refers to a discussion at [1] & [2] with Krzysztof about the issue with the current maintenance. It was decided to move every A1 pll ID to the public clock dt-bindings headers to be merged in a single tree so we can safely add new clocks without having merge issues. [1] https://lore.kernel.org/all/[email protected]/ [2] https://lore.kernel.org/all/[email protected]/ Reviewed-by: Dmitry Rokosov <[email protected]> Acked-by: Krzysztof Kozlowski <[email protected]> Signed-off-by: Neil Armstrong <[email protected]> Link: https://lore.kernel.org/r/20230607-topic-amlogic-upstream-clkid-public-migration-v2-13-38172d17c27a@linaro.org Signed-off-by: Jerome Brunet <[email protected]>
2023-08-08dt-bindings: clk: amlogic,a1-peripherals-clkc: expose all clock idsNeil Armstrong1-63/+0
Due to a policy change in clock ID bindings handling, expose all the "private" clock IDs to the public clock dt-bindings to move out of the previous maintenance scheme. This refers to a discussion at [1] & [2] with Krzysztof about the issue with the current maintenance. It was decided to move every A1 peripherals ID to the public clock dt-bindings headers to be merged in a single tree so we can safely add new clocks without having merge issues. [1] https://lore.kernel.org/all/[email protected]/ [2] https://lore.kernel.org/all/[email protected]/ Reviewed-by: Dmitry Rokosov <[email protected]> Acked-by: Krzysztof Kozlowski <[email protected]> Signed-off-by: Neil Armstrong <[email protected]> Link: https://lore.kernel.org/r/20230607-topic-amlogic-upstream-clkid-public-migration-v2-12-38172d17c27a@linaro.org Signed-off-by: Jerome Brunet <[email protected]>
2023-08-08dt-bindings: clk: meson8b-clkc: expose all clock idsNeil Armstrong1-108/+0
Due to a policy change in clock ID bindings handling, expose all the "private" clock IDs to the public clock dt-bindings to move out of the previous maintenance scheme. This refers to a discussion at [1] & [2] with Krzysztof about the issue with the current maintenance. It was decided to move every meson8b-clkc ID to the public clock dt-bindings headers to be merged in a single tree so we can safely add new clocks without having merge issues. [1] https://lore.kernel.org/all/[email protected]/ [2] https://lore.kernel.org/all/[email protected]/ Acked-by: Krzysztof Kozlowski <[email protected]> Signed-off-by: Neil Armstrong <[email protected]> Link: https://lore.kernel.org/r/20230607-topic-amlogic-upstream-clkid-public-migration-v2-11-38172d17c27a@linaro.org Signed-off-by: Jerome Brunet <[email protected]>
2023-08-08dt-bindings: clk: g12a-aoclkc: expose all clock idsNeil Armstrong1-17/+0
Due to a policy change in clock ID bindings handling, expose all the "private" clock IDs to the public clock dt-bindings to move out of the previous maintenance scheme. This refers to a discussion at [1] & [2] with Krzysztof about the issue with the current maintenance. It was decided to move every g12a-aoclkc ID to the public clock dt-bindings headers to be merged in a single tree so we can safely add new clocks without having merge issues. [1] https://lore.kernel.org/all/[email protected]/ [2] https://lore.kernel.org/all/[email protected]/ Acked-by: Krzysztof Kozlowski <[email protected]> Signed-off-by: Neil Armstrong <[email protected]> Link: https://lore.kernel.org/r/20230607-topic-amlogic-upstream-clkid-public-migration-v2-10-38172d17c27a@linaro.org Signed-off-by: Jerome Brunet <[email protected]>
2023-08-08dt-bindings: clk: g12a-clks: expose all clock idsNeil Armstrong1-140/+0
Due to a policy change in clock ID bindings handling, expose all the "private" clock IDs to the public clock dt-bindings to move out of the previous maintenance scheme. This refers to a discussion at [1] & [2] with Krzysztof about the issue with the current maintenance. It was decided to move every g12a-clkc ID to the public clock dt-bindings headers to be merged in a single tree so we can safely add new clocks without having merge issues. [1] https://lore.kernel.org/all/[email protected]/ [2] https://lore.kernel.org/all/[email protected]/ Acked-by: Krzysztof Kozlowski <[email protected]> Signed-off-by: Neil Armstrong <[email protected]> Link: https://lore.kernel.org/r/20230607-topic-amlogic-upstream-clkid-public-migration-v2-9-38172d17c27a@linaro.org Signed-off-by: Jerome Brunet <[email protected]>
2023-08-08dt-bindings: clk: axg-clkc: expose all clock idsNeil Armstrong1-58/+0
Due to a policy change in clock ID bindings handling, expose all the "private" clock IDs to the public clock dt-bindings to move out of the previous maintenance scheme. This refers to a discussion at [1] & [2] with Krzysztof about the issue with the current maintenance. It was decided to move every axg-clkc ID to the public clock dt-bindings headers to be merged in a single tree so we can safely add new clocks without having merge issues. [1] https://lore.kernel.org/all/[email protected]/ [2] https://lore.kernel.org/all/[email protected]/ Acked-by: Krzysztof Kozlowski <[email protected]> Signed-off-by: Neil Armstrong <[email protected]> Link: https://lore.kernel.org/r/20230607-topic-amlogic-upstream-clkid-public-migration-v2-8-38172d17c27a@linaro.org Signed-off-by: Jerome Brunet <[email protected]>
2023-08-08dt-bindings: clk: gxbb-clkc: expose all clock idsNeil Armstrong1-76/+0
Due to a policy change in clock ID bindings handling, expose all the "private" clock IDs to the public clock dt-bindings to move out of the previous maintenance scheme. This refers to a discussion at [1] & [2] with Krzysztof about the issue with the current maintenance. It was decided to move every gxbb-clkc ID to the public clock dt-bindings headers to be merged in a single tree so we can safely add new clocks without having merge issues. [1] https://lore.kernel.org/all/[email protected]/ [2] https://lore.kernel.org/all/[email protected]/ Acked-by: Krzysztof Kozlowski <[email protected]> Signed-off-by: Neil Armstrong <[email protected]> Link: https://lore.kernel.org/r/20230607-topic-amlogic-upstream-clkid-public-migration-v2-7-38172d17c27a@linaro.org Signed-off-by: Jerome Brunet <[email protected]>
2023-08-08clk: meson: migrate axg-audio out of hw_onecell_data to drop NR_CLKSNeil Armstrong3-428/+424
The way hw_onecell_data is declared: struct clk_hw_onecell_data { unsigned int num; struct clk_hw *hws[]; }; makes it impossible to have the clk_hw table declared outside while using ARRAY_SIZE() to determine ".num" due to ".hws" being a flexible array member. Completely move out of hw_onecell_data and add a custom devm_of_clk_add_hw_provider() "get" callback to retrieve the clk_hw in order to finally get rid on the NR_CLKS define. Signed-off-by: Neil Armstrong <[email protected]> Link: https://lore.kernel.org/r/20230607-topic-amlogic-upstream-clkid-public-migration-v2-6-38172d17c27a@linaro.org Signed-off-by: Jerome Brunet <[email protected]>
2023-08-08clk: meson: migrate meson8b out of hw_onecell_data to drop NR_CLKSNeil Armstrong3-658/+660
The way hw_onecell_data is declared: struct clk_hw_onecell_data { unsigned int num; struct clk_hw *hws[]; }; makes it impossible to have the clk_hw table declared outside while using ARRAY_SIZE() to determine ".num" due to ".hws" being a flexible array member. Completely move out of hw_onecell_data and add a custom devm_of_clk_add_hw_provider() "get" callback to retrieve the clk_hw in order to finally get rid on the NR_CLKS define. Signed-off-by: Neil Armstrong <[email protected]> Link: https://lore.kernel.org/r/20230607-topic-amlogic-upstream-clkid-public-migration-v2-5-38172d17c27a@linaro.org Signed-off-by: Jerome Brunet <[email protected]>
2023-08-08clk: meson: migrate a1 clock drivers out of hw_onecell_data to drop NR_CLKSNeil Armstrong5-180/+183
The way hw_onecell_data is declared: struct clk_hw_onecell_data { unsigned int num; struct clk_hw *hws[]; }; makes it impossible to have the clk_hw table declared outside while using ARRAY_SIZE() to determine ".num" due to ".hws" being a flexible array member. Completely move out of hw_onecell_data and add a custom devm_of_clk_add_hw_provider() "get" callback to retrieve the clk_hw in order to finally get rid on the NR_CLKS define. Signed-off-by: Neil Armstrong <[email protected]> Reviewed-by: Dmitry Rokosov <[email protected]> Link: https://lore.kernel.org/r/20230607-topic-amlogic-upstream-clkid-public-migration-v2-4-38172d17c27a@linaro.org Signed-off-by: Jerome Brunet <[email protected]>
2023-08-08clk: meson: migrate meson-aoclk out of hw_onecell_data to drop NR_CLKSNeil Armstrong9-73/+68
The way hw_onecell_data is declared: struct clk_hw_onecell_data { unsigned int num; struct clk_hw *hws[]; }; makes it impossible to have the clk_hw table declared outside while using ARRAY_SIZE() to determine ".num" due to ".hws" being a flexible array member. Completely move out of hw_onecell_data and add a custom devm_of_clk_add_hw_provider() "get" callback to retrieve the clk_hw from the meson_aoclk_data struct to finally get rid on the NR_CLKS define. [jbrunet: Fixed whitespace checkpatch warning] Signed-off-by: Neil Armstrong <[email protected]> Link: https://lore.kernel.org/r/20230607-topic-amlogic-upstream-clkid-public-migration-v2-3-38172d17c27a@linaro.org Signed-off-by: Jerome Brunet <[email protected]>
2023-08-08clk: meson: migrate meson-eeclk out of hw_onecell_data to drop NR_CLKSNeil Armstrong9-1323/+1312
The way hw_onecell_data is declared: struct clk_hw_onecell_data { unsigned int num; struct clk_hw *hws[]; }; makes it impossible to have the clk_hw table declared outside while using ARRAY_SIZE() to determine ".num" due to ".hws" being a flexible array member. Completely move out of hw_onecell_data and add a custom devm_of_clk_add_hw_provider() "get" callback to retrieve the clk_hw from the meson_eeclkc_data struct to finally get rid on the NR_CLKS define. Signed-off-by: Neil Armstrong <[email protected]> Link: https://lore.kernel.org/r/20230607-topic-amlogic-upstream-clkid-public-migration-v2-2-38172d17c27a@linaro.org Signed-off-by: Jerome Brunet <[email protected]>
2023-08-08clk: meson: introduce meson-clkc-utilsNeil Armstrong4-0/+48
Let's introduce a new module called meson-clkc-utils that will contain shared utility functions for all Amlogic clock controller drivers. The first utility function is a replacement of of_clk_hw_onecell_get in order to get rid of the NR_CLKS define in all Amlogic clock drivers. The goal is to move all duplicate probe and init code in this module. [jbrunet: Fixed MODULE_LICENCE checkpatch warning] Signed-off-by: Neil Armstrong <[email protected]> Link: https://lore.kernel.org/r/20230607-topic-amlogic-upstream-clkid-public-migration-v2-1-38172d17c27a@linaro.org Signed-off-by: Jerome Brunet <[email protected]>
2023-08-04clk: ti: Replace kstrdup() + strreplace() with kstrdup_and_replace()Andy Shevchenko2-6/+7
Replace open coded functionality of kstrdup_and_replace() with a call. Signed-off-by: Andy Shevchenko <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Stephen Boyd <[email protected]>
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