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2023-10-04clk: imx: imx6sx: Allow a different LCDIF1 clock parentFabio Estevam1-3/+11
It is not a good idea to hardcode the LCDIF1 parent inside the clock driver because some users may want to use a different clock parent for LCDIF1. One of the reasons could be related to EMI tests. Remove the harcoded LCDIF1 parent when the LCDIF1 parent is described via devicetree. Old dtb's that do not describe the LCDIF1 parent via devicetree will use the same PLL5 clock as parent to keep the original behavior. Signed-off-by: Fabio Estevam <[email protected]> Reviewed-by: Abel Vesa <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Abel Vesa <[email protected]>
2023-10-04clk: imx: imx8mq: correct error handling pathPeng Fan1-7/+10
Avoid memory leak in error handling path. It does not make much sense for the SoC without clk driver, to make program behavior correct, let's fix it. Fixes: b80522040cd3 ("clk: imx: Add clock driver for i.MX8MQ CCM") Reported-by: kernel test robot <[email protected]> Reported-by: Dan Carpenter <[email protected]> Closes: https://lore.kernel.org/r/[email protected]/ Signed-off-by: Peng Fan <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Abel Vesa <[email protected]>
2023-10-04clk: imx: imx8: Simplify clk_imx_acm_detach_pm_domains()Christophe JAILLET1-5/+3
The return value of clk_imx_acm_detach_pm_domains() is never used. Simplify the code and turn it into a void function. Reviewed-by: Peng Fan <[email protected]> Signed-off-by: Christophe JAILLET <[email protected]> Signed-off-by: Abel Vesa <[email protected]>
2023-10-04clk: imx: imx8: Add a message in case of ↵Christophe JAILLET1-2/+1
devm_clk_hw_register_mux_parent_data_table() error If devm_clk_hw_register_mux_parent_data_table() fails, we branch to the error handling path and imx_check_clk_hws() is never called. Actually, imx_check_clk_hws() is a no-op because values in 'hws' are either valid, either NULL. Move the call to imx_check_clk_hws() in the error handling path, so that an error is logged. Fixes: d3a0946d7ac9 ("clk: imx: imx8: add audio clock mux driver") Reviewed-by: Peng Fan <[email protected]> Signed-off-by: Christophe JAILLET <[email protected]> Signed-off-by: Abel Vesa <[email protected]>
2023-10-04clk: imx: imx8: Fix an error handling path in imx8_acm_clk_probe()Christophe JAILLET1-3/+6
If an error occurs after a successful clk_imx_acm_attach_pm_domains() call, it must be undone. Add an explicit error handling path, re-order the code and add the missing clk_imx_acm_detach_pm_domains() call. Fixes: d3a0946d7ac9 ("clk: imx: imx8: add audio clock mux driver") Reviewed-by: Peng Fan <[email protected]> Signed-off-by: Christophe JAILLET <[email protected]> Signed-off-by: Abel Vesa <[email protected]>
2023-10-04clk: imx: imx8: Fix an error handling path if ↵Christophe JAILLET1-0/+1
devm_clk_hw_register_mux_parent_data_table() fails If a devm_clk_hw_register_mux_parent_data_table() call fails, it is likely that the probe should fail with an error code. Set 'ret' before leaving the function. Fixes: d3a0946d7ac9 ("clk: imx: imx8: add audio clock mux driver") Reviewed-by: Peng Fan <[email protected]> Signed-off-by: Christophe JAILLET <[email protected]> Signed-off-by: Abel Vesa <[email protected]>
2023-10-04clk: imx: imx8: Fix an error handling path in clk_imx_acm_attach_pm_domains()Christophe JAILLET1-2/+4
If a dev_pm_domain_attach_by_id() call fails, previously allocated resources need to be released. Fixes: d3a0946d7ac9 ("clk: imx: imx8: add audio clock mux driver") Reviewed-by: Peng Fan <[email protected]> Signed-off-by: Christophe JAILLET <[email protected]> Signed-off-by: Abel Vesa <[email protected]>
2023-10-04clk: imx: Select MXC_CLK for CLK_IMX8QXPAbel Vesa1-0/+1
If the i.MX8QXP clock provider is built-in but the MXC_CLK is built as module, build fails: aarch64-linux-ld: drivers/clk/imx/clk-imx8-acm.o: in function `imx8_acm_clk_probe': clk-imx8-acm.c:(.text+0x3d0): undefined reference to `imx_check_clk_hws' Fix that by selecting MXC_CLK in case of CLK_IMX8QXP. Fixes: c2cccb6d0b33 ("clk: imx: add imx8qxp clk driver") Closes: https://lore.kernel.org/all/[email protected]/ Reported-by: Randy Dunlap <[email protected]> Reviewed-by: Peng Fan <[email protected]> Acked-by: Randy Dunlap <[email protected]> Tested-by: Randy Dunlap <[email protected]> Signed-off-by: Abel Vesa <[email protected]>
2023-09-27clk: meson: S4: add support for Amlogic S4 SoC peripheral clock controllerYu Tu4-0/+3881
Add the peripherals clock controller driver in the S4 SoC family. [jbrunet: remove extra new line at end of s4-peripherals.h] Signed-off-by: Yu Tu <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Jerome Brunet <[email protected]>
2023-09-27clk: meson: S4: add support for Amlogic S4 SoC PLL clock driverYu Tu4-0/+918
Add the S4 PLL clock controller driver in the S4 SoC family. Signed-off-by: Yu Tu <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Jerome Brunet <[email protected]>
2023-09-26clk: renesas: r8a7795: Constify r8a7795_*_clksMarek Vasut1-2/+2
Make r8a7795_core_clks and r8a7795_mod_clks arrays const and align them with the other clock tables in other *cpg-mssr.c . No functional change. Signed-off-by: Marek Vasut <[email protected]> Reviewed-by: Geert Uytterhoeven <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Geert Uytterhoeven <[email protected]>
2023-09-20clk: qcom: gcc-sm8150: Fix gcc_sdcc2_apps_clk_srcDanila Tikhonov1-1/+1
Set .flags = CLK_OPS_PARENT_ENABLE to fix "gcc_sdcc2_apps_clk_src: rcg didn't update its configuration" error. Fixes: 2a1d7eb854bb ("clk: qcom: gcc: Add global clock controller driver for SM8150") Tested-by: Arseniy Velikanov <[email protected]> Signed-off-by: Danila Tikhonov <[email protected]> Reviewed-by: Konrad Dybcio <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Bjorn Andersson <[email protected]>
2023-09-20Merge branch '[email protected]' into clk-for-6.7Bjorn Andersson4-0/+2928
Merge the SM4450 RPMHCC and GCC through a topic branch, to allow reuse of the defines from the DeviceTree binding in the DeviceTree source.
2023-09-20clk: qcom: Add GCC driver support for SM4450Ajit Pandey3-0/+2907
Add Global Clock Controller (GCC) support for SM4450 platform. Signed-off-by: Ajit Pandey <[email protected]> Reviewed-by: Dmitry Baryshkov <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Bjorn Andersson <[email protected]>
2023-09-20clk: qcom: rpmh: Add RPMH clocks support for SM4450Ajit Pandey1-0/+21
Add support for RPMH clocks for SM4450 platform. Signed-off-by: Ajit Pandey <[email protected]> Reviewed-by: Dmitry Baryshkov <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Bjorn Andersson <[email protected]>
2023-09-20clk: qcom: mmcc-msm8974: remove ocmemcx_ahb_clkLuca Weiss1-18/+0
According to a commit in the 3.4 vendor kernel sources[0] the ocmemcx_ahb_clk clock "is controlled by RPM and should not be touched by APPS.". [0] https://git.codelinaro.org/clo/la/kernel/msm/-/commit/37df5f2d91b4d5768b37fcaacaeea958dd683ebc And indeed, when using MDSS+GPU+OCMEM on MSM8226 and not using clk_ignore_unused, when Linux tries to disable the clock the device crashes and reboots. And since there's also no evidence of this clock in msm8974 vendor kernel sources, remove the clock for msm8226 and msm8974. Fixes: d8b212014e69 ("clk: qcom: Add support for MSM8974's multimedia clock controller (MMCC)") Signed-off-by: Luca Weiss <[email protected]> Reviewed-by: Konrad Dybcio <[email protected]> Link: https://lore.kernel.org/r/20230902-msm8226-ocmemcx_ahb_clk-remove-v1-1-8124dbde83b9@z3ntu.xyz Signed-off-by: Bjorn Andersson <[email protected]>
2023-09-20clk: scmi: Add support for .is_enabled clk_opsCristian Marussi1-3/+20
Add support for .is_enabled atomic clk_ops using the related SCMI clock operation in atomic mode, if available. Note that the .is_enabled callback will be supported by this SCMI clock driver only if the configured underlying SCMI transport does support atomic operations. CC: Michael Turquette <[email protected]> CC: Stephen Boyd <[email protected]> CC: [email protected] Signed-off-by: Cristian Marussi <[email protected]> Acked-by: Stephen Boyd <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Sudeep Holla <[email protected]>
2023-09-20firmware: arm_scmi: Simplify enable/disable clock operationsCristian Marussi1-4/+7
SCMI clock enable/disable operations come in 2 different flavours which simply just differ in how the underlying SCMI transactions is carried on: atomic or not. Currently we expose such SCMI operations through 2 distinctly named wrappers, that, in turn, are wrapped into another couple of similarly and distinctly named callbacks inside SCMI clock driver user. Reduce the churn of duplicated wrappers by adding a param to SCMI clock enable/disable operations to ask for atomic operation while removing the _atomic version of such operations. No functional change. CC: Michael Turquette <[email protected]> CC: Stephen Boyd <[email protected]> CC: [email protected] Signed-off-by: Cristian Marussi <[email protected]> Acked-by: Stephen Boyd <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Sudeep Holla <[email protected]>
2023-09-20clk: qcom: mmcc-msm8998: Fix the SMMU GDSCKonrad Dybcio1-1/+3
The SMMU GDSC doesn't have to be ALWAYS-ON and shouldn't feature the HW_CTRL flag (it's separate from hw_ctrl_addr). In addition to that, it should feature a cxc entry for bimc_smmu_axi_clk and be marked as votable. Fix all of these issues. Fixes: d14b15b5931c ("clk: qcom: Add MSM8998 Multimedia Clock Controller (MMCC) driver") Signed-off-by: Konrad Dybcio <[email protected]> Reviewed-by: Jeffrey Hugo <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Bjorn Andersson <[email protected]>
2023-09-20clk: qcom: mmcc-msm8998: Don't check halt bit on some branch clksKonrad Dybcio1-0/+3
Some branch clocks are governed externally and we're only supposed to send a request concerning their shutdown, not actually ensure it happens. Use the BRANCH_HALT_SKIP define to skip checking the halt bit. Fixes: d14b15b5931c ("clk: qcom: Add MSM8998 Multimedia Clock Controller (MMCC) driver") Reviewed-by: Jeffrey Hugo <[email protected]> Signed-off-by: Konrad Dybcio <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Bjorn Andersson <[email protected]>
2023-09-19clk: qcom: clk-rcg2: Fix clock rate overflow for high parent frequenciesDevi Priya1-10/+4
If the parent clock rate is greater than unsigned long max/2 then integer overflow happens when calculating the clock rate on 32-bit systems. As RCG2 uses half integer dividers, the clock rate is first being multiplied by 2 which will overflow the unsigned long max value. Hence, replace the common pattern of doing 64-bit multiplication and then a do_div() call with simpler mult_frac call. Fixes: bcd61c0f535a ("clk: qcom: Add support for root clock generators (RCGs)") Signed-off-by: Devi Priya <[email protected]> Reviewed-by: Marijn Suijten <[email protected]> Link: https://lore.kernel.org/r/[email protected] [bjorn: Also drop unnecessary {} around single statements] Signed-off-by: Bjorn Andersson <[email protected]>
2023-09-19clk: qcom: gcc-msm8996: Remove RPM bus clocksKonrad Dybcio1-232/+5
The GCC driver contains clocks that are owned (meaning configured and scaled) by the RPM core. Remove them from Linux to stop interjecting the RPM's logic. Fixes: b1e010c0730a ("clk: qcom: Add MSM8996 Global Clock Control (GCC) driver") Signed-off-by: Konrad Dybcio <[email protected]> Reviewed-by: Dmitry Baryshkov <[email protected]> Tested-by: Dmitry Baryshkov <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Bjorn Andersson <[email protected]>
2023-09-19clk: qcom: ipq5332: Drop set rate parent from gpll0 dependent clocksVaradarajan Narayanan1-2/+0
IPQ5332's GPLL0's nominal/turbo frequency is 800MHz. This must not be scaled based on the requirement of dependent clocks. Hence remove the CLK_SET_RATE_PARENT flag. Fixes: 3d89d52970fd ("clk: qcom: add Global Clock controller (GCC) driver for IPQ5332 SoC") Signed-off-by: Varadarajan Narayanan <[email protected]> Reviewed-by: Kathiravan T <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Bjorn Andersson <[email protected]>
2023-09-19Merge branch '[email protected]' into clk-for-6.7Bjorn Andersson5-0/+3603
Merge the SM8550 camera clock controller patches through a topic branch, to make them available for the DeviceTree source as well.
2023-09-19clk: qcom: camcc-sm8550: Add support for qdss, sleep and xo clocksJagadeesh Kona1-0/+181
Add support for camera qdss, sleep and xo clocks. Co-developed-by: Taniya Das <[email protected]> Signed-off-by: Taniya Das <[email protected]> Signed-off-by: Jagadeesh Kona <[email protected]> Reviewed-by: Dmitry Baryshkov <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Bjorn Andersson <[email protected]>
2023-09-19clk: qcom: camcc-sm8550: Add camera clock controller driver for SM8550Jagadeesh Kona3-0/+3391
Add support for the camera clock controller for camera clients to be able to request for camcc clocks on SM8550 platform. Co-developed-by: Taniya Das <[email protected]> Signed-off-by: Taniya Das <[email protected]> Signed-off-by: Jagadeesh Kona <[email protected]> Reviewed-by: Konrad Dybcio <[email protected]> Reviewed-by: Dmitry Baryshkov <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Bjorn Andersson <[email protected]>
2023-09-19clk: qcom: clk-alpha-pll: Add support for lucid ole pll configureJagadeesh Kona2-0/+31
Lucid ole pll has as extra RINGOSC_CAL_L field in L register in addition to the fields that are part of lucid evo pll, hence add support for lucid ole pll configure function to configure the ole plls. Signed-off-by: Jagadeesh Kona <[email protected]> Reviewed-by: Dmitry Baryshkov <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Bjorn Andersson <[email protected]>
2023-09-18clk: renesas: r9a06g032: Name anonymous structsRalph Siemsen1-30/+33
Clarify the content of the r9a06g032_clkdesc structure by naming the remaining anonymous structures defined inside. Renaming each field and updating the doc then becomes necessary in order to avoid name duplications and kdoc warnings. Signed-off-by: Ralph Siemsen <[email protected]> Reviewed-by: Miquel Raynal <[email protected]> Reviewed-by: Geert Uytterhoeven <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Geert Uytterhoeven <[email protected]>
2023-09-18clk: renesas: r9a06g032: Fix kerneldoc warningRalph Siemsen1-0/+1
Mention the 'dual' structure in the kdoc. This fixes the following W=1 warning during build: > drivers/clk/renesas/r9a06g032-clocks.c:119: warning: Function parameter or member 'dual' not described in 'r9a06g032_clkdesc' Reported-by: kernel test robot <[email protected]> Closes: https://lore.kernel.org/oe-kbuild-all/[email protected]/ Signed-off-by: Ralph Siemsen <[email protected]> Reviewed-by: Miquel Raynal <[email protected]> Reviewed-by: Geert Uytterhoeven <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Geert Uytterhoeven <[email protected]>
2023-09-18clk: renesas: rzg2l: Use u32 for flag and mux_flagsClaudiu Beznea1-2/+2
flag and mux_flags are intended to keep bit masks. Use u32 type for it. Signed-off-by: Claudiu Beznea <[email protected]> Reviewed-by: Geert Uytterhoeven <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Geert Uytterhoeven <[email protected]>
2023-09-18clk: renesas: rzg2l: Use FIELD_GET() for PLL register fieldsClaudiu Beznea1-5/+5
Use FIELD_GET() for PLL register fields. This is its purpose. Signed-off-by: Claudiu Beznea <[email protected]> Reviewed-by: Geert Uytterhoeven <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Geert Uytterhoeven <[email protected]>
2023-09-18clk: renesas: rzg2l: Simplify the logic in rzg2l_mod_clock_endisable()Claudiu Beznea1-3/+2
The bitmask << 16 is anyway set on both branches of if thus move it before the if and set the lower bits of registers only in case clock is enabled. Signed-off-by: Claudiu Beznea <[email protected]> Reviewed-by: Geert Uytterhoeven <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Geert Uytterhoeven <[email protected]>
2023-09-18clk: renesas: rzg2l: Use core->name for clock nameClaudiu Beznea1-1/+1
core->name already contains the clock name thus, there is no need to check the GET_SHIFT(core->conf) to decide on it. Signed-off-by: Claudiu Beznea <[email protected]> Reviewed-by: Geert Uytterhoeven <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Geert Uytterhoeven <[email protected]>
2023-09-13clk: qcom: hfpll: Add MSM8976 PLL dataAdam Skladowski1-0/+54
Add PLL configuration for MSM8976 SoC, this SoC offers 3 HFPLL. Small cluster offers two presets for 652-902Mhz range and 902Mhz-1.47Ghz. For simplicity only add second range as smaller frequencies can be obtained via apcs divider or safe parent this also saves us a hassle of reconfiguring VCO bit and config_val. A72 and CCI cluster only use single frequency range with their outputs/post_dividers/vco_bits being static. Signed-off-by: Adam Skladowski <[email protected]> Reviewed-by: Konrad Dybcio <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Bjorn Andersson <[email protected]>
2023-09-13clk: qcom: hfpll: Allow matching pdataAdam Skladowski1-2/+3
HFPLL driver can be used to drive PLLs also on different SoCs like MSM8976 On MSM8976 each PLL gets it own different configuration, add matching pdata to driver to support multiple configurations. Signed-off-by: Adam Skladowski <[email protected]> Reviewed-by: Konrad Dybcio <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Bjorn Andersson <[email protected]>
2023-09-13clk: qcom: clk-hfpll: Configure l_val in init when requiredAdam Skladowski2-0/+5
Add support for pre-configuring default frequency multiplier, this appears to be required on some platforms like MSM8976. Without configuring L_VAL device reboots when trying to bring PLL up. Signed-off-by: Adam Skladowski <[email protected]> Reviewed-by: Konrad Dybcio <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Bjorn Andersson <[email protected]>
2023-09-12clk: tegra: fix error return case for recalc_rateTimo Alho1-1/+1
tegra-bpmp clocks driver makes implicit conversion of signed error code to unsigned value in recalc_rate operation. The behavior for recalc_rate, according to it's specification, should be that "If the driver cannot figure out a rate for this clock, it must return 0." Fixes: ca6f2796eef7 ("clk: tegra: Add BPMP clock driver") Signed-off-by: Timo Alho <[email protected]> Signed-off-by: Mikko Perttunen <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Stephen Boyd <[email protected]>
2023-09-11clk: si521xx: Fix regmap write accessorMarek Vasut1-3/+4
Rework the write operation such that the Byte Count register is written with a single raw i2c write outside of regmap using transfer which does specify the number of bytes to be transfered, one in this case, and which makes the expected subsequent write transfer look like address+register+data, and then make use of this method. Without this change, the Byte Count register write in probe() would succeed as it would provide the byte count as part of its write payload, but any subsequent writes would fail due to this Byte Count register programming. Such failing writes happens e.g. during resume, when restoring the regmap content. Fixes: edc12763a3a2 ("clk: si521xx: Clock driver for Skyworks Si521xx I2C PCIe clock generators") Signed-off-by: Marek Vasut <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Stephen Boyd <[email protected]>
2023-09-11clk: si521xx: Use REGCACHE_FLAT instead of NONEMarek Vasut1-1/+1
In order to reload registers into the clock generator on resume using regcache_sync(), it is necessary to select one of the regcache types which are not NONE. Since this device has some 7 registers, use the simplest one, FLAT. The regcache code complains about REGCACHE_NONE being selected and generates a WARNING, this fixes that warning. Fixes: edc12763a3a2 ("clk: si521xx: Clock driver for Skyworks Si521xx I2C PCIe clock generators") Signed-off-by: Marek Vasut <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Stephen Boyd <[email protected]>
2023-09-11clk: sprd: Fix thm_parents incorrect configurationZhifeng Tang1-1/+1
The thm*_clk have two clock sources 32k and 250k,excluding 32m. Fixes: af3bd36573e3 ("clk: sprd: Add clocks support for UMS512") Signed-off-by: Zhifeng Tang <[email protected]> Acked-by: Chunyan Zhang <[email protected]> Reviewed-by: Baolin Wang <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Stephen Boyd <[email protected]>
2023-09-11clk: vc3: Make vc3_clk_mux enum values based on vc3_clk enum valuesBiju Das1-8/+8
Make vc3_clk_mux enum values depend upon vc3_clk enum values to avoid any accidental breakage in the future. Signed-off-by: Biju Das <[email protected]> Link: https://lore.kernel.org/r/[email protected] Reviewed-by: Geert Uytterhoeven <[email protected]> Signed-off-by: Stephen Boyd <[email protected]>
2023-09-11clk: vc3: Fix output clock mappingBiju Das1-34/+34
According to Table 3. ("Output Source") in the 5P35023 datasheet, the output clock mapping should be 0=REF, 1=SE1, 2=SE2, 3=SE3, 4=DIFF1, 5=DIFF2. But the code uses inverse. Fix this mapping issue. Suggested-by: Geert Uytterhoeven <[email protected]> Closes: https://lore.kernel.org/all/CAMuHMdUHD+bEco=WYTYWsTAyRt3dTQQt4Xpaejss0Y2ZpLCMNg@mail.gmail.com/ Fixes: 6e9aff555db7 ("clk: Add support for versa3 clock driver") Signed-off-by: Biju Das <[email protected]> Reviewed-by: Geert Uytterhoeven <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Stephen Boyd <[email protected]>
2023-09-11clk: vc3: Fix 64 by 64 divisionBiju Das1-3/+2
Fix the below cocci warnings by replacing do_div()->div64_ul() and bound the result with a max value of U16_MAX. cocci warnings: drivers/clk/clk-versaclock3.c:404:2-8: WARNING: do_div() does a 64-by-32 division, please consider using div64_ul instead. Reported-by: Julia Lawall <[email protected]> Closes: https://lore.kernel.org/r/[email protected]/ Fixes: 6e9aff555db7 ("clk: Add support for versa3 clock driver") Signed-off-by: Biju Das <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Stephen Boyd <[email protected]>
2023-09-11clk: gate: fix comment typo and grammarBaruch Siach1-1/+1
Change ouput -> output. While at it change also grammatically incorrect "it's" to "its". Signed-off-by: Baruch Siach <[email protected]> Link: https://lore.kernel.org/r/d47978a09dd0320f9929a19fa3e829608a02b224.1693485415.git.baruch@tkos.co.il Signed-off-by: Stephen Boyd <[email protected]>
2023-09-11clk: asm9620: Remove 'hw' local variable that isn't checkedStephen Boyd1-3/+3
The 'hw' pointer local variable in this function became unused after commit f5290d8e4f0c ("clk: asm9260: use parent index to link the reference clock"). Remove it to silence an unused but set variable warning. drivers/clk/clk-asm9260.c:258:17: warning: variable 'hw' set but not used [-Wunused-but-set-variable] struct clk_hw *hw, *pll_hw; ^ 1 warning generated. Cc: Dmitry Baryshkov <[email protected]> Fixes: f5290d8e4f0c ("clk: asm9260: use parent index to link the reference clock") Reported-by: kernel test robot <[email protected]> Closes: https://lore.kernel.org/oe-kbuild-all/[email protected]/ Signed-off-by: Stephen Boyd <[email protected]> Link: https://lore.kernel.org/r/[email protected]
2023-09-11clk: renesas: r9a06g032: Use for_each_compatible_node()Yang Yingliang1-3/+2
Use for_each_compatible_node() instead of open-coding it. Signed-off-by: Yang Yingliang <[email protected]> Reviewed-by: Geert Uytterhoeven <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Geert Uytterhoeven <[email protected]>
2023-08-30Merge tag 'clk-for-linus' of ↵Linus Torvalds320-6457/+10989
git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux Pull clk subsystem updates from Stephen Boyd: "This pull request is full of clk driver changes. In fact, there aren't any changes to the clk framework this time around. That's probably because everyone was on vacation (yours truly included). We did lose a couple clk drivers this time around because nobody was using those devices. That skews the diffstat a bit, but either way, nothing looks out of the ordinary here. The usual suspects are chugging along adding support for more SoCs and fixing bugs. If I had to choose, I'd say the theme for the past few months has been "polish". There's quite a few patches that migrate to devm_platform_ioremap_resource() in here. And there's more than a handful of patches that move the NR_CLKS define from the DT binding header to the driver. There's even patches that migrate drivers to use clk_parent_data and clk_hw to describe clk tree topology. It seems that the spring (summer?) cleaning bug got some folks, or the semiconductor shortage finally hit the software side. New Drivers: - StarFive JH7110 SoC clock drivers - Qualcomm IPQ5018 Global Clock Controller driver - Versa3 clk generator to support 48KHz playback/record with audio codec on RZ/G2L SMARC EVK Removed Drivers: - Remove non-OF mmp clk drivers - Remove OXNAS clk driver Updates: - Add __counted_by to struct clk_hw_onecell_data and struct spmi_pmic_div_clk_cc - Move defines for numbers of clks (NR_CLKS) from DT headers to drivers - Introduce kstrdup_and_replace() and use it - Add PLL rates for Rockchip rk3568 - Add the display clock tree for Rockchip rv1126 - Add Audio Clock Generator (ADG) clocks on Renesas R-Car Gen3 and RZ/G2 SoCs - Convert sun9i-mmc clock to use devm_platform_get_and_ioremap_resource() - Fix function name in a comment in ccu_mmc_timing.c - Parameter name correction for ccu_nkm_round_rate() - Implement CLK_SET_RATE_PARENT for Allwinner NKM clocks, i.e. consider alternative parent rates when determining clock rates - Set CLK_SET_RATE_PARENT for Allwinner A64 pll-mipi - Support finding closest (as opposed to closest but not higher) clock rate for NM, NKM, mux and div type clocks, as use it for Allwinner A64 pll-video0 - Prefer current parent rate if able to generate ideal clock rate for Allwinner NKM clocks - Clean up Qualcomm SMD RPM driver, with interconnect bus clocks moved out to the interconnect drivers - Fix various PM runtime bugs across many Qualcomm clk drivers - Migrate Qualcomm MDM9615 is to parent_hw and parent_data - Add network related resets on Qualcomm IPQ4019 - Add a couple missing USB related clocks to Qualcomm IPQ9574 - Add missing gpll0_sleep_clk_src to Qualcomm MSM8917 global clock controller - In the Qualcomm QDU1000 global clock controller, GDSCs, clkrefs, and GPLL1 are added, while PCIe pipe clock, SDCC rcg ops are corrected - Add missing GDSCs to and correct GDSCs for the SC8280XP global clock controller driver - Support retention for the Qualcomm SC8280XP display clock controller GDSCs. - Qualcommm's SDCC apps_clk_src is marked with CLK_OPS_PARENT_ENABLE to fix issues with missing parent clocks across sc7180, sm7150, sm6350 and sm8250, while sm8450 is corrected to use floor ops - Correct Qualcomm SM6350 GPU clock controller's clock supplies - Drop unwanted clocks from the Qualcomm IPQ5332 GCC driver - Add missing OXILICX GDSC to Qualcomm MSM8226 GCC - Change the delay in the Qualcomm reset controller to fsleep() for correctness - Extend the Qualcomm SM83550 Video clock controller to support SC8280XP - Add graphics clock support on Renesas RZ/G2M, RZ/G2N, RZ/G2E, and R-Car H3, M3-W, and M3-N SoCs - Add Clocked Serial Interface (CSI) clocks on Renesas RZ/V2M - Add PWM (MTU3) clock and reset on Renesas RZ/G2UL and RZ/Five - Add the PDM IPC clock for i.MX93 - Add 519.75MHz frequency support for i.MX9 PLL - Simplify the .determine_rate() implementation for i.MX GPR mux - Make the i.MX8QXP LPCG clock use devm_platform_ioremap_resource() - Add the audio mux clock to i.MX8 - Fix the SPLL2 MULT range for PLLv4 - Update the SPLL2 type in i.MX8ULP - Fix the SAI4 clock on i.MX8MP - Add silicon revision print for i.MX25 on clocks init - Drop the return value from __mx25_clocks_init() - Fix the clock pauses on no-op set_rate for i.MX8M composite clock - Drop restrictions for i.MX PLL14xx and fix its max prediv value - Drop the 393216000 and 361267200 from i.MX PLL14xx rate table to allow glitch free switching" * tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux: (207 commits) clk: qcom: Fix SM_GPUCC_8450 dependencies clk: lmk04832: Support using PLL1_LD as SPI readback pin clk: lmk04832: Don't disable vco clock on probe fail clk: lmk04832: Set missing parent_names for output clocks clk: mvebu: Convert to devm_platform_ioremap_resource() clk: nuvoton: Convert to devm_platform_ioremap_resource() clk: socfpga: agilex: Convert to devm_platform_ioremap_resource() clk: ti: Use devm_platform_get_and_ioremap_resource() clk: mediatek: Convert to devm_platform_ioremap_resource() clk: hsdk-pll: Convert to devm_platform_ioremap_resource() clk: gemini: Convert to devm_platform_ioremap_resource() clk: fsl-sai: Convert to devm_platform_ioremap_resource() clk: bm1880: Convert to devm_platform_ioremap_resource() clk: axm5516: Convert to devm_platform_ioremap_resource() clk: actions: Convert to devm_platform_ioremap_resource() clk: cdce925: Remove redundant of_match_ptr() clk: pxa910: Move number of clocks to driver source clk: pxa1928: Move number of clocks to driver source clk: pxa168: Move number of clocks to driver source clk: mmp2: Move number of clocks to driver source ...
2023-08-30Merge branch 'clk-qcom' into clk-nextStephen Boyd34-1188/+4598
* clk-qcom: (87 commits) clk: qcom: Fix SM_GPUCC_8450 dependencies clk: qcom: smd-rpm: Set XO rate and CLK_IS_CRITICAL on PCNoC clk: qcom: smd-rpm: Add a way to define bus clocks with rate and flags clk: qcom: gcc-ipq5018: change some variable static clk: qcom: gcc-ipq4019: add missing networking resets dt-bindings: clock: qcom: ipq4019: add missing networking resets clk: qcom: gcc-msm8917: Enable GPLL0_SLEEP_CLK_SRC dt-bindings: clock: gcc-msm8917: Add definition for GPLL0_SLEEP_CLK_SRC clk: qcom: gcc-qdu1000: Update the RCGs ops clk: qcom: gcc-qdu1000: Update the SDCC clock RCG ops clk: qcom: gcc-qdu1000: Add support for GDSCs clk: qcom: gcc-qdu1000: Add gcc_ddrss_ecpri_gsi_clk support clk: qcom: gcc-qdu1000: Register gcc_gpll1_out_even clock clk: qcom: gcc-qdu1000: Fix clkref clocks handling clk: qcom: gcc-qdu1000: Fix gcc_pcie_0_pipe_clk_src clock handling dt-bindings: clock: Update GCC clocks for QDU1000 and QRU1000 SoCs clk: qcom: gcc-sm8450: Use floor ops for SDCC RCGs clk: qcom: ipq5332: drop the gcc_apss_axi_clk_src clock clk: qcom: ipq5332: drop the mem noc clocks clk: qcom: gcc-msm8998: Don't check halt bit on some branch clks ...
2023-08-30Merge branches 'clk-imx', 'clk-samsung', 'clk-annotate', 'clk-marvell' and ↵Stephen Boyd43-1278/+741
'clk-lmk' into clk-next - Add __counted_by to struct clk_hw_onecell_data and struct spmi_pmic_div_clk_cc - Remove non-OF mmp clk drivers - Move number of clks from DT headers to drivers * clk-imx: clk: imx: pll14xx: dynamically configure PLL for 393216000/361267200Hz clk: imx: pll14xx: align pdiv with reference manual clk: imx: composite-8m: fix clock pauses when set_rate would be a no-op clk: imx25: make __mx25_clocks_init return void clk: imx25: print silicon revision during init dt-bindings: clocks: imx8mp: make sai4 a dummy clock clk: imx8mp: fix sai4 clock clk: imx: imx8ulp: update SPLL2 type clk: imx: pllv4: Fix SPLL2 MULT range clk: imx: imx8: add audio clock mux driver dt-bindings: clock: fsl,imx8-acm: Add audio clock mux support clk: imx: clk-imx8qxp-lpcg: Convert to devm_platform_ioremap_resource() clk: imx: clk-gpr-mux: Simplify .determine_rate() clk: imx: Add 519.75MHz frequency support for imx9 pll clk: imx93: Add PDM IPG clk dt-bindings: clock: imx93: Add PDM IPG clk * clk-samsung: dt-bindings: clock: samsung: remove define with number of clocks clk: samsung: exynoautov9: do not define number of clocks in bindings clk: samsung: exynos850: do not define number of clocks in bindings clk: samsung: exynos7885: do not define number of clocks in bindings clk: samsung: exynos5433: do not define number of clocks in bindings clk: samsung: exynos5420: do not define number of clocks in bindings clk: samsung: exynos5410: do not define number of clocks in bindings clk: samsung: exynos5260: do not define number of clocks in bindings clk: samsung: exynos5250: do not define number of clocks in bindings clk: samsung: exynos4: do not define number of clocks in bindings clk: samsung: exynos3250: do not define number of clocks in bindings * clk-annotate: clk: qcom: clk-spmi-pmic-div: Annotate struct spmi_pmic_div_clk_cc with __counted_by clk: Annotate struct clk_hw_onecell_data with __counted_by * clk-marvell: clk: pxa910: Move number of clocks to driver source clk: pxa1928: Move number of clocks to driver source clk: pxa168: Move number of clocks to driver source clk: mmp2: Move number of clocks to driver source clk: mmp: Remove old non-OF clock drivers * clk-lmk: clk: lmk04832: Support using PLL1_LD as SPI readback pin clk: lmk04832: Don't disable vco clock on probe fail clk: lmk04832: Set missing parent_names for output clocks
2023-08-30Merge branches 'clk-versa', 'clk-strdup', 'clk-amlogic', 'clk-allwinner' and ↵Stephen Boyd49-3353/+4153
'clk-rockchip' into clk-next - Add Versa3 clk generator to support 48KHz playback/record with audio codec on RZ/G2L SMARC EVK - Introduce kstrdup_and_replace() and use it * clk-versa: clk: vc7: Use i2c_get_match_data() instead of device_get_match_data() clk: vc5: Use i2c_get_match_data() instead of device_get_match_data() clk: versaclock3: Switch to use i2c_driver's probe callback clk: Add support for versa3 clock driver dt-bindings: clock: Add Renesas versa3 clock generator bindings * clk-strdup: clk: ti: Replace kstrdup() + strreplace() with kstrdup_and_replace() clk: tegra: Replace kstrdup() + strreplace() with kstrdup_and_replace() driver core: Replace kstrdup() + strreplace() with kstrdup_and_replace() lib/string_helpers: Add kstrdup_and_replace() helper * clk-amlogic: (22 commits) dt-bindings: soc: amlogic: document System Control registers dt-bindings: clock: amlogic: convert amlogic,gxbb-aoclkc.txt to dt-schema dt-bindings: clock: amlogic: convert amlogic,gxbb-clkc.txt to dt-schema clk: meson: axg-audio: move bindings include to main driver clk: meson: meson8b: move bindings include to main driver clk: meson: a1: move bindings include to main driver clk: meson: eeclk: move bindings include to main driver clk: meson: aoclk: move bindings include to main driver dt-bindings: clk: axg-audio-clkc: expose all clock ids dt-bindings: clk: amlogic,a1-pll-clkc: expose all clock ids dt-bindings: clk: amlogic,a1-peripherals-clkc: expose all clock ids dt-bindings: clk: meson8b-clkc: expose all clock ids dt-bindings: clk: g12a-aoclkc: expose all clock ids dt-bindings: clk: g12a-clks: expose all clock ids dt-bindings: clk: axg-clkc: expose all clock ids dt-bindings: clk: gxbb-clkc: expose all clock ids clk: meson: migrate axg-audio out of hw_onecell_data to drop NR_CLKS clk: meson: migrate meson8b out of hw_onecell_data to drop NR_CLKS clk: meson: migrate a1 clock drivers out of hw_onecell_data to drop NR_CLKS clk: meson: migrate meson-aoclk out of hw_onecell_data to drop NR_CLKS ... * clk-allwinner: clk: sunxi-ng: nkm: Prefer current parent rate clk: sunxi-ng: a64: select closest rate for pll-video0 clk: sunxi-ng: div: Support finding closest rate clk: sunxi-ng: mux: Support finding closest rate clk: sunxi-ng: nkm: Support finding closest rate clk: sunxi-ng: nm: Support finding closest rate clk: sunxi-ng: Add helper function to find closest rate clk: sunxi-ng: Add feature to find closest rate clk: sunxi-ng: a64: allow pll-mipi to set parent's rate clk: sunxi-ng: nkm: consider alternative parent rates when determining rate clk: sunxi-ng: nkm: Use correct parameter name for parent HW clk: sunxi-ng: Modify mismatched function name clk: sunxi: sun9i-mmc: Use devm_platform_get_and_ioremap_resource() * clk-rockchip: clk: rockchip: rv1126: Add PD_VO clock tree clk: rockchip: rk3568: Fix PLL rate setting for 78.75MHz clk: rockchip: rk3568: Add PLL rate for 101MHz
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