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2020-09-22clk: socfpga: agilex: Remove unused variable 'cntr_mux'YueHaibing1-13/+0
drivers/clk/socfpga/clk-agilex.c:24:37: warning: ‘cntr_mux’ defined but not used [-Wunused-const-variable=] static const struct clk_parent_data cntr_mux[] = { ^~~~~~~~ There is no caller in tree, so can remove it. Signed-off-by: YueHaibing <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Stephen Boyd <[email protected]>
2020-09-22clk: si5341: drop unused 'err' variableKrzysztof Kozlowski1-3/+1
'err' is assigned but never read: /drivers/clk/clk-si5341.c: In function ‘si5341_output_get_parent’: drivers/clk/clk-si5341.c:886:6: warning: variable ‘err’ set but not used [-Wunused-but-set-variable] Signed-off-by: Krzysztof Kozlowski <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Stephen Boyd <[email protected]>
2020-09-22clk: mmp: pxa1928: drop unused 'clk' variableKrzysztof Kozlowski1-2/+1
'clk' is assigned but never read: drivers/clk/mmp/clk-of-pxa1928.c: In function ‘pxa1928_pll_init’: drivers/clk/mmp/clk-of-pxa1928.c:71:14: warning: variable ‘clk’ set but not used [-Wunused-but-set-variable] Signed-off-by: Krzysztof Kozlowski <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Stephen Boyd <[email protected]>
2020-09-22clk: at91: drop unused at91sam9g45_pcr_layoutKrzysztof Kozlowski1-7/+0
The at91sam9g45_pcr_layout is not used so drop it to fix build warning: drivers/clk/at91/at91sam9g45.c:49:36: warning: 'at91sam9g45_pcr_layout' defined but not used [-Wunused-const-variable=] Signed-off-by: Krzysztof Kozlowski <[email protected]> Acked-by: Alexandre Belloni <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Stephen Boyd <[email protected]>
2020-09-22clk: davinci: add missing kerneldocKrzysztof Kozlowski1-0/+1
Add missing kerneldoc to fix compile warning: drivers/clk/davinci/da8xx-cfgchip.c:578: warning: Function parameter or member 'dev' not described in 'da8xx_cfgchip_register_usb1_clk48' Signed-off-by: Krzysztof Kozlowski <[email protected]> Reviewed-by: David Lechner <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Stephen Boyd <[email protected]>
2020-09-22clk: fixed: add missing kerneldocKrzysztof Kozlowski2-0/+2
Add missing kerneldoc to fix compile warnings like: drivers/clk/clk-fixed-factor.c:211: warning: Function parameter or member 'node' not described in 'of_fixed_factor_clk_setup' Signed-off-by: Krzysztof Kozlowski <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Stephen Boyd <[email protected]>
2020-09-22clk: s2mps11: initialize driver via module_platform_driverKrzysztof Kozlowski1-12/+1
The driver was using subsys_initcall() because in old times deferred probe was not supported everywhere and specific ordering was needed. Since probe deferral works fine and specific ordering is discouraged (hides dependencies between drivers and couples their boot order), the driver can be converted to regular module_platform_driver. Signed-off-by: Krzysztof Kozlowski <[email protected]> Link: https://lore.kernel.org/r/[email protected] Tested-by: Marek Szyprowski <[email protected]> Signed-off-by: Stephen Boyd <[email protected]>
2020-09-22clk: bcm: rpi: Add register to control pixel bvb clkHoegeun Kwon1-0/+1
To use QHD or higher, we need to modify the pixel_bvb_clk value. So add register to control this clock. Signed-off-by: Hoegeun Kwon <[email protected]> Link: https://lore.kernel.org/r/[email protected] Reviewed-by: Maxime Ripard <[email protected]> Acked-by: Nicolas Saenz Julienne <[email protected]> Tested-by: Nicolas Saenz Julienne <[email protected]> Signed-off-by: Stephen Boyd <[email protected]>
2020-09-22clk: samsung: exynos4: mark 'chipid' clock as CLK_IGNORE_UNUSEDMarek Szyprowski1-2/+2
The ChipID IO region has it's own clock, which is being disabled while scanning for unused clocks. It turned out that some CPU hotplug, CPU idle or even SOC firmware code depends on the reads from that area. Fix the mysterious hang caused by entering deep CPU idle state by ignoring the 'chipid' clock during unused clocks scan, as there are no direct clients for it which will keep it enabled. Fixes: e062b571777f ("clk: exynos4: register clocks using common clock framework") Signed-off-by: Marek Szyprowski <[email protected]> Link: https://lore.kernel.org/r/[email protected] Reviewed-by: Krzysztof Kozlowski <[email protected]> Acked-by: Sylwester Nawrocki <[email protected]> Signed-off-by: Stephen Boyd <[email protected]>
2020-09-22Merge tag 'for-5.10-clk' of ↵Stephen Boyd2-5/+4
git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux into clk-fixes Pull Tegra clk driver fixes from Thierry Reding: This is a set of small fixes for the Tegra clock driver. * tag 'for-5.10-clk' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux: clk: tegra: Fix missing prototype for tegra210_clk_register_emc() clk: tegra: Always program PLL_E when enabled clk: tegra: Capitalization fixes
2020-09-22clk: qcom: gcc-sdm660: Fix wrong parent_mapKonrad Dybcio1-1/+1
This was likely overlooked while porting the driver upstream. Reported-by: Pavel Dubrova <[email protected]> Signed-off-by: Konrad Dybcio <[email protected]> Link: https://lore.kernel.org/r/[email protected] Fixes: f2a76a2955c0 ("clk: qcom: Add Global Clock controller (GCC) driver for SDM660") Signed-off-by: Stephen Boyd <[email protected]>
2020-09-22clk: qcom: dispcc: Update DP clk ops for phy designStephen Boyd2-9/+13
The clk_rcg2_dp_determine_rate() function is used for the DP pixel clk. This function should return the rate that can be achieved by the pixel clk in 'struct clk_rate_request::rate' and match the logic similar to what is seen in clk_rcg2_dp_set_rate(). But that isn't the case. Instead the code merely bubbles the rate request up to the parent of the pixel clk and doesn't try to do a rational approximation of the rate that would be achieved by picking some m/n value for the RCG. Let's change this logic so that we can assume the parent clk frequency is fixed (it is because it's the VCO of the DP PLL that is configured based on the link rate) and so that we can calculate what the m/n value will be and adjust the req->rate appropriately. Cc: Jeykumar Sankaran <[email protected]> Cc: Chandan Uddaraju <[email protected]> Cc: Vara Reddy <[email protected]> Cc: Tanmay Shah <[email protected]> Cc: Bjorn Andersson <[email protected]> Cc: Manu Gautam <[email protected]> Cc: Sandeep Maheswaram <[email protected]> Cc: Douglas Anderson <[email protected]> Cc: Sean Paul <[email protected]> Cc: Stephen Boyd <[email protected]> Cc: Jonathan Marek <[email protected]> Cc: Dmitry Baryshkov <[email protected]> Cc: Rob Clark <[email protected]> Signed-off-by: Stephen Boyd <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Stephen Boyd <[email protected]>
2020-09-22clk: qcom: gcc-msm8939: remove defined but not used variablesJason Yan1-12/+0
This addresses the following gcc warning with "make W=1": drivers/clk/qcom/gcc-msm8939.c:610:32: warning: ‘gcc_xo_gpll6_gpll0a_map’ defined but not used [-Wunused-const-variable=] static const struct parent_map gcc_xo_gpll6_gpll0a_map[] = { ^~~~~~~~~~~~~~~~~~~~~~~ drivers/clk/qcom/gcc-msm8939.c:598:32: warning: ‘gcc_xo_gpll6_gpll0_map’ defined but not used [-Wunused-const-variable=] static const struct parent_map gcc_xo_gpll6_gpll0_map[] = { ^~~~~~~~~~~~~~~~~~~~~~ Reported-by: Hulk Robot <[email protected]> Signed-off-by: Jason Yan <[email protected]> Link: https://lore.kernel.org/r/[email protected] Reviewed-by: Bjorn Andersson <[email protected]> Signed-off-by: Stephen Boyd <[email protected]>
2020-09-22clk: qcom: ipq8074: make pcie0_rchng_clk_src staticJason Yan1-1/+1
This addresses the following sparse warning: drivers/clk/qcom/gcc-ipq8074.c:4325:17: warning: symbol 'pcie0_rchng_clk_src' was not declared. Should it be static? Reported-by: Hulk Robot <[email protected]> Signed-off-by: Jason Yan <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Stephen Boyd <[email protected]>
2020-09-22clk: rockchip: rk3399: Support module buildElaine Zhang2-1/+57
support CLK_OF_DECLARE and builtin_platform_driver_probe double clk init method. add module author, description and license to support building Soc Rk3399 clock driver as module. Signed-off-by: Elaine Zhang <[email protected]> Reviewed-by: Kever Yang <[email protected]> Reviewed-by: Stephen Boyd <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Heiko Stuebner <[email protected]>
2020-09-22clk: rockchip: fix the clk config to support module buildElaine Zhang3-20/+101
use CONFIG_COMMON_CLK_ROCKCHIP for Rk common clk drivers. use CONFIG_CLK_RKXX for Rk soc clk driver. Mark CONFIG_CLK_RK3399 to "tristate", to support building Rk3399 SoC clock driver as module. Signed-off-by: Elaine Zhang <[email protected]> Reviewed-by: Kever Yang <[email protected]> Reviewed-by: Stephen Boyd <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Heiko Stuebner <[email protected]>
2020-09-22clk: rockchip: Export some clock common APIs for module driversElaine Zhang1-22/+30
This is used by the Rockchip clk driver, export it to allow that driver to be compiled as a module. Signed-off-by: Elaine Zhang <[email protected]> Reviewed-by: Kever Yang <[email protected]> Reviewed-by: Stephen Boyd <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Heiko Stuebner <[email protected]>
2020-09-22clk: rockchip: Export rockchip_register_softrst()Elaine Zhang1-3/+4
This is used by the Rockchip clk driver, export it to allow that driver to be compiled as a module.. Signed-off-by: Elaine Zhang <[email protected]> Reviewed-by: Kever Yang <[email protected]> Reviewed-by: Stephen Boyd <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Heiko Stuebner <[email protected]>
2020-09-22clk: rockchip: Export rockchip_clk_register_ddrclk()Elaine Zhang1-0/+1
This is used by the Rockchip clk driver, export it to allow that driver to be compiled as a module.. Signed-off-by: Elaine Zhang <[email protected]> Reviewed-by: Kever Yang <[email protected]> Reviewed-by: Stephen Boyd <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Heiko Stuebner <[email protected]>
2020-09-22clk: rockchip: Use clk_hw_register_composite instead of ↵Elaine Zhang2-39/+40
clk_register_composite calls clk_hw_register_composite it's already exported. Preparation for compilation of rK common clock drivers into modules. Reported-by: kernel test robot <[email protected]> Signed-off-by: Elaine Zhang <[email protected]> Reviewed-by: Kever Yang <[email protected]> Reviewed-by: Heiko Stuebner <[email protected]> Reviewed-by: Stephen Boyd <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Heiko Stuebner <[email protected]>
2020-09-22clk: rockchip: rk3308: drop unused mux_timer_src_pKrzysztof Kozlowski1-1/+0
The parent names 'mux_timer_src_p' is not used: In file included from drivers/clk/rockchip/clk-rk3308.c:13:0: drivers/clk/rockchip/clk-rk3308.c:136:7: warning: ‘mux_timer_src_p’ defined but not used [-Wunused-const-variable=] Signed-off-by: Krzysztof Kozlowski <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Heiko Stuebner <[email protected]>
2020-09-22clk: imx: imx21: Remove clock driverFabio Estevam3-176/+0
As i.MX21 support has been removed, get rid of its clock driver too. Signed-off-by: Fabio Estevam <[email protected]> Acked-by: Arnd Bergmann <[email protected]> Signed-off-by: Shawn Guo <[email protected]>
2020-09-22clk: imx: imx35: Remove mx35_clocks_init()Fabio Estevam1-68/+0
mx35_clocks_init() has been used to register clocks on i.MX35 non-devicetree platforms. Now that i.MX is a devicetree-only platform, it is safe to remove mx35_clocks_init() as there are no more users. Signed-off-by: Fabio Estevam <[email protected]> Acked-by: Arnd Bergmann <[email protected]> Signed-off-by: Shawn Guo <[email protected]>
2020-09-22clk: imx: imx31: Remove mx31_clocks_init()Fabio Estevam1-71/+0
mx31_clocks_init() has been used to register clocks on i.MX31 non-devicetree platforms. Now that i.MX is a devicetree-only platform, it is safe to remove mx31_clocks_init() as there are no more users. Signed-off-by: Fabio Estevam <[email protected]> Acked-by: Arnd Bergmann <[email protected]> Signed-off-by: Shawn Guo <[email protected]>
2020-09-22clk: imx: imx27: Remove mx27_clocks_init()Fabio Estevam1-73/+0
mx27_clocks_init() has been used to register clocks on i.MX27 non-devicetree platforms. Now that i.MX is a devicetree-only platform, it is safe to remove mx27_clocks_init() as there are no more users. Signed-off-by: Fabio Estevam <[email protected]> Acked-by: Arnd Bergmann <[email protected]> Signed-off-by: Shawn Guo <[email protected]>
2020-09-21clk: tegra: Fix missing prototype for tegra210_clk_register_emc()Thierry Reding1-0/+2
Include the Tegra driver's clk.h to pull in the prototype definition for this function so that compilers don't warn about it being missing. Fixes: 0ac65fc946d3 ("clk: tegra: Implement Tegra210 EMC clock") Reported-by: kernel test robot <[email protected]> Signed-off-by: Thierry Reding <[email protected]>
2020-09-21clk: tegra: Always program PLL_E when enabledThierry Reding1-3/+0
Commit bff1cef5f23a ("clk: tegra: Don't enable already enabled PLLs") added checks to avoid enabling PLLs that have already been enabled by the bootloader. However, the PLL_E configuration inherited from the bootloader isn't necessarily the one that is needed for the kernel. This can cause SATA to fail like this: [ 5.310270] phy phy-sata.6: phy poweron failed --> -110 [ 5.315604] tegra-ahci 70027000.sata: failed to power on AHCI controller: -110 [ 5.323022] tegra-ahci: probe of 70027000.sata failed with error -110 Fix this by always programming the PLL_E. This ensures that any mis- configuration by the bootloader will be overwritten by the kernel. Fixes: bff1cef5f23a ("clk: tegra: Don't enable already enabled PLLs") Reported-by: LABBE Corentin <[email protected]> Tested-by: Corentin Labbe <[email protected]> Reviewed-by: Dmitry Osipenko <[email protected]> Signed-off-by: Thierry Reding <[email protected]>
2020-09-21clk: tegra: Capitalization fixesThierry Reding1-2/+2
HW, XUSB and PLL are abbreviations and should be all-uppercase. Signed-off-by: Thierry Reding <[email protected]>
2020-09-17clk: renesas: rcar-gen3: Update description for RZ/G2Lad Prabhakar1-1/+1
The rcar-gen3-cpg driver is also used on Renesas RZ/G2 SoC's, update the description for the CLK_RCAR_GEN3_CPG config symbol to reflect this. Signed-off-by: Lad Prabhakar <[email protected]> Reviewed-by: Chris Paterson <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Geert Uytterhoeven <[email protected]>
2020-09-17clk: renesas: cpg-mssr: Add support for R-Car V3UYoshihiro Shimoda5-1/+316
Initial support for R-Car V3U (r8a779a0), including core, module clocks, resets, and register access, because register specification differs from R-Car Gen2/3. Inspired by patches in the BSP by LUU HOAI. Signed-off-by: Yoshihiro Shimoda <[email protected]> Link: https://lore.kernel.org/r/1599810232-29035-4-git-send-email-yoshihiro.shimoda.uh@renesas.com Signed-off-by: Geert Uytterhoeven <[email protected]>
2020-09-17clk: renesas: cpg-mssr: Add register pointers into struct cpg_mssr_privYoshihiro Shimoda1-35/+47
To support other register layouts in the future, add register pointers of {control,status,reset,reset_clear}_regs into struct cpg_mssr_priv. After that, we can remove unused macros like MSTPSR(). No behavioral changes. Signed-off-by: Yoshihiro Shimoda <[email protected]> Link: https://lore.kernel.org/r/1599810232-29035-3-git-send-email-yoshihiro.shimoda.uh@renesas.com Signed-off-by: Geert Uytterhoeven <[email protected]>
2020-09-17clk: renesas: cpg-mssr: Use enum clk_reg_layout instead of a boolean flagYoshihiro Shimoda3-19/+22
Geert suggested defining multiple register layout variants using an enum [1] to support further devices like R-Car V3U. So, use enum clk_reg_layout instead of a boolean .stbyctrl flag. No behavioral change. [1] https://lore.kernel.org/linux-renesas-soc/CAMuHMdVAgN69p9FFnQdO4iHk2CHkeNaVui2Q-FOY6_BFVjQ-Nw@mail.gmail.com/ Signed-off-by: Yoshihiro Shimoda <[email protected]> Link: https://lore.kernel.org/r/1599810232-29035-2-git-send-email-yoshihiro.shimoda.uh@renesas.com Signed-off-by: Geert Uytterhoeven <[email protected]>
2020-09-17clk: samsung: Use cached clk_hws instead of __clk_lookup() callsSylwester Nawrocki7-36/+42
For the CPU clock registration two parent clocks are required, these are now being passed as struct clk_hw pointers, rather than by the global scope names. That allows us to avoid __clk_lookup() calls and simplifies a bit the CPU clock registration function. While at it drop unneeded extern keyword in the function declaration. Reviewed-by: Krzysztof Kozlowski <[email protected]> Acked-by: Chanwoo Choi <[email protected]> Link: https://lore.kernel.org/r/[email protected] Reported-by: Marek Szyprowski <[email protected]> Signed-off-by: Sylwester Nawrocki <[email protected]>
2020-09-17clk: samsung: exynos5420/5250: Add IDs to the CPU parent clk definitionsSylwester Nawrocki2-7/+8
Use non-zero clock IDs in definitions of the CPU parent clocks for exynos5420, exynos5250 SoCs. This will allow us to reference the parent clocks directly in the driver by cached struct clk_hw pointers, rather than doing clk lookup by name. Reviewed-by: Krzysztof Kozlowski <[email protected]> Acked-by: Chanwoo Choi <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Sylwester Nawrocki <[email protected]>
2020-09-17clk: samsung: exynos5420: Avoid __clk_lookup() calls when enabling clocksSylwester Nawrocki1-4/+6
This patch adds a clk ID to the mout_sw_aclk_g3d clk definition so related clk pointer gets cached in the driver's private data and can be used later instead of a __clk_lookup() call. With that we have all clocks used in the clk_prepare_enable() calls in the clk provider init callback cached in clk_data.hws[] and we can reference the clk pointers directly rather than using __clk_lookup() with global names. Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Sylwester Nawrocki <[email protected]>
2020-09-15Merge tag 'v5.9-clk-samsung-fixes' of ↵Stephen Boyd1-0/+5
https://git.kernel.org/pub/scm/linux/kernel/git/snawrocki/clk into clk-fixes Pull a Samsung clk driver fix from Sylwester Nawrocki: - fix for a regression in v5.9-rc1 on Odroid XU3/XU4, i.e. booting failure due to the DRAM controller root clock being disabled * tag 'v5.9-clk-samsung-fixes' of https://git.kernel.org/pub/scm/linux/kernel/git/snawrocki/clk: clk: samsung: Keep top BPLL mux on Exynos542x enabled
2020-09-15clk: samsung: Keep top BPLL mux on Exynos542x enabledMarek Szyprowski1-0/+5
BPLL clock must not be disabled because it is needed for proper DRAM operation. This is normally handled by respective memory devfreq driver, but when that driver is not yet probed or its probe has been deferred the clock might get disabled what causes board hang. Fix this by calling clk_prepare_enable() directly from the clock provider driver. Cc: [email protected] Signed-off-by: Marek Szyprowski <[email protected]> Reviewed-by: Lukasz Luba <[email protected]> Tested-by: Lukasz Luba <[email protected]> Acked-by: Krzysztof Kozlowski <[email protected]> Link: https://lore.kernel.org/r/[email protected] Fixes: 6e7674c3c6df ("memory: Add DMC driver for Exynos5422") Signed-off-by: Sylwester Nawrocki <[email protected]>
2020-09-13clk: imx: gate2: Fix a few typosJonathan Neuschäfer1-1/+1
A few words were misspelled in this comment. Signed-off-by: Jonathan Neuschäfer <[email protected]> Reviewed-by: Stephen Boyd <[email protected]> Signed-off-by: Shawn Guo <[email protected]>
2020-09-10clk: qcom: lpass: Correct goto target in lpass_core_sc7180_probe()Jing Xiangfeng1-3/+4
lpass_core_sc7180_probe() misses to call pm_clk_destroy() and pm_runtime_disable() in error paths. Correct goto target to fix it. This issue is found by code inspection. Signed-off-by: Jing Xiangfeng <[email protected]> Link: https://lore.kernel.org/r/[email protected] Fixes: edab812d802d ("clk: qcom: lpass: Add support for LPASS clock controller for SC7180") Signed-off-by: Stephen Boyd <[email protected]>
2020-09-10clk: meson: make shipped controller configurableJerome Brunet1-9/+17
Add the necessary bits so unnecessary amlogic clock controllers can be compiled out. This allows to save a few kB when necessary. Signed-off-by: Jerome Brunet <[email protected]> Reviewed-by: Stephen Boyd <[email protected]> Link: https://lore.kernel.org/r/[email protected]
2020-09-10clk: versatile: Add of_node_put() before return statementSumera Priyadarsini1-1/+3
Every iteration of for_each_available_child_of_node() decrements the reference count of the previous node, however when control is transferred from the middle of the loop, as in the case of a return or break or goto, there is no decrement thus ultimately resulting in a memory leak. Fix a potential memory leak in clk-impd1.c by inserting of_node_put() before a return statement. Issue found with Coccinelle. Signed-off-by: Sumera Priyadarsini <[email protected]> Link: https://lore.kernel.org/r/20200829175704.GA10998@Kaladin Reviewed-by: Linus Walleij <[email protected]> Signed-off-by: Stephen Boyd <[email protected]>
2020-09-10clk: bcm: dvp: Select the reset frameworkMaxime Ripard1-0/+1
The DVP driver depends both on the RESET_SIMPLE driver but also on the reset framework itself. Let's make sure we have it enabled. Fixes: 1bc95972715a ("clk: bcm: Add BCM2711 DVP driver") Signed-off-by: Maxime Ripard <[email protected]> Link: https://lore.kernel.org/r/[email protected] Acked-by: Nicolas Saenz Julienne <[email protected]> Signed-off-by: Stephen Boyd <[email protected]>
2020-09-07clk: imx: Fix and update kerneldocKrzysztof Kozlowski3-3/+6
Fix and add missing kerneldoc to fix compile warnings like: drivers/clk/imx/clk-pfd.c:27: warning: Function parameter or member 'hw' not described in 'clk_pfd' drivers/clk/imx/clk-pllv3.c:53: warning: Function parameter or member 'ref_clock' not described in 'clk_pllv3' Signed-off-by: Krzysztof Kozlowski <[email protected]> Signed-off-by: Shawn Guo <[email protected]>
2020-09-07clk: imx: fix i.MX7D peripheral clk mux flagsPeng Fan1-65/+66
According to RM, Page 574, Chapter 5.2.6.4.3 Peripheral clock slice, "IP clock slices must be stopped to change the clock source.". So we must have CLK_SET_PARENT_GATE flag to avoid glitch. Signed-off-by: Peng Fan <[email protected]> Signed-off-by: Shawn Guo <[email protected]>
2020-09-07clk: imx: fix composite peripheral flagsPeng Fan1-0/+1
According to RM, for peripheral clock slice, "IP clock slices must be stopped to change the clock source.". So we must have CLK_SET_PARENT_GATE flag to avoid glitch. Signed-off-by: Peng Fan <[email protected]> Signed-off-by: Shawn Guo <[email protected]>
2020-09-04clk: renesas: rcar-gen2: Rename vsp1-(sy|rt) clocks to vsp(s|r)Lad Prabhakar7-8/+8
VSP1 instances VSPS (which stands for "VSP Standard") and VSPR (which stands for "VSP for Resizing") were wrongly named as "vsp1-sy" and "vsp1-rt". The clock section in the SoC datasheets misunderstood the abbreviations as meaning VSP System and VSP Realtime, and named the corresponding clocks VSP1(SY) and VSP1(RT). This mistake has been carried over to the kernel code. This patch fixes this by renaming the clock names to "vsps" and "vspr". Inspired from commit 79ea9934b8df ("ARM: shmobile: r8a7790: Rename VSP1_(SY|RT) clocks to VSP1_(S|R)") Signed-off-by: Lad Prabhakar <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Geert Uytterhoeven <[email protected]>
2020-09-04clk: renesas: r8a7742: Add clk entry for VSPRLad Prabhakar1-1/+2
Add clock entry 130 for VSPR (VSP for Resizing) module, so that this module can be used on R8A7742 (RZ/G1H) SoC. Alongside rename clock entry "vsp1-sy" to "vsps" (VSP Standard), so that VSP1 clock names are in sync. Note: The entry for VSPR clock was accidentally dropped from RZ/G manual when all the information related to RT were removed. Signed-off-by: Lad Prabhakar <[email protected]> Reviewed-by: Biju Das <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Geert Uytterhoeven <[email protected]>
2020-08-31clk: imx: Correct the memrepair clock on imx8mpJacky Bai1-10/+4
The root clock slice at offset 0xbf80 should be memrepair clock, so correct it. And this clock should be always on to make sure the memory repair function can works well. Signed-off-by: Jacky Bai <[email protected]> Signed-off-by: Shawn Guo <[email protected]>
2020-08-31clk: imx: Correct the root clk of media ldb on imx8mpJacky Bai1-5/+5
The root clock slice at 0xbf00 is media_ldb clock, not csi_phy2_ref, so correct it. Signed-off-by: Jacky Bai <[email protected]> Signed-off-by: Shawn Guo <[email protected]>
2020-08-29clk: meson: g12a: mark fclk_div2 as criticalStefan Agner1-0/+11
On Amlogic Meson G12b platform, similar to fclk_div3, the fclk_div2 seems to be necessary for the system to operate correctly as well. Typically, the clock also gets chosen by the eMMC peripheral. This probably masked the problem so far. However, when booting from a SD card the clock seems to get disabled which leads to a system freeze. Let's mark this clock as critical, fixing boot from SD card on G12b platforms. Fixes: 085a4ea93d54 ("clk: meson: g12a: add peripheral clock controller") Signed-off-by: Stefan Agner <[email protected]> Signed-off-by: Jerome Brunet <[email protected]> Tested-by: Anand Moon <[email protected]> Cc: Marek Szyprowski <[email protected]> Link: https://lore.kernel.org/r/577e0129e8ee93972d92f13187ff4e4286182f67.1598629915.git.stefan@agner.ch
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