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2020-05-12clk: tegra20: Use custom CCLK implementationDmitry Osipenko1-2/+5
We're going to use the generic cpufreq-dt driver on Tegra20 and thus CCLK intermediate re-parenting will be performed by the clock driver. There is now special CCLK implementation that supports all CCLK quirks, this patch makes Tegra20 SoCs to use that implementation. Acked-by: Peter De Schrijver <[email protected]> Tested-by: Peter Geis <[email protected]> Tested-by: Marcel Ziswiler <[email protected]> Tested-by: Jasper Korten <[email protected]> Tested-by: David Heidelberg <[email protected]> Tested-by: Nicolas Chauvet <[email protected]> Signed-off-by: Dmitry Osipenko <[email protected]> Signed-off-by: Thierry Reding <[email protected]>
2020-05-12clk: tegra: cclk: Add helpers for handling PLLX rate changesDmitry Osipenko2-0/+36
CCLK should be re-parented away from PLLX if PLLX's rate is changing. The PLLP parent is a common safe CPU parent for all Tegra SoCs, thus CCLK will be re-parented to PLLP before PLLX rate-change begins and then switched back to PLLX after the rate-change completion. This patch adds helper functions which perform CCLK re-parenting, these helpers will be utilized by further patches. Acked-by: Peter De Schrijver <[email protected]> Tested-by: Peter Geis <[email protected]> Tested-by: Marcel Ziswiler <[email protected]> Tested-by: Jasper Korten <[email protected]> Tested-by: David Heidelberg <[email protected]> Tested-by: Nicolas Chauvet <[email protected]> Signed-off-by: Dmitry Osipenko <[email protected]> Signed-off-by: Thierry Reding <[email protected]>
2020-05-12clk: tegra: pll: Add pre/post rate-change hooksDmitry Osipenko2-1/+17
There is a need to temporarily re-parent CCLK away from PLLX if PLLX's rate is about to change. The newly introduced PLL pre/post rate-change hooks allow to handle such case. Acked-by: Peter De Schrijver <[email protected]> Tested-by: Peter Geis <[email protected]> Tested-by: Marcel Ziswiler <[email protected]> Tested-by: Jasper Korten <[email protected]> Tested-by: David Heidelberg <[email protected]> Tested-by: Nicolas Chauvet <[email protected]> Signed-off-by: Dmitry Osipenko <[email protected]> Signed-off-by: Thierry Reding <[email protected]>
2020-05-12clk: tegra: Add custom CCLK implementationDmitry Osipenko3-2/+188
CCLK stands for "CPU Clock", CPU core is running off CCLK. CCLK supports multiple parents, it has internal clock divider and a clock skipper. PLLX is the main CCLK parent that provides clock rates above 1GHz and it has special property such that the CCLK's internal divider is set into bypass mode when PLLX is selected as a parent for CCLK. This patch forks generic Super Clock into CCLK implementation which takes into account all CCLK specifics. The proper CCLK implementation is needed by the upcoming Tegra20 CPUFreq driver update that will allow to utilize the generic cpufreq-dt driver by moving intermediate clock selection into the clock driver. Note that technically this patch could be squashed into clk-super.c, but it is cleaner to have a separate source file. Also note that currently all CCLKLP bits are left in the clk-super.c and only CCLKG is supported by clk-tegra-super-cclk. It shouldn't be difficult to move the CCLKLP bits, but CCLKLP is not used by anything in kernel and thus better not to touch it for now. Acked-by: Peter De Schrijver <[email protected]> Tested-by: Peter Geis <[email protected]> Tested-by: Marcel Ziswiler <[email protected]> Tested-by: Jasper Korten <[email protected]> Tested-by: David Heidelberg <[email protected]> Tested-by: Nicolas Chauvet <[email protected]> Signed-off-by: Dmitry Osipenko <[email protected]> Signed-off-by: Thierry Reding <[email protected]>
2020-05-12clk: tegra: Remove the old emc_mux clock for Tegra210Joseph Lo1-19/+31
Remove the old emc_mux clock and don't use the common EMC clock definition. This will be replaced by a new clock defined in the EMC driver. Signed-off-by: Joseph Lo <[email protected]> Signed-off-by: Thierry Reding <[email protected]>
2020-05-12clk: tegra: Implement Tegra210 EMC clockJoseph Lo3-0/+373
The EMC clock needs to carefully coordinate with the EMC controller programming to make sure external memory can be properly clocked. Do so by hooking up the EMC clock with an EMC provider that will specify which rates are supported by the EMC and provide a callback to use for setting the clock rate at the EMC. Based on work by Peter De Schrijver <[email protected]>. Signed-off-by: Joseph Lo <[email protected]> Signed-off-by: Thierry Reding <[email protected]>
2020-05-12clk: tegra: Export functions for EMC clock scalingJoseph Lo1-0/+26
Export functions to allow accessing the CAR register required by EMC clock scaling. These functions will be used to access the CAR register as part of the scaling sequence. Signed-off-by: Joseph Lo <[email protected]> Signed-off-by: Thierry Reding <[email protected]>
2020-05-12clk: tegra: Add PLLP_UD and PLLMB_UD for Tegra210Joseph Lo1-0/+11
Introduce the low jitter path of PLLP and PLLMB which can be used as EMC clock source. Signed-off-by: Joseph Lo <[email protected]> Signed-off-by: Thierry Reding <[email protected]>
2020-05-12clk: tegra: Rename Tegra124 EMC clock source fileThierry Reding4-6/+2
This code is only used on Tegra124, so rename it accordingly to make it more consistent with other file names. While at it, also get rid of the TEGRA_CLK_EMC Kconfig symbol that's really just an alias for TEGRA124_EMC. Signed-off-by: Thierry Reding <[email protected]>
2020-05-07clk: qoriq: add cpufreq platform deviceMian Yousaf Kaukab1-3/+27
Add a platform device for qoirq-cpufreq driver for the compatible clockgen blocks. Reviewed-by: Yuantian Tang <[email protected]> Acked-by: Viresh Kumar <[email protected]> Signed-off-by: Mian Yousaf Kaukab <[email protected]> Acked-by: Stephen Boyd <[email protected]> Signed-off-by: Viresh Kumar <[email protected]>
2020-05-05clk: Allow the common clk framework to be selectableStephen Boyd1-4/+13
Enable build testing and configuration control of the common clk framework so that more code coverage and testing can be done on the common clk framework across various architectures. This also nicely removes the requirement that architectures must select the framework when they don't use it in architecture code. There's one snag with doing this, and that's making sure that randconfig builds don't select this option when some architecture or platform implements 'struct clk' outside of the common clk framework. Introduce a new config option 'HAVE_LEGACY_CLK' to indicate those platforms that haven't migrated to the common clk framework and therefore shouldn't be allowed to select this new config option. Also add a note that we hope one day to remove this config entirely. Based on a patch by Mark Brown <[email protected]>. Cc: Mark Brown <[email protected]> Cc: Geert Uytterhoeven <[email protected]> Cc: Mark Salter <[email protected]> Cc: Aurelien Jacquiot <[email protected]> Cc: Jiaxun Yang <[email protected]> Cc: Guan Xuetao <[email protected]> Cc: Russell King <[email protected]> Cc: Arnd Bergmann <[email protected]> Cc: Yoshinori Sato <[email protected]> Cc: Rich Felker <[email protected]> Cc: Thomas Bogendoerfer <[email protected]> Cc: <[email protected]> Cc: <[email protected]> Cc: <[email protected]> Cc: <[email protected]> Cc: <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Stephen Boyd <[email protected]> Link: https://lkml.kernel.org/r/[email protected] Reviewed-by: Mark Brown <[email protected]> Reviewed-by: Arnd Bergmann <[email protected]>
2020-05-05clk: clk-xgene: Fix a typo in KconfigChristophe JAILLET1-1/+1
s/Sypport/Support Signed-off-by: Christophe JAILLET <[email protected]> Link: https://lkml.kernel.org/r/[email protected] Signed-off-by: Stephen Boyd <[email protected]>
2020-05-05clk: Remove unused inline function clk_debug_reparentYueHaibing1-4/+0
There's no callers in-tree anymore. Signed-off-by: YueHaibing <[email protected]> Link: https://lkml.kernel.org/r/[email protected] Signed-off-by: Stephen Boyd <[email protected]>
2020-05-05clk: impd1: Look up clock-output-namesLinus Walleij1-0/+1
The IM-PD1 still need to pass the clock output names. Signed-off-by: Linus Walleij <[email protected]> Link: https://lkml.kernel.org/r/[email protected] Fixes: 84655b762a27 ("clk: versatile: Add device tree probing for IM-PD1 clocks") Signed-off-by: Stephen Boyd <[email protected]>
2020-05-05clk: Unlink clock if failed to prepare or enableMarc Zyngier1-0/+3
On failing to prepare or enable a clock, remove the core structure from the list it has been inserted as it is about to be freed. This otherwise leads to random crashes when subsequent clocks get registered, during which parsing of the clock tree becomes adventurous. Observed with QEMU's RPi-3 emulation. Fixes: 12ead77432f2 ("clk: Don't try to enable critical clocks if prepare failed") Signed-off-by: Marc Zyngier <[email protected]> Cc: Guenter Roeck <[email protected]> Cc: Stephen Boyd <[email protected]> Cc: Michael Turquette <[email protected]> Link: https://lkml.kernel.org/r/[email protected] Signed-off-by: Stephen Boyd <[email protected]>
2020-05-05clk: vexpress-osc: Use the devres clock API variantsRob Herring1-5/+5
In preparation to enable the vexpress-osc clock driver as a module, convert the driver to use the managed devres clock API variants. With this, a driver .remove() hook is not needed. Cc: Lorenzo Pieralisi <[email protected]> Cc: Linus Walleij <[email protected]> Cc: [email protected] Reviewed-by: Stephen Boyd <[email protected]> Reviewed-by: Sudeep Holla <[email protected]> Acked-by: Arnd Bergmann <[email protected]> Acked-by: Liviu Dudau <[email protected]> Signed-off-by: Rob Herring <[email protected]>
2020-05-05clk: versatile: Only enable SP810 on 32-bit by defaultRob Herring1-1/+1
While 64-bit Arm reference platforms have SP810 for clocks for SP804 timers, they are not needed since the arch timers are used instead. Cc: Catalin Marinas <[email protected]> Cc: Will Deacon <[email protected]> Cc: Lorenzo Pieralisi <[email protected]> Cc: Linus Walleij <[email protected]> Cc: [email protected] Reviewed-by: Sudeep Holla <[email protected]> Reviewed-by: Stephen Boyd <[email protected]> Acked-by: Arnd Bergmann <[email protected]> Acked-by: Liviu Dudau <[email protected]> Signed-off-by: Rob Herring <[email protected]>
2020-05-05clk: versatile: Rework kconfig structureRob Herring2-11/+13
CONFIG_COMMON_CLK_VERSATILE doesn't really do anything other than hiding Arm Ltd reference platform clock drivers. It is both selected by the platforms that need it and has a 'depends on' for those platforms. Let's drop the selects and convert CONFIG_COMMON_CLK_VERSATILE into a menuconfig entry. With this make CONFIG_ICST visible. Move the 'select REGMAP_MMIO' to the drivers that require it (SP810 did not). This also has the side effect of enabling CONFIG_ICST for COMPILE_TEST as it was not visible before. Cc: Catalin Marinas <[email protected]> Cc: Will Deacon <[email protected]> Cc: Liviu Dudau <[email protected]> Cc: Lorenzo Pieralisi <[email protected]> Cc: Linus Walleij <[email protected]> Reviewed-by: Sudeep Holla <[email protected]> Reviewed-by: Stephen Boyd <[email protected]> Signed-off-by: Rob Herring <[email protected]>
2020-05-02clk: meson: meson8b: Don't rely on u-boot to init all GP_PLL registersMartin Blumenstingl2-0/+13
Not all u-boot versions initialize the HHI_GP_PLL_CNTL[2-5] registers. In that case all HHI_GPLL_PLL_CNTL[1-5] registers are 0x0 and when booting Linux the PLL fails to lock. The initialization sequence from u-boot is: - put the PLL into reset - write 0x59C88000 to HHI_GP_PLL_CNTL2 - write 0xCA463823 to HHI_GP_PLL_CNTL3 - write 0x0286A027 to HHI_GP_PLL_CNTL4 - write 0x00003000 to HHI_GP_PLL_CNTL5 - set M, N, OD and the enable bit - take the PLL out of reset - check if it has locked - disable the PLL In Linux we already initialize M, N, OD, the enable and the reset bits. Also the HHI_GP_PLL_CNTL[2-5] registers with these magic values (the exact meaning is unknown) so the PLL can lock when the vendor u-boot did not initialize these registers yet. Fixes: b882964b376f21 ("clk: meson: meson8b: add support for the GP_PLL clock on Meson8m2") Signed-off-by: Martin Blumenstingl <[email protected]> Signed-off-by: Jerome Brunet <[email protected]> Link: https://lore.kernel.org/r/[email protected]
2020-04-30clk: renesas: rcar-gen2: Remove superfluous CLK_RENESAS_DIV6 selectsGeert Uytterhoeven1-3/+0
CLK_RENESAS_CPG_MSSR selects CLK_RENESAS_DIV6, and CLK_RCAR_GEN2_CPG selects CLK_RENESAS_CPG_MSSR, so there is no longer a need for the individual R-Car Gen2 clock driver options to select CLK_RENESAS_DIV6. Signed-off-by: Geert Uytterhoeven <[email protected]> Reviewed-by: Niklas Söderlund <[email protected]> Link: https://lore.kernel.org/r/[email protected]
2020-04-30clk: renesas: cpg-mssr: Add R8A7742 supportLad Prabhakar5-0/+288
Add RZ/G1H (R8A7742) Clock Pulse Generator / Module Standby and Software Reset support, using the CPG/MSSR driver core and the common R-Car Gen2 (and RZ/G) code. Signed-off-by: Lad Prabhakar <[email protected]> Reviewed-by: Marian-Cristian Rotariu <[email protected]> Link: https://lore.kernel.org/r/1587998460-7804-1-git-send-email-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven <[email protected]>
2020-04-29clk: meson: meson8b: Make the CCF use the glitch-free VPU muxMartin Blumenstingl1-3/+11
The "vpu_0" or "vpu_1" clock trees should not be updated while the clock is running. Enforce this by setting CLK_SET_RATE_GATE on the "vpu_0" and "vpu_1" gates. This makes the CCF switch to the "vpu_1" tree when "vpu_0" is currently active and vice versa, which is exactly what the vendor driver does when updating the frequency of the VPU clock. Signed-off-by: Martin Blumenstingl <[email protected]> Signed-off-by: Jerome Brunet <[email protected]> Link: https://lore.kernel.org/r/[email protected]
2020-04-29clk: meson: meson8b: Fix the vclk_div{1, 2, 4, 6, 12}_en gate bitsMartin Blumenstingl1-5/+5
The DIV{1,2,4,6,12}_EN bits are actually located in HHI_VID_CLK_CNTL register: - HHI_VID_CLK_CNTL[0] = DIV1_EN - HHI_VID_CLK_CNTL[1] = DIV2_EN - HHI_VID_CLK_CNTL[2] = DIV4_EN - HHI_VID_CLK_CNTL[3] = DIV6_EN - HHI_VID_CLK_CNTL[4] = DIV12_EN Update the bits accordingly so we will enable the bits in the correct register once we switch these clocks to be mutable. Fixes: 6cb57c678bb70e ("clk: meson: meson8b: add the read-only video clock trees") Signed-off-by: Martin Blumenstingl <[email protected]> Signed-off-by: Jerome Brunet <[email protected]> Link: https://lore.kernel.org/r/[email protected]
2020-04-29clk: meson: meson8b: Fix the polarity of the RESET_N linesMartin Blumenstingl1-23/+56
CLKC_RESET_VID_DIVIDER_CNTL_RESET_N_POST and CLKC_RESET_VID_DIVIDER_CNTL_RESET_N_PRE are active low. This means: - asserting them requires setting the register value to 0 - de-asserting them requires setting the register value to 1 Set the register value accordingly for these two reset lines by setting the inverted the register value compared to all other reset lines. Fixes: 189621726bc2f6 ("clk: meson: meson8b: register the built-in reset controller") Signed-off-by: Martin Blumenstingl <[email protected]> Signed-off-by: Jerome Brunet <[email protected]> Link: https://lore.kernel.org/r/[email protected]
2020-04-29clk: meson: meson8b: Fix the first parent of vid_pll_in_selMartin Blumenstingl1-1/+1
Use hdmi_pll_lvds_out as parent of the vid_pll_in_sel clock. It's not easy to see that the vendor kernel does the same, but it actually does. meson_clk_pll_ops in mainline still cannot fully recalculate all rates from the HDMI PLL registers because some register bits (at the time of writing it's unknown which bits are used for this) double the HDMI PLL output rate (compared to simply considering M, N and FRAC) for some (but not all) PLL settings. Update the vid_pll_in_sel parent so our clock calculation works for simple clock settings like the CVBS output (where no rate doubling is going on). The PLL ops need to be fixed later on for more complex clock settings (all HDMI rates). Fixes: 6cb57c678bb70 ("clk: meson: meson8b: add the read-only video clock trees") Suggested-by: Neil Armstrong <[email protected]> Signed-off-by: Martin Blumenstingl <[email protected]> Signed-off-by: Jerome Brunet <[email protected]> Link: https://lore.kernel.org/r/[email protected]
2020-04-29clk: imx: Add helpers for passing the device as argumentAbel Vesa1-0/+29
All the imx clocks that need to be registered by the audiomix need to pass on the device so that the runtime PM support could work properly. Signed-off-by: Abel Vesa <[email protected]> Reviewed-by: Stephen Boyd <[email protected]> Reviewed-by: Peng Fan <[email protected]> Signed-off-by: Shawn Guo <[email protected]>
2020-04-29clk: imx: pll14xx: Add the device as argument when registeringAbel Vesa2-7/+14
In order to allow runtime PM, the device needs to be passed on to the register function. Audiomix clock controller, used on i.MX8MP and future platforms, registers a pll14xx and has runtime PM support. Signed-off-by: Abel Vesa <[email protected]> Reviewed-by: Stephen Boyd <[email protected]> Signed-off-by: Shawn Guo <[email protected]>
2020-04-29clk: imx: gate2: Allow single bit gating clockAbel Vesa2-8/+36
Audiomix on i.MX8MP registers two gates that share the same enable count but use the same bit to control the gate instead of two bits. By adding the flag IMX_CLK_GATE2_SINGLE_BIT we allow the gate2 to use the generic gate ops for enable, disable and is_enabled. For the disable_unused, nothing happens if this flag is specified. Signed-off-by: Abel Vesa <[email protected]> Reviewed-by: Stephen Boyd <[email protected]> Signed-off-by: Shawn Guo <[email protected]>
2020-04-28firmware: xilinx: Use APIs instead of IOCTLsRajan Vaja1-10/+4
Remove IOCTL API and use individual APIs for better readability. Signed-off-by: Rajan Vaja <[email protected]> Signed-off-by: Jolly Shah <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Greg Kroah-Hartman <[email protected]>
2020-04-28firmware: xilinx: Remove eemi ops for clock set/get parentRajan Vaja1-4/+2
Use direct function call instead of eemi ops for clock set/get parent. Signed-off-by: Rajan Vaja <[email protected]> Signed-off-by: Jolly Shah <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Greg Kroah-Hartman <[email protected]>
2020-04-28firmware: xilinx: Remove eemi ops for clock_getdividerRajan Vaja2-5/+3
Use direct function call instead of using eemi ops for clock_getdivider. Signed-off-by: Rajan Vaja <[email protected]> Signed-off-by: Jolly Shah <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Greg Kroah-Hartman <[email protected]>
2020-04-28firmware: xilinx: Remove eemi ops for clock_setdividerRajan Vaja2-4/+3
Use direct function call instead of using eemi ops for clock_setdivider. Signed-off-by: Rajan Vaja <[email protected]> Signed-off-by: Jolly Shah <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Greg Kroah-Hartman <[email protected]>
2020-04-28firmware: xilinx: Remove eemi ops for clock_getstateRajan Vaja2-4/+2
Use direct function call instead of eemi ops for clock_getstate. Signed-off-by: Rajan Vaja <[email protected]> Signed-off-by: Jolly Shah <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Greg Kroah-Hartman <[email protected]>
2020-04-28firmware: xilinx: Remove eemi ops for clock_disableRajan Vaja2-5/+2
Use direct function call for clock_disable instead using of eemi ops. Signed-off-by: Rajan Vaja <[email protected]> Signed-off-by: Jolly Shah <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Greg Kroah-Hartman <[email protected]>
2020-04-28firmware: xilinx: Remove eemi ops for clock_enableRajan Vaja2-3/+2
Use direct function call for clock_enable instead of eemi ops. Signed-off-by: Rajan Vaja <[email protected]> Signed-off-by: Jolly Shah <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Greg Kroah-Hartman <[email protected]>
2020-04-28firmware: xilinx: Remove eemi ops for query_dataRajan Vaja2-13/+7
Use direct function call for query_data instead of using eemi ops. Signed-off-by: Rajan Vaja <[email protected]> Signed-off-by: Jolly Shah <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Greg Kroah-Hartman <[email protected]>
2020-04-21clk: qcom: msm8916: Fix the address location of pll->config_regBryan O'Donoghue1-4/+4
During the process of debugging a processor derived from the msm8916 which we found the new processor was not starting one of its PLLs. After tracing the addresses and writes that downstream was doing and comparing to upstream it became obvious that we were writing to a different register location than downstream when trying to configure the PLL. This error is also present in upstream msm8916. As an example clk-pll.c::clk_pll_recalc_rate wants to write to pll->config_reg updating the bit-field POST_DIV_RATIO. That bit-field is defined in PLL_USER_CTL not in PLL_CONFIG_CTL. Taking the BIMC PLL as an example lm80-p0436-13_c_qc_snapdragon_410_processor_hrd.pdf 0x01823010 GCC_BIMC_PLL_USER_CTL 0x01823014 GCC_BIMC_PLL_CONFIG_CTL This pattern is repeated for gpll0, gpll1, gpll2 and bimc_pll. This error is likely not apparent since the bootloader will already have initialized these PLLs. This patch corrects the location of config_reg from PLL_CONFIG_CTL to PLL_USER_CTL for all relevant PLLs on msm8916. Fixes commit 3966fab8b6ab ("clk: qcom: Add MSM8916 Global Clock Controller support") Cc: Georgi Djakov <[email protected]> Cc: Andy Gross <[email protected]> Cc: Bjorn Andersson <[email protected]> Cc: Michael Turquette <[email protected]> Cc: Stephen Boyd <[email protected]> Signed-off-by: Bryan O'Donoghue <[email protected]> Link: https://lkml.kernel.org/r/[email protected] Signed-off-by: Stephen Boyd <[email protected]>
2020-04-20clk: imx: clk-pllv3: Use readl_relaxed_poll_timeout() for PLL lock waitAnson Huang1-11/+5
Use readl_relaxed_poll_timeout() for PLL lock wait which can simplify the code a lot. Signed-off-by: Anson Huang <[email protected]> Reviewed-by: Abel Vesa <[email protected]> Reviewed-by: Stephen Boyd <[email protected]> Signed-off-by: Shawn Guo <[email protected]>
2020-04-20clk: imx: clk-sscg-pll: Remove unnecessary blank linesAnson Huang1-10/+0
Remove many unnecessary blank lines for cleanup. Signed-off-by: Anson Huang <[email protected]> Reviewed-by: Abel Vesa <[email protected]> Reviewed-by: Stephen Boyd <[email protected]> Signed-off-by: Shawn Guo <[email protected]>
2020-04-16clk: meson: g12a: Prepare the GPU clock tree to change at runtimeMartin Blumenstingl1-8/+22
The "mali_0" or "mali_1" clock trees should not be updated while the clock is running. Enforce this by setting CLK_SET_RATE_GATE on the "mali_0" and "mali_1" gates. This makes the CCF switch to the "mali_1" tree when "mali_0" is currently active and vice versa, which is exactly what the vendor driver does when updating the frequency of the mali clock. Also propagate set_rate requests from the gate to the divider and from the divider to the the mux so the GPU clock frequency can be updated at runtime (which will be required for GPU DVFS). Don't propagate rate changes to the mux parents because we don't want to change the MPLL clocks (these are reserved for audio). Signed-off-by: Martin Blumenstingl <[email protected]> Signed-off-by: Jerome Brunet <[email protected]> Acked-by: Neil Armstrong <[email protected]> Link: https://lore.kernel.org/r/[email protected]
2020-04-16clk: meson: gxbb: Prepare the GPU clock tree to change at runtimeMartin Blumenstingl1-18/+22
The "mali_0" or "mali_1" clock trees should not be updated while the clock is running. Enforce this by setting CLK_SET_RATE_GATE on the "mali_0" and "mali_1" gates. This makes the CCF switch to the "mali_1" tree when "mali_0" is currently active and vice versa, which is exactly what the vendor driver does when updating the frequency of the mali clock. Also propagate set_rate requests from the gate to the divider and from the divider to the the mux so the GPU clock frequency can be updated at runtime (which will be required for GPU DVFS). Don't propagate rate changes to the mux parents because we don't want to change the MPLL clocks (these are reserved for audio). Signed-off-by: Martin Blumenstingl <[email protected]> Signed-off-by: Jerome Brunet <[email protected]> Acked-by: Neil Armstrong <[email protected]> Link: https://lore.kernel.org/r/[email protected]
2020-04-14clk: imx: drop the dependency on ARM64 for i.MX8MPeng Fan1-4/+4
Moving to support aarch32 mode on aarch64 hardware, need to drop the dependency on ARM64 to make the driver could be selected for ARM32. Signed-off-by: Peng Fan <[email protected]> Acked-by: Arnd Bergmann <[email protected]> Acked-by: Stephen Boyd <[email protected]> Signed-off-by: Shawn Guo <[email protected]>
2020-04-14clk: imx7ulp: make it easy to change ARM core clkPeng Fan1-2/+4
ARM clk could only source from divcore or hsrun_divcore. Follow what we already used on i.MX7D and i.MX8M SoCs, use imx_clk_hw_cpu API. When ARM core is running normaly, whether divcore or hwrun_divcore will finally source from SPLL_PFD0. However SPLL_PFD0 is marked with CLK_SET_GATE, so we need to disable SPLL_PFD0, when configure the rate. So add CORE and HSRUN_CORE virtual clk to make it easy to configure the clk using imx_clk_hw_cpu API. Since CORE and HSRUN_CORE already marked with CLK_IS_CRITICAL, no need to set ARM as CLK_IS_CRITICAL. And when set the rate of ARM clk, prograting it the parent with CLK_SET_RATE_PARENT will finally set the SPLL_PFD0 clk. Signed-off-by: Peng Fan <[email protected]> Reviewed-by: Abel Vesa <[email protected]> Signed-off-by: Shawn Guo <[email protected]>
2020-04-14clk: meson: meson8b: make the hdmi_sys clock tree mutableMartin Blumenstingl1-3/+3
The HDMI TX controller requires the hdmi_sys clock to be enabled. Allow changing the whole clock tree now that we know that one of our drivers requires this. Signed-off-by: Martin Blumenstingl <[email protected]> Signed-off-by: Jerome Brunet <[email protected]> Link: https://lore.kernel.org/r/[email protected]
2020-04-14clk: meson8b: export the HDMI system clockMartin Blumenstingl1-1/+0
Export the HDMI system clock (used by the HDMI transmitter) so it can be used in the dt-bindings. Signed-off-by: Martin Blumenstingl <[email protected]> Signed-off-by: Jerome Brunet <[email protected]> Acked-by: Rob Herring <[email protected]> Link: https://lore.kernel.org/r/[email protected]
2020-04-14clk: renesas: r9a06g032: Fix some typo in commentsChristophe JAILLET1-3/+3
This file seems to be for R9A06G032 only. So replace reference to R9A09G032 by R9A06G032 to avoid confusion. AFAIK, R9A09G032 does'nt exist. Signed-off-by: Christophe JAILLET <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Geert Uytterhoeven <[email protected]>
2020-04-14clk: sunxi: Fix incorrect usage of round_down()Rikard Falkeborn1-1/+1
round_down() can only round to powers of 2. If round_down() is asked to round to something that is not a power of 2, incorrect results are produced. The incorrect results can be both too large and too small. Instead, use rounddown() which can round to any number. Fixes: 6a721db180a2 ("clk: sunxi: Add A31 clocks support") Signed-off-by: Rikard Falkeborn <[email protected]> Signed-off-by: Maxime Ripard <[email protected]>
2020-04-13clk: sprd: don't gate uart console clockChunyan Zhang1-1/+2
Don't gate uart1_eb which provides console clock, gating that clock would make serial stop working if serial driver didn't enable that explicitly. Fixes: 0e4b8a2349f3 ("clk: sprd: add clocks support for SC9863A") Signed-off-by: Chunyan Zhang <[email protected]> Link: https://lkml.kernel.org/r/[email protected] Signed-off-by: Stephen Boyd <[email protected]>
2020-04-13clk: mmp2: fix link error without mmp2Arnd Bergmann3-39/+32
The newly added function is only built into the kernel if mmp2 is enabled, causing a link error otherwise. arm-linux-gnueabi-ld: drivers/clk/mmp/clk.o: in function `mmp_register_pll_clks': clk.c:(.text+0x6dc): undefined reference to `mmp_clk_register_pll' Move it to a different file to get it to link. Fixes: 5d34d0b32d6c ("clk: mmp2: Add support for PLL clock sources") Signed-off-by: Arnd Bergmann <[email protected]> Link: https://lkml.kernel.org/r/[email protected] Reported-by: Guenter Roeck <[email protected]> Reported-by: kbuild test robot <[email protected]> Signed-off-by: Stephen Boyd <[email protected]>
2020-04-13clk: asm9260: fix __clk_hw_register_fixed_rate_with_accuracy typoArnd Bergmann1-1/+1
The __clk_hw_register_fixed_rate_with_accuracy() function (with two '_') does not exist, and apparently never did: drivers/clk/clk-asm9260.c: In function 'asm9260_acc_init': drivers/clk/clk-asm9260.c:279:7: error: implicit declaration of function '__clk_hw_register_fixed_rate_with_accuracy'; did you mean 'clk_hw_register_fixed_rate_with_accuracy'? [-Werror=implicit-function-declaration] 279 | hw = __clk_hw_register_fixed_rate_with_accuracy(NULL, NULL, pll_clk, | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ | clk_hw_register_fixed_rate_with_accuracy drivers/clk/clk-asm9260.c:279:5: error: assignment to 'struct clk_hw *' from 'int' makes pointer from integer without a cast [-Werror=int-conversion] 279 | hw = __clk_hw_register_fixed_rate_with_accuracy(NULL, NULL, pll_clk, | ^ From what I can tell, __clk_hw_register_fixed_rate() is the correct API here, so use that instead. Fixes: 728e3096741a ("clk: asm9260: Use parent accuracy in fixed rate clk") Signed-off-by: Arnd Bergmann <[email protected]> Link: https://lkml.kernel.org/r/[email protected] Signed-off-by: Stephen Boyd <[email protected]>
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