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2020-07-27clk: qcom: gcc-sdm660: Add missing modem resetKonrad Dybcio1-0/+1
This will be required in order to support the modem upstream. Signed-off-by: Konrad Dybcio <[email protected]> Link: https://lore.kernel.org/r/[email protected] Fixes: f2a76a2955c0 ("clk: qcom: Add Global Clock controller (GCC) driver for SDM660") Signed-off-by: Stephen Boyd <[email protected]>
2020-07-24clk: qcom: lpass: Add support for LPASS clock controller for SC7180Taniya Das3-0/+486
The Low Power Audio subsystem clocks are required for Audio client to be able to request for the clocks and power domains. Signed-off-by: Taniya Das <[email protected]> Link: https://lore.kernel.org/r/[email protected] [[email protected]: Drop unused ret in probe function] Signed-off-by: Stephen Boyd <[email protected]>
2020-07-24clk: qcom: gcc: Add support for GCC LPASS clock for SC7180Taniya Das1-0/+14
Add the GCC lpass clock which is required to access the LPASS core clocks. Signed-off-by: Taniya Das <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Stephen Boyd <[email protected]>
2020-07-24clk: qcom: gdsc: Add support to enable retention of GSDCRTaniya Das2-0/+13
Add support for the RETAIN_FF_ENABLE feature which enables the usage of retention registers. These registers maintain their state after disabling and re-enabling a GDSC. Signed-off-by: Taniya Das <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Stephen Boyd <[email protected]>
2020-07-24clk: Clean up kernel-doc errorsStephen Boyd1-0/+3
Two things aren't documented causing kernel-doc to fail when checking the core clk.c file. Fix them so that this file is clean. Signed-off-by: Stephen Boyd <[email protected]> Link: https://lore.kernel.org/r/[email protected]
2020-07-24clk: qcom: Export gdsc_gx_do_nothing_enable() to modulesStephen Boyd1-0/+2
A clk driver can be a module but the gdsc code is in the common module. Export this symbol so that allmodconfig builds keep working. Cc: Jonathan Marek <[email protected]> Fixes: 0638226dd095 ("clk: qcom: add common gdsc_gx_do_nothing_enable for gpucc drivers") Signed-off-by: Stephen Boyd <[email protected]> Link: https://lore.kernel.org/r/[email protected]
2020-07-24clk: at91: sama7g5: add clock support for sama7g5Claudiu Beznea2-0/+1060
Add clock support for SAMA7G5. Signed-off-by: Claudiu Beznea <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Stephen Boyd <[email protected]>
2020-07-24clk: at91: clk-utmi: add utmi support for sama7g5Claudiu Beznea2-5/+102
Add UTMI support for SAMA7G5. SAMA7G5's UTMI control is done via XTALF register. Values written at bits 2..0 in this register correspond to the on board crystal oscillator frequency. Signed-off-by: Claudiu Beznea <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Stephen Boyd <[email protected]>
2020-07-24clk: at91: clk-sam9x60-pll: re-factor to support plls with multiple outputsClaudiu Beznea3-186/+433
Some of the SAMA7G5 PLLs support multiple outputs (e.g. AUDIO PLL). For these, split the PLL clock in two: fractional clock and divider clock. In case PLLs supports multiple outputs (since these outputs are dividers (with different settings) sharing the same fractional part), it will register one fractional clock and multiple divider clocks (dividers sharing the fractional clock). Signed-off-by: Claudiu Beznea <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Stephen Boyd <[email protected]>
2020-07-24clk: at91: clk-programmable: add mux_table optionClaudiu Beznea13-17/+38
Add mux table option. This is necessary for IP versions that has gaps in the range of available clock sources (e.g. SAMA7G5). Signed-off-by: Claudiu Beznea <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Stephen Boyd <[email protected]>
2020-07-24clk: at91: clk-peripheral: add support for changeable parent rateClaudiu Beznea9-16/+119
Some peripheral clocks on SAMA7G5 supports requesting parent to change its rate (image related clocks: csi, csi2dc, isc). Add support so that if registered with this option the clock rate to be requested from parent. Signed-off-by: Claudiu Beznea <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Stephen Boyd <[email protected]>
2020-07-24clk: at91: clk-master: add master clock support for SAMA7G5Claudiu Beznea2-5/+312
Add master clock support (MCK1..4) for SAMA7G5. SAMA7G5's PMC has multiple master clocks feeding different subsystems. One of them feeds image subsystem and is changeable based on image subsystem needs. Signed-off-by: Claudiu Beznea <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Stephen Boyd <[email protected]>
2020-07-24clk: at91: clk-generated: add mux_table optionClaudiu Beznea5-8/+16
Add mux table option. This is necessary for IP versions that has gaps in the range of available clock sources (e.g. SAMA7G5). Signed-off-by: Claudiu Beznea <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Stephen Boyd <[email protected]>
2020-07-24clk: at91: clk-generated: pass the id of changeable parent at registrationClaudiu Beznea5-35/+37
Pass the ID of changeable parent at registration. This will allow the scalability of this clock driver with regards to the changeable parent ID for versions of this IP where changeable parent is not the last one in the parents list (e.g. SAMA7G5). With this the clock flags are set to zero in case we have no changeable parent. Also in clk_generated_best_diff() the *best_diff variable is check against tmp_diff variable using ">=" operator instead of ">" so that in case the requested frequency could be obtained using fix parents + gck dividers but the clock also supports changeable parent to be able to force the usage of the changeable parent. Signed-off-by: Claudiu Beznea <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Stephen Boyd <[email protected]>
2020-07-24clk: at91: replace conditional operator with double logical notClaudiu Beznea5-8/+8
Replace conditional operator with double logical not as code may be simpler to read. Signed-off-by: Claudiu Beznea <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Stephen Boyd <[email protected]>
2020-07-24clk: at91: sckc: register slow_rc with accuracy optionClaudiu Beznea1-2/+3
Chapter 57.7.5 of SAM9X60 datasheet specifies that the maximum drift of this oscillator is +- 3KHz. Use that value and the formula at [1] or the calculator at [2] to compute the PPB value. [1] https://www.everythingrf.com/rf-calculators/ppm-to-hz-calculator [2] https://www.changpuak.ch/electronics/ppm_to_Hz_converter.php Fixes: 04bcc4275e601 ("clk: at91: sckc: add support for SAM9X60") Signed-off-by: Claudiu Beznea <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Stephen Boyd <[email protected]>
2020-07-24clk: at91: sam9x60: fix main rc oscillator frequencyClaudiu Beznea1-1/+1
Main RC oscillator frequency is 12MHz according to datasheet (chapter 27.2). Fixes: 01e2113de9a52 ("clk: at91: add sam9x60 pmc driver") Signed-off-by: Claudiu Beznea <[email protected]> Reviewed-by: Alexandre Belloni <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Stephen Boyd <[email protected]>
2020-07-24clk: at91: sam9x60-pll: use frac when setting frequencyClaudiu Beznea1-4/+8
In commit a436c2a447e59 ("clk: at91: add sam9x60 PLL driver") the fractional part of PLL wasn't set on registers but it was calculated and taken into account for determining div and mul (see sam9x60_pll_get_best_div_mul()). Fixes: a436c2a447e59 ("clk: at91: add sam9x60 PLL driver") Signed-off-by: Claudiu Beznea <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Stephen Boyd <[email protected]>
2020-07-24clk: at91: sam9x60-pll: check fcore against rangesClaudiu Beznea2-2/+12
According to datasheet the range of 600-1200MHz is for the frequency generated by the fractional part of the PLL (namely Fcorepllck according to datasheet). With this in mind the output range of the PLL itself (fractional + div), taking into account that the divider is 8 bits wide, is 600/256-1200Hz=2.3-1200MHz. Fixes: a436c2a447e59 ("clk: at91: add sam9x60 PLL driver") Signed-off-by: Claudiu Beznea <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Stephen Boyd <[email protected]>
2020-07-24clk: at91: sam9x60-pll: use logical or for range checkClaudiu Beznea1-1/+1
Use logical or for range check. In case bestrate is not in characteristics->output[0].min..characteristics->output[0].max range we should return -ERANGE. Fixes: a436c2a447e59 ("clk: at91: add sam9x60 PLL driver") Signed-off-by: Claudiu Beznea <[email protected]> Reviewed-by: Alexandre Belloni <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Stephen Boyd <[email protected]>
2020-07-24clk: at91: clk-sam9x60-pll: fix mul maskClaudiu Beznea1-1/+1
According to datasheet mul mask is on bits 31..24. Fixes: a436c2a447e59 ("clk: at91: add sam9x60 PLL driver") Signed-off-by: Claudiu Beznea <[email protected]> Reviewed-by: Alexandre Belloni <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Stephen Boyd <[email protected]>
2020-07-24clk: at91: clk-generated: check best_rate against rangesClaudiu Beznea1-2/+2
Check best_rate against available clock ranges. Fixes: df70aeef6083 ("clk: at91: add generated clock driver") Signed-off-by: Claudiu Beznea <[email protected]> Reviewed-by: Alexandre Belloni <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Stephen Boyd <[email protected]>
2020-07-24clk: at91: clk-generated: continue if __clk_determine_rate() returns errorClaudiu Beznea1-1/+2
__clk_determine_rate() may return error. Skip the current step in case of error. Fixes: 1a1a36d72e3d3 ("clk: at91: clk-generated: make gclk determine audio_pll rate") Signed-off-by: Claudiu Beznea <[email protected]> Reviewed-by: Alexandre Belloni <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Stephen Boyd <[email protected]>
2020-07-24clk: at91: fix possible dead lock in new driversAhmad Fatoum4-4/+4
syscon_node_to_regmap() will make the created regmap get and enable the first clock it can parse from the device tree. This clock is not needed to access the registers and should not be enabled at that time. Use device_node_to_regmap to resolve this as it looks up the regmap in the same list but doesn't care about the clocks. This issue is detected by lockdep when booting the sama5d3 with a device tree containing the new clk bindings. This fix already happened in 6956eb33abb5 ("clk: at91: fix possible deadlock") for the drivers that had been migrated to the new clk binding back then. This does the same for the new drivers as well. Fixes: 01e2113de9a5 ("clk: at91: add sam9x60 pmc driver") Signed-off-by: Ahmad Fatoum <[email protected]> Link: https://lore.kernel.org/r/[email protected] Acked-by: Alexandre Belloni <[email protected]> Signed-off-by: Stephen Boyd <[email protected]>
2020-07-24clk: Add support for enabling/disabling clocks from debugfsMike Tipton1-0/+29
For test and debug purposes, it's simple enough to enable or disable clocks from shell. Add a new debugfs file 'clk_prepare_enable' that calls clk_prepare_enable() when writing "1" and clk_disable_unprepare() when writing "0". This can have security implications, so only support it when the code has been modified to #define CLOCK_ALLOW_WRITE_DEBUGFS. Signed-off-by: Mike Tipton <[email protected]> Link: https://lore.kernel.org/r/[email protected] [[email protected]: Reword commit text and remove comment update] Signed-off-by: Stephen Boyd <[email protected]>
2020-07-24clk: intel: Avoid unnecessary memset by improving codeRahul Tanwar1-4/+3
memset can be avoided in a loop if the variables used are declared inside the loop. Move such variables declaration inside the loop to avoid memset. Signed-off-by: Rahul Tanwar <[email protected]> Link: https://lore.kernel.org/r/26624b65d0e6b958c4765a406b9929d1a9ce1c2c.1594880946.git.rahul.tanwar@linux.intel.com [[email protected]: Drop NULL assignment that is overwritten] Signed-off-by: Stephen Boyd <[email protected]>
2020-07-24clk: intel: Improve locking in the driverRahul Tanwar1-12/+5
Remove/reduce unnecessary spin locking of the code. Signed-off-by: Rahul Tanwar <[email protected]> Link: https://lore.kernel.org/r/79c0f5f9f5bc512a7e2b5f3c91f6341f28b5854c.1594880946.git.rahul.tanwar@linux.intel.com Signed-off-by: Stephen Boyd <[email protected]>
2020-07-24clk: intel: Use devm_clk_hw_register() instead of clk_hw_register()Rahul Tanwar2-5/+5
To ensure that clks are unregistered in case of any failure, use devm_clk_hw_register() instead of clk_hw_register(). Signed-off-by: Rahul Tanwar <[email protected]> Link: https://lore.kernel.org/r/7ef7009b4e9f986fd6dfbf487c0e85de68a4ba9b.1594880946.git.rahul.tanwar@linux.intel.com Signed-off-by: Stephen Boyd <[email protected]>
2020-07-24clk: iproc: round clock rate to the closestLori Hikichi1-2/+2
Change from 'DIV_ROUND_UP' to 'DIV_ROUND_CLOSEST' when calculating the clock divisor in the iProc ASIU clock driver to allow to get to the closest clock rate. Fixes: 5fe225c105fd ("clk: iproc: add initial common clock support") Signed-off-by: Lori Hikichi <[email protected]> Signed-off-by: Ray Jui <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Stephen Boyd <[email protected]>
2020-07-24clk: qcom: Add graphics clock controller driver for SM8250Jonathan Marek3-0/+357
Add support for the graphics clock controller found on SM8250 based devices. This is initially copied from the downstream kernel, but has been modified to more closely match the upstream sc7180 driver. Signed-off-by: Jonathan Marek <[email protected]> Tested-by: Dmitry Baryshkov <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Stephen Boyd <[email protected]>
2020-07-24clk: qcom: Add graphics clock controller driver for SM8150Jonathan Marek3-0/+329
Add support for the graphics clock controller found on SM8150 based devices. This is initially copied from the downstream kernel, but has been modified to more closely match the upstream sc7180 driver. Signed-off-by: Jonathan Marek <[email protected]> Tested-by: Dmitry Baryshkov <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Stephen Boyd <[email protected]>
2020-07-24clk: qcom: add common gdsc_gx_do_nothing_enable for gpucc driversJonathan Marek4-52/+28
All gpucc drivers need this, so move it to common code instead of duplicating it in every gpucc driver. Signed-off-by: Jonathan Marek <[email protected]> Tested-by: Dmitry Baryshkov <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Stephen Boyd <[email protected]>
2020-07-24clk: qcom: gcc: remove unnecessary vco_table from SM8150Jonathan Marek1-10/+0
The fixed alpha pll ops only use it for clamping in round_rate, which is unnecessary. This is consistent with SM8250 GCC not using vco_table. Signed-off-by: Jonathan Marek <[email protected]> Tested-by: Dmitry Baryshkov <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Stephen Boyd <[email protected]>
2020-07-24clk: qcom: clk-alpha-pll: use the right PCAL_DONE value for lucid pllJonathan Marek2-3/+27
Lucid PCAL_DONE is different from trion. Signed-off-by: Jonathan Marek <[email protected]> Tested-by: Dmitry Baryshkov <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Stephen Boyd <[email protected]>
2020-07-24clk: qcom: clk-alpha-pll: same regs and ops for trion and lucidJonathan Marek3-51/+32
Fixed ops were already identical, this adds support for non-fixed ops by sharing between trion and lucid. This also changes the names for trion ops to be consistent with the rest. Note LUCID_PCAL_DONE is renamed to TRION_PCAL_DONE because it is wrong for lucid, LUCID_PCAL_DONE should be BIT(27). Next patch will address this. Signed-off-by: Jonathan Marek <[email protected]> Tested-by: Dmitry Baryshkov <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Stephen Boyd <[email protected]>
2020-07-24clk: qcom: clk-alpha-pll: remove unused/incorrect PLL_CAL_VALJonathan Marek1-2/+0
0x44 isn't a register offset, it is the value that goes into CAL_L_VAL. Fixes: 548a909597d5 ("clk: qcom: clk-alpha-pll: Add support for Trion PLLs") Signed-off-by: Jonathan Marek <[email protected]> Tested-by: Dmitry Baryshkov <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Stephen Boyd <[email protected]>
2020-07-24clk: qcom: gcc: fix sm8150 GPU and NPU clocksJonathan Marek1-2/+6
Fix the parents and set BRANCH_HALT_SKIP. From the downstream driver it should be a 500us delay and not skip, however this matches what was done for other clocks that had 500us delay in downstream. Fixes: f73a4230d5bb ("clk: qcom: gcc: Add GPU and NPU clocks for SM8150") Signed-off-by: Jonathan Marek <[email protected]> Tested-by: Dmitry Baryshkov <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Stephen Boyd <[email protected]>
2020-07-23clk: vc5: use a dedicated struct to describe the output driversLuca Ceresoli1-9/+15
Reusing the generic struct vc5_hw_data for all blocks is handy. However it implies we allocate space the div_int and div_frc fields even for the output drivers where they are unused, and the clk_output_cfg0 and clk_output_cfg0_mask fields for all components even though they are used only for the output drivers. Use a dedicated struct for the output drivers so that each block uses exactly the fields it needs, not more. Signed-off-by: Luca Ceresoli <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Stephen Boyd <[email protected]>
2020-07-22clk: vc5: Add memory check to prevent oopsAdam Ford1-3/+5
When getting the names of the child nodes, kasprintf is used to allocate memory which is used to create the string for the node name. Unfortunately, there is no memory check to determine if this allocation fails, it may cause an error when trying to get child node name. This patch will check if the memory allocation fails, and returns and -ENOMEM error instead of blindly moving on. Fixes: 260249f929e8 ("clk: vc5: Enable addition output configurations of the Versaclock") Suggested-by: Dan Carpenter <[email protected]> Signed-off-by: Adam Ford <[email protected]> Reviewed-by: Luca Ceresoli <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Stephen Boyd <[email protected]>
2020-07-22clk: vc5: fix use of memory after it has been kfree'dColin Ian King1-32/+18
There are a several places where printing an error message of init.name occurs after init.name has been kfree'd. Also the failure message is duplicated each time in the code. Fix this by adding a registration error failure path for these cases, moving the duplicated error messages to one common point and kfree'ing init.name only after it has been used. Changes also shrink the object code size by 171 bytes (x86-64, gcc 9.3): Before: text data bss dec hex filename 21057 3960 64 25081 61f9 drivers/clk/clk-versaclock5.o After: text data bss dec hex filename 20886 3960 64 24910 614e drivers/clk/clk-versaclock5.o Addresses-Coverity: ("Use after free") Fixes: f491276a5168 ("clk: vc5: Allow Versaclock driver to support multiple instances") Signed-off-by: Colin Ian King <[email protected]> Link: https://lore.kernel.org/r/[email protected] Reviewed-by: Luca Ceresoli <[email protected]> [[email protected]: Drop stray newline] Signed-off-by: Stephen Boyd <[email protected]>
2020-07-22clk: rockchip: add sclk_mac_lbtest to rk3188_critical_clocksAlex Bee1-0/+1
Since the loopbacktest clock is not exported and is not touched in the driver, it has to be added to rk3188_critical_clocks to be protected from being disabled and in order to get the emac working. Signed-off-by: Alex Bee <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Heiko Stuebner <[email protected]>
2020-07-21clk: actions: Add Actions S500 SoC Reset Management Unit supportCristian Ciocaltea1-0/+78
Add Reset Management Unit (RMU) support for Actions Semi S500 SoC. Signed-off-by: Cristian Ciocaltea <[email protected]> Reviewed-by: Manivannan Sadhasivam <[email protected]> Link: https://lore.kernel.org/r/3fba2e6f0edfac97cb8c6ce60f95c24852578eac.1593788312.git.cristian.ciocaltea@gmail.com Signed-off-by: Stephen Boyd <[email protected]>
2020-07-21clk: actions: Add APB, DMAC, GPIO clock support for Actions S500 SoCCristian Ciocaltea1-0/+9
Add support for the missing APB, DMAC and GPIO clocks in the Actions Semi S500 SoC clock driver. Signed-off-by: Cristian Ciocaltea <[email protected]> Link: https://lore.kernel.org/r/87964ae012e513597b8b4c7be2e7ac332a70087a.1593788312.git.cristian.ciocaltea@gmail.com Reviewed-by: Manivannan Sadhasivam <[email protected]> Signed-off-by: Stephen Boyd <[email protected]>
2020-07-21clk: actions: Fix h_clk for Actions S500 SoCCristian Ciocaltea1-1/+1
The h_clk clock in the Actions Semi S500 SoC clock driver has an invalid parent. Replace with the correct one. Fixes: ed6b4795ece4 ("clk: actions: Add clock driver for S500 SoC") Signed-off-by: Cristian Ciocaltea <[email protected]> Reviewed-by: Manivannan Sadhasivam <[email protected]> Link: https://lore.kernel.org/r/c57e7ebabfa970014f073b92fe95b47d3e5a70b1.1593788312.git.cristian.ciocaltea@gmail.com Signed-off-by: Stephen Boyd <[email protected]>
2020-07-21Merge branch 'clk-imx' into clk-nextStephen Boyd2-0/+2
* clk-imx: clk: imx: vf610: add CAAM clock clk: imx8mp: add mu root clk
2020-07-21Merge branch 'clk-amlogic' into clk-nextStephen Boyd4-19/+178
* clk-amlogic: clk: meson: meson8b: add the vclk2_en gate clock clk: meson: meson8b: add the vclk_en gate clock clk: meson: meson8b: Drop CLK_IS_CRITICAL from fclk_div2 clk: meson: g12a: Add support for NNA CLK source clocks dt-bindings: clk: g12a-clkc: Add NNA CLK Source clock IDs
2020-07-21Merge branch 'clk-renesas' into clk-nextStephen Boyd5-0/+362
* clk-renesas: clk: renesas: cpg-mssr: Add r8a774e1 support dt-bindings: clock: renesas,cpg-mssr: Document r8a774e1 clk: renesas: Add r8a774e1 CPG Core Clock Definitions dt-bindings: power: Add r8a774e1 SYSC power domain definitions
2020-07-21Merge branch 'clk-qcom' into clk-nextStephen Boyd4-5/+5
* clk-qcom: clk: qcom: gcc: Make disp gpll0 branch aon for sc7180/sdm845 ipq806x: gcc: add support for child probe clk: qcom: msm8996: Make symbol 'cpu_msm8996_clks' static clk: qcom: ipq8074: Add correct index for PCIe clocks
2020-07-21clk: qcom: gcc: Make disp gpll0 branch aon for sc7180/sdm845Taniya Das2-3/+3
The display gpll0 branch clock inside GCC needs to always be enabled. Otherwise the AHB clk (disp_cc_mdss_ahb_clk_src) for the display clk controller (dispcc) will stop clocking while sourcing from gpll0 when this branch inside GCC is turned off during unused clk disabling. We can never turn this branch off because the AHB clk for the display subsystem is needed to read/write any registers inside the display subsystem including clk related ones. This makes this branch a really easy way to turn off AHB access to the display subsystem and cause all sorts of mayhem. Let's just make the clk ops keep the clk enabled forever and ignore any attempts to disable this clk so that dispcc accesses keep working. Signed-off-by: Taniya Das <[email protected]> Reported-by: Evan Green <[email protected]> Link: https://lore.kernel.org/r/[email protected] Fixes: 17269568f726 ("clk: qcom: Add Global Clock controller (GCC) driver for SC7180") Fixes: 06391eddb60a ("clk: qcom: Add Global Clock controller (GCC) driver for SDM845") [[email protected]: Fill out commit text more] Signed-off-by: Stephen Boyd <[email protected]>
2020-07-21ipq806x: gcc: add support for child probeAnsuel Smith1-1/+1
Add support for child probing needed for tsens driver that share the same regs of gcc for this platform. Signed-off-by: Ansuel Smith <[email protected]> Reviewed-by: Amit Kucheria <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Stephen Boyd <[email protected]>
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