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2014-07-15clk: qcom: mdp_lut_clk is a child of mdp_srcStephen Boyd1-1/+1
The mdp_lut_clk isn't a child of the mdp_clk. Instead it's the child of the mdp_src clock. Fix it. Fixes: 6d00b56fe "clk: qcom: Add support for MSM8960's multimedia clock controller (MMCC)" Signed-off-by: Stephen Boyd <[email protected]>
2014-07-15clk: qcom: Fix PLL rate configurationsStephen Boyd3-17/+38
Sometimes we need to program PLLs with a fixed rate configuration during driver probe. Doing this after we register the PLLs with the clock framework causes the common clock framework to assume the rate of the PLLs are 0. This causes all sorts of problems for rate recalculations because the common clock framework caches the rate once at registration time unless a flag is set to always recalculate the rates. Split the qcom_cc_probe() function into two pieces, map and everything else, so that drivers which need to configure some PLL rates or otherwise twiddle bits in the clock controller can do so before registering clocks. This allows us to properly detect the rates of PLLs that are programmed at boot. Fixes: 49fc825f0cc2 "clk: qcom: Consolidate common probe code" Signed-off-by: Stephen Boyd <[email protected]>
2014-07-15clk: qcom: Fix MN frequency tables, parent map, and jpegdStephen Boyd1-40/+42
Clocks that don't have a pre-divider don't list any pre-divider in their frequency tables, but their tables are initialized using aggregate initializers. Use tagged initializers so we properly assign the m and n values for each frequency. Furthermore, the mmcc_pxo_pll8_pll2_pll3 array improperly mapped the second element to pll2 instead of pll8, causing the clock driver to recalculate the wrong rate for any clocks using this array along with a rate that uses pll2. Plus the .num_parents field is 3 instead of 4 so you can't even switch the parent to pll3. Finally I noticed that the jpegd clock improperly indicates that the pre-divider width is only 2, when it's actually 4 bits wide. Fixes: 6d00b56fe "clk: qcom: Add support for MSM8960's multimedia clock controller (MMCC)" Tested-by: Rob Clark <[email protected]> Signed-off-by: Stephen Boyd <[email protected]>
2014-07-15clk: qcom: Support bypass RCG configurationStephen Boyd3-14/+47
In the case of HDMI clocks, we want to bypass the RCG's ability to divide the output clock and pass through the parent HDMI PLL rate. Add a simple set of clk_ops to configure the RCG to do this. This removes the need to keep adding more frequency entries to the tv_src clock whenever we want to support a new rate. Tested-by: Rob Clark <[email protected]> Signed-off-by: Stephen Boyd <[email protected]>
2014-07-15clk: qcom: Add support for IPQ8064's global clock controller (GCC)Kumar Gala3-0/+2433
Add a driver for the global clock controller found on IPQ8064 based platforms. This should allow most non-multimedia device drivers to probe and control their clocks. This is currently missing clocks for USB HSIC and networking devices. Signed-off-by: Kumar Gala <[email protected]> Signed-off-by: Andy Gross <[email protected]> Signed-off-by: Stephen Boyd <[email protected]>
2014-07-15clk: qcom: Add APQ8084 Multimedia Clock Controller (MMCC) supportGeorgi Djakov3-0/+3362
Add support for the multimedia clock controller found on the APQ8084 based platforms. This will allow the multimedia device drivers to control their clocks. Signed-off-by: Georgi Djakov <[email protected]> [sboyd: Rework parent mapping to avoid conflicts] Signed-off-by: Stephen Boyd <[email protected]>
2014-07-15clk: sunxi: sun6i-a31-apb0-gates: Add A23 APB0 supportChen-Yu Tsai1-0/+5
This patch adds "allwinner,sun8i-a23-apb0-gates-clk", a A23 specific compatible to the sun6i-a31-apb0-gates clock driver, along with the gate bitmap. Signed-off-by: Chen-Yu Tsai <[email protected]> Signed-off-by: Maxime Ripard <[email protected]>
2014-07-15clk: sunxi: sun6i-apb0-gates: use bitmaps for valid gate indicesChen-Yu Tsai1-36/+39
sun6i-apb0-gates uses the "clock-indices" DT property to indicate valid gate bits or holes in between. However, the rest of sunxi clock drivers use bitmaps for this purpose. This patch modifies sun6i-apb0-gates to use bitmaps as well, to be consistent with the sunxi platform. Also add the missing call to clk_register_clkdev, so system clock lookups will work. Signed-off-by: Chen-Yu Tsai <[email protected]> Signed-off-by: Maxime Ripard <[email protected]>
2014-07-13Merge tag 'clk-fixes-for-linus' of ↵Linus Torvalds12-67/+93
git://git.linaro.org/people/mike.turquette/linux Pull clock driver fixes from Mike Turquette: "This batch of fixes is for a handful of clock drivers from Allwinner, Samsung, ST & TI. Most of them are of the "this hardware won't work without this fix" variety, including patches that fix platforms that did not boot under certain configurations. Other fixes are the result of changes to the clock core introduced in 3.15 that had subtle impacts on the clock drivers. There are no fixes to the clock framework core in this pull request" * tag 'clk-fixes-for-linus' of git://git.linaro.org/people/mike.turquette/linux: clk: spear3xx: Set proper clock parent of uart1/2 clk: spear3xx: Use proper control register offset clk: qcom: HDMI source sel is 3 not 2 clk: sunxi: fix devm_ioremap_resource error detection code clk: s2mps11: Fix double free corruption during driver unbind clk: ti: am43x: Fix boot with CONFIG_SOC_AM33XX disabled clk: exynos5420: Remove aclk66_peric from the clock tree description clk/exynos5250: fix bit number for tv sysmmu clock clk: s3c64xx: Hookup SPI clocks correctly clk: samsung: exynos4: Remove SRC_MASK_ISP gates clk: samsung: add more aliases for s3c24xx clk: samsung: fix several typos to fix boot on s3c2410 clk: ti: set CLK_SET_RATE_NO_REPARENT for ti,mux-clock clk: ti: am43x: Fix boot with CONFIG_SOC_AM33XX disabled clk: ti: dra7: return error code in failure case clk: ti: apll: not allocating enough data
2014-07-13clk: rockchip: add clock controller for rk3288Heiko Stübner3-0/+727
Add the clock tree definition for the new rk3288 SoC. Signed-off-by: Heiko Stuebner <[email protected]> Acked-By: Max Schwarz <[email protected]> Tested-By: Max Schwarz <[email protected]> Signed-off-by: Mike Turquette <[email protected]>
2014-07-13clk: rockchip: add clock driver for rk3188 and rk3066 clocksHeiko Stübner2-0/+674
This adds a clock driver that handles the specific muxes, dividers and gates of rk3188 and rk3066 SoCs. The structure of the clock list resembles the arrangement of their counterparts in the clock architecture diagrams found in the SoC documentation. Clocks exported to the clock provider are currently limited to well known or measured ones. So additional clock exports may be necessary in the future. Signed-off-by: Heiko Stuebner <[email protected]> Acked-By: Max Schwarz <[email protected]> Tested-By: Max Schwarz <[email protected]> Signed-off-by: Mike Turquette <[email protected]>
2014-07-13clk: rockchip: add reset controllerHeiko Stübner3-0/+133
All Rockchip SoCs at least down to the ARM9-based RK28xx include the reset- controller for SoC peripherals in their clock controller. While the older SoCs (ARM9 and Cortex-A8) use a regular scheme to change register values, the Cortex-A9 SoCs use a hiword-mask making locking unecessary. To be compatible with both schemes the reset controller takes a flag to decide which scheme to use, similar to the other HIWORD_MASK flags used in the clock framework. Signed-off-by: Heiko Stuebner <[email protected]> Acked-By: Max Schwarz <[email protected]> Tested-By: Max Schwarz <[email protected]> Signed-off-by: Mike Turquette <[email protected]>
2014-07-13clk: rockchip: add clock type for pll clocks and pll used on rk3066Heiko Stübner4-0/+541
All known Rockchip SoCs down to the RK28xx (ARM9) use a similar pattern to handle their plls: |--\ xin32k ----------------|mux\ xin24m -----| pll |----|pll|--- pll output \---------------|src/ |--/ The pll output is sourced from 1 of 3 sources, the actual pll being one of them. To change the pll frequency it is imperative to remux it to another source beforehand. This is done by adding a clock-listener to the pll that handles the remuxing before and after the rate change. The output mux is implemented as a separate clock to make use of already existing common-clock features for disabling the pll if one of the other two sources is used. Signed-off-by: Heiko Stuebner <[email protected]> Acked-By: Max Schwarz <[email protected]> Tested-By: Max Schwarz <[email protected]> Signed-off-by: Mike Turquette <[email protected]>
2014-07-13clk: rockchip: add basic infrastructure for clock branchesHeiko Stübner3-0/+460
This adds infrastructure for registering clock branches. On Rockchip SoCs most clock branches are a combination of mux,divider and gate components, thus a composite clock is used when appropriate. Clock branches are supposed to be declared in an array using the COMPOSITE* or MUX, etc makros defined in the header and then registered using rockchip_clk_register_branches. Signed-off-by: Heiko Stuebner <[email protected]> Acked-By: Max Schwarz <[email protected]> Tested-By: Max Schwarz <[email protected]> Signed-off-by: Mike Turquette <[email protected]>
2014-07-13clk: composite: improve rate_hw sanity check logicMike Turquette1-10/+16
The function pointer population and sanity checking logic got a bit ugly with the advent of the .determine_rate callback. Clean it up. Signed-off-by: Mike Turquette <[email protected]>
2014-07-13clk: composite: allow read-only clocksHeiko Stübner1-6/+3
This allows readl-only composite clocks by making mux_ops->set_parent and divider_ops->round_rate/set_rate optional. Signed-off-by: Heiko Stuebner <[email protected]> Acked-By: Max Schwarz <[email protected]> Tested-By: Max Schwarz <[email protected]> Signed-off-by: Mike Turquette <[email protected]>
2014-07-13clk: composite: support determine_rate using rate_ops->round_rate + ↵Boris BREZILLON1-1/+47
mux_ops->set_parent In case the rate_hw does not implement determine_rate, but only round_rate we fallback to best_parent selection if mux_hw is present and support reparenting. This also fixes a rate calculation problem when using the standard div and mux ops, as in this case currently only the mux->determine_rate is used in the composite rate calculation. So when for example the composite clock has two parents at 600 and 800MHz, the requested rate is 75MHz, which the divider could provide, without this change the rate would be set 600MHz ignoring the divider completely. This may be way out of spec for the component. Signed-off-by: Boris BREZILLON <[email protected]> Signed-off-by: Heiko Stuebner <[email protected]> [[email protected]: fixed output return a rate instead of the diff] Acked-By: Max Schwarz <[email protected]> Tested-By: Max Schwarz <[email protected]> Tested-by: Gabriel Fernandez <[email protected]> Signed-off-by: Mike Turquette <[email protected]>
2014-07-13Merge branch 'clk-fixes' into clk-nextMike Turquette1-5/+11
2014-07-13clk: spear3xx: Set proper clock parent of uart1/2Thomas Gleixner1-4/+10
The uarts only work when the parent is ras_ahb_clk. The stale 3.5 based ST tree does this in the board file. Add it to the clk init function. Not pretty, but the mess there is amazing anyway. Signed-off-by: Thomas Gleixner <[email protected]> Acked-by: Viresh Kumar <[email protected]> Signed-off-by: Mike Turquette <[email protected]>
2014-07-13clk: spear3xx: Use proper control register offsetThomas Gleixner1-1/+1
The control register is at offset 0x10, not 0x0. This is wreckaged since commit 5df33a62c (SPEAr: Switch to common clock framework). Signed-off-by: Thomas Gleixner <[email protected]> Cc: [email protected] Acked-by: Viresh Kumar <[email protected]> Signed-off-by: Mike Turquette <[email protected]>
2014-07-11clk: qcom: Add APQ8084 clocks for SATA, PCIe and UFSGeorgi Djakov1-0/+667
Add the necessary clocks for SATA, PCIe and UFS to the APQ8084 global clock controller (GCC). This will allow the above device drivers to control their clocks. Signed-off-by: Georgi Djakov <[email protected]> Signed-off-by: Stephen Boyd <[email protected]>
2014-07-11clk: qcom: Add APQ8084 Global Clock Controller supportGeorgi Djakov3-0/+2953
This patch adds support for the global clock controller found on the APQ8084 based devices. This includes UART, I2C, SPI etc. Signed-off-by: Georgi Djakov <[email protected]> Signed-off-by: Stephen Boyd <[email protected]>
2014-07-11clk: qcom: Fully support apq8064 global clock controlStephen Boyd1-4/+569
Add in the handful of new clocks and introduce a new reset table with the few new resets. Signed-off-by: Stephen Boyd <[email protected]>
2014-07-11clk: qcom: add clocks necessary for apq8064 sdccSrinivas Kandagatla1-0/+12
This patch adds clocks necessary for SD card controller on apq8064 SOC. Without this patch the clocks are not visible to the sdcc driver. Signed-off-by: Srinivas Kandagatla <[email protected]> Reviewed-by: Kumar Gala <[email protected]> Signed-off-by: Stephen Boyd <[email protected]>
2014-07-11ARM: SPEAr13xx: Fix pcie clock namePratyush Anand2-4/+4
Follow dt clock naming convention for PCIe clocks. Signed-off-by: Pratyush Anand <[email protected]> Acked-by: Viresh Kumar <[email protected]> [viresh: fixed logs/cclist] Signed-off-by: Viresh Kumar <[email protected]> Signed-off-by: Mike Turquette <[email protected]>
2014-07-11clk: exynos5420: Add IDs for clocks used in PD mfcArun Kumar K1-2/+4
Adds IDs for MUX clocks to be used by power domain for MFC for doing re-parenting while pd on/off. Signed-off-by: Arun Kumar K <[email protected]> Signed-off-by: Shaik Ameer Basha <[email protected]> Acked-by: Tomasz Figa <[email protected]> Signed-off-by: Kukjin Kim <[email protected]>
2014-07-08Merge tag 'tegra-clk-3.17-1' of ↵Mike Turquette5-4/+66
git://nv-tegra.nvidia.com/user/pdeschrijver/linux into clk-next-tegra tegra clk updates for 3.17 including PLLE fixes for xusb
2014-07-08clk: tegra: Use XUSB-compatible SATA PLL sequenceMikko Perttunen1-0/+11
Use a sequence for enabling hardware control of the SATA PLL that works both when using the SATA lane with SATA and when using it with XUSB. Signed-off-by: Mikko Perttunen <[email protected]>
2014-07-07clk: sunxi: Fix gate indexing for sun6i-a31-apb0-gatesChen-Yu Tsai1-1/+5
sun6i-a31-apb0-gates supports using clock-indices for holes between individual gates. However, the driver passes the number of gates registered in clk_data->clk_num, which of_clk_src_onecell_get uses to recognize the range of valid indices a consumer can use. This patch makes the driver pass the maximum gate index + 1, so of_clk_src_onecell_get does not complain about indices greater than gates registered. This was tested on the A23 SoC, which has a similar APB0 clock, but has holes for gates to removed IP blocks. Signed-off-by: Chen-Yu Tsai <[email protected]> Acked-by: Maxime Ripard <[email protected]> Signed-off-by: Maxime Ripard <[email protected]>
2014-07-07clk: sunxi: Add A23 APB0 divider clock supportChen-Yu Tsai2-1/+71
The A23 has an almost identical PRCM clock tree. The difference in the APB0 clock is the smallest divisor is 1, instead of 2. This patch adds a separate sun8i-a23-apb0-clk driver to support it. Signed-off-by: Chen-Yu Tsai <[email protected]> Signed-off-by: Maxime Ripard <[email protected]>
2014-07-04clk: sunxi: Add A23 clocks supportChen-Yu Tsai1-0/+101
The clock control unit on the A23 is similar to the one found on the A31. The AHB1, APB1, APB2 gates on the A23 are almost identical to the ones on the A31, but some outputs are missing. The main CPU PLL (PLL1) however is like that on older Allwinner SoCs, such as the A10 or A20, but the N factor starts from 1 instead of 0. This patch adds support for PLL1 and all the basic clock muxes and gates. Signed-off-by: Chen-Yu Tsai <[email protected]> Acked-by: Maxime Ripard <[email protected]> Signed-off-by: Maxime Ripard <[email protected]>
2014-07-04clk: sunxi: Add support for table-based divider clocksChen-Yu Tsai1-4/+5
A few of the clock modules have odd dividers, such as the 2 lowest dividers being the same (2), or have the same divider when the highest bit is set. This patch adds support for optional divider tables, so the clock framework will know about the odd values. Signed-off-by: Chen-Yu Tsai <[email protected]> Acked-by: Maxime Ripard <[email protected]> Signed-off-by: Maxime Ripard <[email protected]>
2014-07-04clk: sunxi: Support factor clocks with N factor starting not from 0Chen-Yu Tsai2-1/+2
The PLLs on newer Allwinner SoC's, such as the A31 and A23, have a N multiplier factor that starts from 1, not 0. This patch adds an option to the factor clk driver's config data structures to specify the base value of N. Signed-off-by: Chen-Yu Tsai <[email protected]> Acked-by: Maxime Ripard <[email protected]> Signed-off-by: Maxime Ripard <[email protected]>
2014-07-04clk: sunxi: move "ahb_sdram" to protected clock listChen-Yu Tsai1-5/+3
With sunxi_gates clocks registered with clkdev, we can use the protected clocks list to enable the "ahb_sdram" clock, instead of looking for it and adding CLK_IGNORE_UNUSED inline in the clock setup code. Signed-off-by: Chen-Yu Tsai <[email protected]> Acked-by: Maxime Ripard <[email protected]> Signed-off-by: Maxime Ripard <[email protected]>
2014-07-04clk: sunxi: register clock gates with clkdevChen-Yu Tsai1-0/+1
The new important clock protect code requires the clocks be registered with clkdev. This was missing for sunxi_gates type clocks. Signed-off-by: Chen-Yu Tsai <[email protected]> Acked-by: Maxime Ripard <[email protected]> Signed-off-by: Maxime Ripard <[email protected]>
2014-07-03Merge branch 'clk-fixes' into clk-nextMike Turquette11-62/+82
2014-07-02clk: qcom: HDMI source sel is 3 not 2Stephen Boyd1-1/+1
The HDMI PLL input to the tv mux is supposed to be 3, not 2. Fix the code so that we can properly select the HDMI PLL. Fixes: 6d00b56fe "clk: qcom: Add support for MSM8960's multimedia clock controller (MMCC)" Reported-by: Rob Clark <[email protected]> Signed-off-by: Stephen Boyd <[email protected]> Signed-off-by: Mike Turquette <[email protected]>
2014-07-02clk: define and export clk_debugs_add_filePeter De Schrijver1-0/+12
Define and export a new function clk_debugs_add_file which adds a file to a existing clock's debugfs directory. This can be used by clock providers to add debugfs entries which are not related to a specific clock type. Examples include the ability to measure the rate of a clock. It can also be used by modules to create new debugfs entries. This is useful if you want to expose features for testing which can potentially cause system instability such as allowing to change a clock's rate from userspace. Signed-off-by: Peter De Schrijver <[email protected]> Signed-off-by: Mike Turquette <[email protected]>
2014-07-02Merge tag 'for_3.16/samsung-clk-fixes' of ↵Mike Turquette5-47/+71
git://git.kernel.org/pub/scm/linux/kernel/git/tfiga/samsung-clk into clk-fixes-samsung Samsung clock fixes for v3.16. This pull request contains fixes for various issues found while testing -rc versions of Linux 3.16. Mostly two kinds of patches: * Fixes of incorrectly defined clocks 1) a37c82a clk: samsung: exynos4: Remove SRC_MASK_ISP gates Issue present since v3.10. 2) 0b1643b clk/exynos5250: fix bit number for tv sysmmu clock Issue present since v3.16. 3) 44ff025 clk: exynos5420: Remove aclk66_peric from the clock tree description Issue present since v3.11. * Adding things missed by original patches 1) cec1cde clk: samsung: fix several typos to fix boot on s3c2410 2) 34ece9e clk: samsung: add more aliases for s3c24xx Both issues present since the driver was added in v3.16. 3) a92dda4 clk: s3c64xx: Hookup SPI clocks correctly Issue present since v3.12.
2014-07-02clk: s2mps11: Fix clk_opsKarol Wrona1-22/+11
s2mps11 clocks had registered callbacks for prepare ,unprepare and is_enabled. During disabling unused clocks the lack of is_prepared caused that unused s2mps11 clocks were not unprepared and stayed active. Regmap_read is cached so it can be called in is_prepare callback to achieve this information. Enabled field was removed from struct s2mps11_clk. Signed-off-by: Karol Wrona <[email protected]> Signed-off-by: Mike Turquette <[email protected]>
2014-07-02clk: at91: main: warn when the main crystal frequency is not setAlexandre Belloni1-0/+1
When the main crystal frequency is not set, the main clock is approximated using the MAINF value in the CKGR_MCFR register. Warn the user in that case. Signed-off-by: Alexandre Belloni <[email protected]> Acked-by: Boris BREZILLON <[email protected]> Signed-off-by: Mike Turquette <[email protected]>
2014-07-02CLK: ti: dra7: Initialize USB_DPLLRoger Quadros1-0/+11
USB_DPLL must be initialized and locked at boot so that USB modules can work. Also program USB_DLL_M2 output to half rate. CC: Mike Turquette <[email protected]> CC: Tero Kristo <[email protected]> Signed-off-by: Roger Quadros <[email protected]> Signed-off-by: Tero Kristo <[email protected]>
2014-07-01Merge branch 'for-v3.16-rc/ti-clk-drv' of github.com:t-kristo/linux-pm into ↵Mike Turquette2-6/+4
clk-fixes-ti
2014-07-01clk: sunxi: fix devm_ioremap_resource error detection codeHimangi Saraogi1-1/+1
devm_ioremap_resource returns an ERR_PTR value, not NULL, on failure. A simplified version of the semantic match that finds this problem is as follows: // <smpl> @@ expression e,e1; statement S; @@ *e = devm_ioremap_resource(...); if (!e1) S // </smpl> Signed-off-by: Himangi Saraogi <[email protected]> Acked-by: Julia Lawall <[email protected]> Acked-by Boris BREZILLON <[email protected]> Signed-off-by: Mike Turquette <[email protected]>
2014-07-01clk: s2mps11: Fix double free corruption during driver unbindKrzysztof Kozlowski1-5/+2
After unbinding the driver memory was corrupted by double free of clk_lookup structure. This lead to OOPS when re-binding the driver again. The driver allocated memory for 'clk_lookup' with devm_kzalloc. During driver removal this memory was freed twice: once by clkdev_drop() and second by devm code. Kernel panic log: [ 30.839284] Unable to handle kernel paging request at virtual address 5f343173 [ 30.846476] pgd = dee14000 [ 30.849165] [5f343173] *pgd=00000000 [ 30.852703] Internal error: Oops: 805 [#1] PREEMPT SMP ARM [ 30.858166] Modules linked in: [ 30.861208] CPU: 0 PID: 1 Comm: bash Not tainted 3.16.0-rc2-00239-g94bdf617b07e-dirty #40 [ 30.869364] task: df478000 ti: df480000 task.ti: df480000 [ 30.874752] PC is at clkdev_add+0x2c/0x38 [ 30.878738] LR is at clkdev_add+0x18/0x38 [ 30.882732] pc : [<c0350908>] lr : [<c03508f4>] psr: 60000013 [ 30.882732] sp : df481e78 ip : 00000001 fp : c0700ed8 [ 30.894187] r10: 0000000c r9 : 00000000 r8 : c07b0e3c [ 30.899396] r7 : 00000002 r6 : df45f9d0 r5 : df421390 r4 : c0700d6c [ 30.905906] r3 : 5f343173 r2 : c0700d84 r1 : 60000013 r0 : c0700d6c [ 30.912417] Flags: nZCv IRQs on FIQs on Mode SVC_32 ISA ARM Segment user [ 30.919534] Control: 10c53c7d Table: 5ee1406a DAC: 00000015 [ 30.925262] Process bash (pid: 1, stack limit = 0xdf480240) [ 30.930817] Stack: (0xdf481e78 to 0xdf482000) [ 30.935159] 1e60: 00001000 df6de610 [ 30.943321] 1e80: df7f4558 c0355650 c05ec6ec c0700eb0 df6de600 df7f4510 dec9d69c 00000014 [ 30.951480] 1ea0: 00167b48 df6de610 c0700e30 c0713518 00000000 c0700e30 dec9d69c 00000006 [ 30.959639] 1ec0: 00167b48 c02c1b7c c02c1b64 df6de610 c07aff48 c02c0420 c06fb150 c047cc20 [ 30.967798] 1ee0: df6de610 df6de610 c0700e30 df6de644 c06fb150 0000000c dec9d690 c02bef90 [ 30.975957] 1f00: dec9c6c0 dece4c00 df481f80 dece4c00 0000000c c02be73c 0000000c c016ca8c [ 30.984116] 1f20: c016ca48 00000000 00000000 c016c1f4 00000000 00000000 b6f18000 df481f80 [ 30.992276] 1f40: df7f66c0 0000000c df480000 df480000 b6f18000 c011094c df47839c 60000013 [ 31.000435] 1f60: 00000000 00000000 df7f66c0 df7f66c0 0000000c df480000 b6f18000 c0110dd4 [ 31.008594] 1f80: 00000000 00000000 0000000c b6ec05d8 0000000c b6f18000 00000004 c000f2a8 [ 31.016753] 1fa0: 00001000 c000f0e0 b6ec05d8 0000000c 00000001 b6f18000 0000000c 00000000 [ 31.024912] 1fc0: b6ec05d8 0000000c b6f18000 00000004 0000000c 00000001 00000000 00167b48 [ 31.033071] 1fe0: 00000000 bed83a80 b6e004f0 b6e5122c 60000010 00000001 ffffffff ffffffff [ 31.041248] [<c0350908>] (clkdev_add) from [<c0355650>] (s2mps11_clk_probe+0x2b4/0x3b4) [ 31.049223] [<c0355650>] (s2mps11_clk_probe) from [<c02c1b7c>] (platform_drv_probe+0x18/0x48) [ 31.057728] [<c02c1b7c>] (platform_drv_probe) from [<c02c0420>] (driver_probe_device+0x13c/0x384) [ 31.066579] [<c02c0420>] (driver_probe_device) from [<c02bef90>] (bind_store+0x88/0xd8) [ 31.074564] [<c02bef90>] (bind_store) from [<c02be73c>] (drv_attr_store+0x20/0x2c) [ 31.082118] [<c02be73c>] (drv_attr_store) from [<c016ca8c>] (sysfs_kf_write+0x44/0x48) [ 31.090016] [<c016ca8c>] (sysfs_kf_write) from [<c016c1f4>] (kernfs_fop_write+0xc0/0x17c) [ 31.098176] [<c016c1f4>] (kernfs_fop_write) from [<c011094c>] (vfs_write+0xa0/0x1c4) [ 31.105899] [<c011094c>] (vfs_write) from [<c0110dd4>] (SyS_write+0x40/0x8c) [ 31.112931] [<c0110dd4>] (SyS_write) from [<c000f0e0>] (ret_fast_syscall+0x0/0x3c) [ 31.120481] Code: e2842018 e584501c e1a00004 e885000c (e5835000) [ 31.126596] ---[ end trace efad45bfa3a61b05 ]--- [ 31.131181] Kernel panic - not syncing: Fatal exception [ 31.136368] CPU1: stopping [ 31.139054] CPU: 1 PID: 0 Comm: swapper/1 Tainted: G D 3.16.0-rc2-00239-g94bdf617b07e-dirty #40 [ 31.148697] [<c0016480>] (unwind_backtrace) from [<c0012950>] (show_stack+0x10/0x14) [ 31.156419] [<c0012950>] (show_stack) from [<c0480db8>] (dump_stack+0x80/0xcc) [ 31.163622] [<c0480db8>] (dump_stack) from [<c001499c>] (handle_IPI+0x130/0x15c) [ 31.170998] [<c001499c>] (handle_IPI) from [<c000862c>] (gic_handle_irq+0x60/0x68) [ 31.178549] [<c000862c>] (gic_handle_irq) from [<c0013480>] (__irq_svc+0x40/0x70) [ 31.186009] Exception stack(0xdf4bdf88 to 0xdf4bdfd0) [ 31.191046] df80: ffffffed 00000000 00000000 00000000 df4bc000 c06d042c [ 31.199207] dfa0: 00000000 ffffffed c06d03c0 00000000 c070c288 00000000 00000000 df4bdfd0 [ 31.207363] dfc0: c0010324 c0010328 60000013 ffffffff [ 31.212402] [<c0013480>] (__irq_svc) from [<c0010328>] (arch_cpu_idle+0x28/0x30) [ 31.219783] [<c0010328>] (arch_cpu_idle) from [<c005f150>] (cpu_startup_entry+0x2c4/0x3f0) [ 31.228027] [<c005f150>] (cpu_startup_entry) from [<400086c4>] (0x400086c4) [ 31.234968] ---[ end Kernel panic - not syncing: Fatal exception Fixes: 7cc560dea415 ("clk: s2mps11: Add support for s2mps11") Cc: <[email protected]> Signed-off-by: Krzysztof Kozlowski <[email protected]> Reviewed-by: Yadwinder Singh Brar <[email protected]> Signed-off-by: Mike Turquette <[email protected]>
2014-07-01clk: Add driver for Palmas clk32kg and clk32kgaudio clocksPeter Ujfalusi3-0/+315
Palmas class of devices can provide 32K clock(s) to be used by other devices on the board. Depending on the actual device the provided clocks can be: CLK32K_KG and CLK32K_KGAUDIO or only one: CLK32K_KG (TPS659039 for example) Use separate compatible flags for the two 32K clock. A system which needs or have only one of the 32k clock from Palmas will need to add node(s) for each clock as separate section in the dts file. The two compatible property is: "ti,palmas-clk32kg" for clk32kg clock "ti,palmas-clk32kgaudio" for clk32kgaudio clock Apart from the register control of the clocks - which is done via the clock API there is a posibility to enable the external sleep control. In this way the clock can be enabled/disabled on demand by the user of the clock. See the documentation for more details. Signed-off-by: Peter Ujfalusi <[email protected]> Reviewed-by: Nishanth Menon <[email protected]> Signed-off-by: Mike Turquette <[email protected]>
2014-07-01clk: ti: am43x: Fix boot with CONFIG_SOC_AM33XX disabledRoger Quadros1-2/+3
Define ti_clk_register_dpll_x2() and of_ti_am3_dpll_x2_setup() if AM43XX is defined. Fixes the below boot issue. [ 2.157258] gpmc_l3_clk not enabled [ 2.161194] gpmc_l3_clk not enabled [ 2.164896] Division by zero in kernel. [ 2.169055] CPU: 0 PID: 321 Comm: kworker/u2:2 Tainted: G W 3.16.0-rc1-00008-g4c0e520 #273 [ 2.178880] Workqueue: deferwq deferred_probe_work_func [ 2.184459] [<c001477c>] (unwind_backtrace) from [<c001187c>] (show_stack+0x10/0x14) [ 2.192752] [<c001187c>] (show_stack) from [<c0530f28>] (dump_stack+0x80/0x9c) [ 2.200486] [<c0530f28>] (dump_stack) from [<c02c867c>] (Ldiv0+0x8/0x10) [ 2.207678] [<c02c867c>] (Ldiv0) from [<c0022da0>] (gpmc_calc_divider+0x24/0x40) [ 2.215490] [<c0022da0>] (gpmc_calc_divider) from [<c0022e20>] (gpmc_cs_set_timings+0x18/0x474) [ 2.224783] [<c0022e20>] (gpmc_cs_set_timings) from [<c003069c>] (gpmc_nand_init+0x74/0x1a8) [ 2.233791] [<c003069c>] (gpmc_nand_init) from [<c0024668>] (gpmc_probe+0x52c/0x874) [ 2.242089] [<c0024668>] (gpmc_probe) from [<c0349218>] (platform_drv_probe+0x18/0x48) [ 2.250534] [<c0349218>] (platform_drv_probe) from [<c0347d88>] (driver_probe_device+0x104/0x22c) [ 2.259988] [<c0347d88>] (driver_probe_device) from [<c03464dc>] (bus_for_each_drv+0x44/0x8c) [ 2.269087] [<c03464dc>] (bus_for_each_drv) from [<c0347c4c>] (device_attach+0x74/0x8c) [ 2.277620] [<c0347c4c>] (device_attach) from [<c0347380>] (bus_probe_device+0x88/0xb0) [ 2.286074] [<c0347380>] (bus_probe_device) from [<c0347768>] (deferred_probe_work_func+0x60/0x90) [ 2.295611] [<c0347768>] (deferred_probe_work_func) from [<c004ef50>] (process_one_work+0x1b4/0x4bc) [ 2.305288] [<c004ef50>] (process_one_work) from [<c004f3d4>] (worker_thread+0x148/0x550) [ 2.313954] [<c004f3d4>] (worker_thread) from [<c0055a48>] (kthread+0xc8/0xe4) [ 2.321628] [<c0055a48>] (kthread) from [<c000e648>] (ret_from_fork+0x14/0x2c) Signed-off-by: Roger Quadros <[email protected]> Signed-off-by: Mike Turquette <[email protected]>
2014-07-01clk: Fix build warningsSachin Kamat1-11/+11
‘all_lists’ and ‘orphan_list’ is accessed only when DEBUG_FS is defined. Thus, make their compilation conditional to fix the below warnings introduced by commit 27b8d5f723 ("clk: flatten clk tree in debugfs"): drivers/clk/clk.c:40:27: warning: ‘all_lists’ defined but not used [-Wunused-variable] drivers/clk/clk.c:46:27: warning: ‘orphan_list’ defined but not used [-Wunused-variable] Signed-off-by: Sachin Kamat <[email protected]> Cc: Peter De Schrijver <[email protected]> Signed-off-by: Mike Turquette <[email protected]>
2014-07-01clk: ppc-corenet: Fix Section mismatch warningJingchang Lu1-1/+1
WARNING: drivers/built-in.o(.data+0x10258): Section mismatch in reference from the variable ppc_corenet_clk_driver to the (unknown reference) .init.rodata:(unknown) The variable ppc_corenet_clk_driver references the (unknown reference) __initconst (unknown) If the reference is valid then annotate the variable with __init* or __refdata (see linux/init.h) or name the variable: *_template, *_timer, *_sht, *_ops, *_probe, *_probe_one, *_console Signed-off-by: Jingchang Lu <[email protected]> Signed-off-by: Mike Turquette <[email protected]>
2014-06-30clk: tegra: export clock names for debuggingPeter De Schrijver1-0/+6
When writing a module for testing or debugging purposes, there is no way to get hold of clk handles. This patch solves this by exposing all valid clocks as clkdev's for the virtual device tegra-clk-debug. Signed-off-by: Peter De Schrijver <[email protected]>
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