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2014-04-30clk: socfpga: fix clock driver for 3.15Dinh Nguyen2-20/+10
commit [1771b10d6 clk: respect the clock dependencies in of_clk_init] exposed a flaw in the socfpga clock driver and prevents the platform from booting on 3.15-rc1. Because the "altr,clk-mgr" is not really a clock, it should not be using CLK_OF_DECLARE, instead we should be mapping the clk-mgr's base address one of the functional clock init function. Use the socfpga_pll_init function to map the clk_mgr_base_addr as this clock should always be initialized first. Signed-off-by: Dinh Nguyen <[email protected]> Tested-by: Pavel Machek <[email protected]>
2014-03-18clk: socfpga: Fix section mismatch warningDinh Nguyen1-1/+1
WARNING: drivers/clk/socfpga/built-in.o(.data+0xc0): Section mismatch in reference from the variable socfpga_child_clocks to the function .init.text:socfpga_pll_init() The variable socfpga_child_clocks references the function __init socfpga_pll_init() If the reference is valid then annotate the variable with __init* or __refdata (see linux/init.h) or name the variable: *_template, *_timer, *_sht, *_ops, *_probe, *_probe_one, *_console WARNING: drivers/clk/socfpga/built-in.o(.data+0x184): Section mismatch in reference from the variable socfpga_child_clocks to the function .init.text:socfpga_periph_init() The variable socfpga_child_clocks references the function __init socfpga_periph_init() If the reference is valid then annotate the variable with __init* or __refdata (see linux/init.h) or name the variable: *_template, *_timer, *_sht, *_ops, *_probe, *_probe_one, *_console WARNING: drivers/clk/socfpga/built-in.o(.data+0x248): Section mismatch in reference from the variable socfpga_child_clocks to the function .init.text:socfpga_gate_init() The variable socfpga_child_clocks references the function __init socfpga_gate_init() If the reference is valid then annotate the variable with __init* or __refdata (see linux/init.h) or name the variable: *_template, *_timer, *_sht, *_ops, *_probe, *_probe_one, *_console Reported-by: Mike Turquette <[email protected]> Signed-off-by: Dinh Nguyen <[email protected]> Signed-off-by: Mike Turquette <[email protected]>
2014-02-26clk: socfpga: Support multiple parents for the pll clocksDinh Nguyen1-4/+22
The PLLs can be from 3 different sources: osc1, osc2, or the f2s_ref_clk. Update the clock driver to be able to get the correct parent. Signed-off-by: Dinh Nguyen <[email protected]> Cc: Steffen Trumtrar <[email protected]> Signed-off-by: Mike Turquette <[email protected]>
2014-02-26clk: socfpga: Fix integer overflow in clock calculationDinh Nguyen1-3/+5
Use 64-bit integer for calculating clock rate. Also use do_div for the 64-bit division. Signed-off-by: Graham Moore <[email protected]> Signed-off-by: Dinh Nguyen <[email protected]> Cc: Steffen Trumtrar <[email protected]> Signed-off-by: Mike Turquette <[email protected]>
2014-02-18clk: socfpga: Add a clk-phase property to the "altr,socfpga-gate-clk"Dinh Nguyen1-0/+68
The clk-phase property is used to represent the 2 clock phase values that is needed for the SD/MMC driver. Add a prepare function to the clk_ops, that will use the syscon driver to set sdmmc_clk's phase shift that is located in the system manager. Signed-off-by: Dinh Nguyen <[email protected]> Acked-by: Zhangfei Gao <[email protected]> Acked-by: Jaehoon Chung <[email protected]> --- v9: none v8: Use degrees in the clk-phase binding property v7: Add dts property to represent the clk phase of the sdmmc_clk. Add a prepare function to the gate clk that will toggle clock phase setting. Remove the "altr,socfpga-sdmmc-sdr-clk" clock type. v6: Add a new clock type "altr,socfpga-sdmmc-sdr-clk" that will be used to set the phase shift settings. v5: Use the "snps,dw-mshc" binding v4: Use the sdmmc_clk prepare function to set the phase shift settings v3: Not use the syscon driver because as of 3.13-rc1, the syscon driver is loaded after the clock driver. v2: Use the syscon driver
2014-02-18clk: socfpga: split clk codeSteffen Trumtrar6-306/+462
Move the different kinds of clocks into their own files. The reason is to aid readability of the code. This also goes along with the other SoC-specific clock drivers. The split introduces new structs for the three types of clocks and uses them. Other changes are not done to the code. Signed-off-by: Steffen Trumtrar <[email protected]> Signed-off-by: Dinh Nguyen <[email protected]>
2014-02-18clk: socfpga: fix define typoSteffen Trumtrar1-3/+3
It should be SOCFPGA instead of SOCFGPA. Signed-off-by: Steffen Trumtrar <[email protected]> Signed-off-by: Dinh Nguyen <[email protected]>
2014-02-18clk: socfpga: remove unused fieldSteffen Trumtrar1-1/+0
The clk_name field from the socfpga_clk struct is unused. Remove it. Signed-off-by: Steffen Trumtrar <[email protected]> Signed-off-by: Dinh Nguyen <[email protected]>
2014-02-18clk: socfpga: Remove socfpga_init_clocksDinh Nguyen1-10/+0
The only thing that socfpga_init_clocks was doing is setting up the smp_twd clk. Now that twd-timer's clock phandle is populated in the DTS, we can remove this function. Signed-off-by: Dinh Nguyen <[email protected]> Acked-by: Arnd Bergmann <[email protected]>
2014-02-18clk: socfpga: Look for the GPIO_DB_CLK by its offsetDinh Nguyen1-2/+3
After the patch: "clk: socfpga: Map the clk manager base address in the clock driver" The clk->name field in socfpga_clk_recalc_rate() was getting cleared. Replace looking for the GPIO_DB_CLK by its divider offset instead. Also rename the define SOCFPGA_DB_CLK_OFFSET -> SOCFPGA_GPIO_DB_CLK_OFFSET, as this represents the GPIO_DB_CLK. Signed-off-by: Dinh Nguyen <[email protected]>
2014-02-18clk: socfpga: Map the clk manager base address in the clock driverDinh Nguyen1-4/+16
The clk manager's base address was being mapped in SOCFPGA's arch code and being extern'ed out to the clock driver. This method is not correct, and the arch code was not really doing anything with that clk manager anyways. This patch moves the mapping of the clk manager's base address in the clock driver itself. Cleans up CLK_OF_DECLARE() into a single registration of all the clocks. Suggested-by: Arnd Bergmann <[email protected]> Signed-off-by: Dinh Nguyen <[email protected]> Acked-by: Arnd Bergmann <[email protected]> --- v2: Use a static declaration for the clk_mgr_base_addr. Clean up the CLK_OF_DECLARE() as suggested by Arnd.
2013-12-19clk: socfpga: Use NULL instead of 0Sachin Kamat1-1/+1
'div_reg' is a pointer. Assign NULL instead of 0. Signed-off-by: Sachin Kamat <[email protected]> Acked-by: Dinh Nguyen <[email protected]> Signed-off-by: Mike Turquette <[email protected]>
2013-11-27clk: socfpga: Remove check for "reg" property in socfpga_clk_initDinh Nguyen1-3/+1
The function socfpga_clk_init() can support clocks that do not have a divider register, but a fixed-divider that can be read from DTS. Therefore, the "reg" property is not a failing condition for socfpga_clk_init(). Signed-off-by: Dinh Nguyen <[email protected]> Signed-off-by: Mike Turquette <[email protected]>
2013-10-07clk: socfpga: Fix incorrect sdmmc clock nameDinh Nguyen1-1/+1
The SD/MMC clock is named "sdmmc_clk", and NOT "mmc_clk". Because of this, the SD driver was getting the incorrect clock value. This prevented the SD driver from initializing correctly. Signed-off-by: Dinh Nguyen <[email protected]> CC: Arnd Bergmann <[email protected]> CC: Olof Johansson <[email protected]> Reviewed-by: Pavel Machek <[email protected]> Cc: [email protected] Signed-off-by: Mike Turquette <[email protected]>
2013-06-11ARM: socfpga: Add support to gate peripheral clocksDinh Nguyen1-9/+185
Add support to gate the clocks that directly feed peripherals. For clocks with multiple parents, add the ability to determine the correct parent, and also set parents. Also add support to calculate and set the clocks' rate. Signed-off-by: Dinh Nguyen <[email protected]> Reviewed-by: Pavel Machek <[email protected]> Acked-by: Mike Turquette <[email protected]> Cc: Mike Turquette <[email protected]> CC: Arnd Bergmann <[email protected]> CC: Olof Johansson <[email protected]> Cc: Pavel Machek <[email protected]> CC: <[email protected]> v4: - Add Acked-by: Mike Turquette v3: - Addressed comments from Pavel v2: - Fix space/indent errors - Add streq for strcmp == 0 Signed-off-by: Olof Johansson <[email protected]>
2013-04-14ARM: socfpga: Upgrade clk driver for socfpga to make use of dts clock entriesDinh Nguyen1-21/+142
With this patch, the socfpga clk driver is able to query the clock and clock rates appropriately. Signed-off-by: Dinh Nguyen <[email protected]> Reviewed-by: Pavel Machek <[email protected]> Signed-off-by: Olof Johansson <[email protected]>
2012-07-19ARM: socfpga: initial support for Altera's SOCFPGA platformDinh Nguyen2-0/+52
Adding core definitions for Altera's SOCFPGA ARM platform. Mininum support for Altera's SOCFPGA Cyclone 5 hardware. Signed-off-by: Dinh Nguyen <[email protected]> Reviewed-by: Pavel Machek <[email protected]> Reviewed-by: Rob Herring <[email protected]> Reviewed-by: Thomas Petazzoni <[email protected]> Signed-off-by: Arnd Bergmann <[email protected]>
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