| Age | Commit message (Collapse) | Author | Files | Lines |
|---|
|
The debug base clock can be bypassed from the main PLL to the OSC1 clock.
The bypass register is the staysoc1(0x10) register that is in the clock
manager.
This patch adds the option to get the correct parent for the debug base
clock.
Signed-off-by: Dinh Nguyen <[email protected]>
Signed-off-by: Stephen Boyd <[email protected]>
|
|
Convert the code to use GENMASK() helper instead of div_mask() macro.
Signed-off-by: Andy Shevchenko <[email protected]>
Acked-by: Dinh Nguyen <[email protected]>
Signed-off-by: Stephen Boyd <[email protected]>
|
|
Clock provider drivers generally shouldn't include clk.h because
it's the consumer API. Remove the include here because this is a
provider driver. The clkdev.h include isn't used either, remove
it and add in slab.h to make sure things keep compiling.
Acked-by: Dinh Nguyen <[email protected]>
Signed-off-by: Stephen Boyd <[email protected]>
|
|
drivers/clk/socfpga/clk-periph.c:79:39: warning: Using plain integer as NULL pointer
Cc: Dinh Nguyen <[email protected]>
Signed-off-by: Stephen Boyd <[email protected]>
|
|
The C0(mpu_clk), C1(main_clk), and C2(dbg_base_clk) outputs from the main
PLL go through a pre-divider before coming into the system. These registers
were hidden for the CycloneV platform, but are now used for the ArriaV
platform.
This patch updates the clock driver to read the div-reg property for the
socfpga-periph-clk clocks. Also moves the div_mask define to clk.h for re-use.
Signed-off-by: Dinh Nguyen <[email protected]>
|
|
Move the different kinds of clocks into their own files. The reason is to aid
readability of the code. This also goes along with the other SoC-specific
clock drivers.
The split introduces new structs for the three types of clocks and uses them.
Other changes are not done to the code.
Signed-off-by: Steffen Trumtrar <[email protected]>
Signed-off-by: Dinh Nguyen <[email protected]>
|