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2019-12-11clk: imx: pllv2: Switch to clk_hw based APIAbel Vesa2-6/+13
Switch the imx_clk_pllv2 register function to clk_hw based API, rename accordingly and add a macro for clk based legacy. This allows us to move closer to a clear split between consumer and provider clk APIs. Signed-off-by: Abel Vesa <[email protected]> Reviewed-by: Peng Fan <[email protected]> Signed-off-by: Shawn Guo <[email protected]>
2019-12-11clk: imx: pllv1: Switch to clk_hw based APIAbel Vesa2-6/+13
Switch the imx_clk_pllv1 register function to clk_hw based API, rename accordingly and add a macro for clk based legacy. This allows us to move closer to a clear split between consumer and provider clk APIs. Signed-off-by: Abel Vesa <[email protected]> Reviewed-by: Peng Fan <[email protected]> Signed-off-by: Shawn Guo <[email protected]>
2019-12-11clk: imx: Replace all the clk based helpers with macrosAbel Vesa1-27/+12
Replacing with macros all the clk based API helpers we reduce the code duplication. The end goal is to get rid of all these macros when there will be no more users of the clk based API, that is, when all the i.MX clock provider drivers will be switched completely to the clk_hw based API. This is another step in moving away from the non clk_hw based API usage throughout the i.MX clock drivers. The reason for doing that is to have a clear split between the clock provider and the clock consumer API. Signed-off-by: Abel Vesa <[email protected]> Reviewed-by: Peng Fan <[email protected]> Signed-off-by: Shawn Guo <[email protected]>
2019-12-11clk: imx: Rename the SCCG to SSCGAbel Vesa4-81/+81
According to the manual the acronym stands for Spread Sprectum Clock Generator. Signed-off-by: Abel Vesa <[email protected]> Signed-off-by: Shawn Guo <[email protected]>
2019-12-11clk: imx: Add correct failure handling for clk based helpersAbel Vesa1-15/+22
If the clk_hw based API returns an error, trying to return the clk from hw will end up in a NULL pointer dereference. So adding the to_clk checker and using it inside every clk based macro helper we handle that case correctly. This to_clk is also temporary and will go away along with the clk based macro helpers once there is no user that need them anymore. Signed-off-by: Abel Vesa <[email protected]> Signed-off-by: Shawn Guo <[email protected]>
2019-12-11clk: imx8qxp-lpcg: Warn against devm_platform_ioremap_resourceLeonard Crestez1-0/+11
On imx8 the LPCG nodes map entire subsystems and overlap peripherals, this means that using devm_platform_ioremap_resource will cause many devices to fail to probe including serial ports. Well-meaning but boot-breaking patches were posted multiple times so add a comment explaining this issue. Suggested-by: Peng Fan <[email protected]> Signed-off-by: Leonard Crestez <[email protected]> Reviewed-by: Peng Fan <[email protected]> Signed-off-by: Shawn Guo <[email protected]>
2019-12-11clk: imx: pll14xx: fix clk_pll14xx_wait_lockPeng Fan1-1/+1
The usage of readl_poll_timeout is wrong, the 3rd parameter(cond) should be "val & LOCK_STATUS" not "val & LOCK_TIMEOUT_US", It is not check whether the pll locked, LOCK_STATUS reflects the mask, not LOCK_TIMEOUT_US. Fixes: 8646d4dcc7fb ("clk: imx: Add PLLs driver for imx8mm soc") Cc: <[email protected]> Reviewed-by: Abel Vesa <[email protected]> Signed-off-by: Peng Fan <[email protected]> Signed-off-by: Shawn Guo <[email protected]>
2019-12-11clk: imx8mn: correct the usb1_ctrl parent to be usb_busLi Jun1-1/+1
Per latest imx8mn datasheet of CCM, the parent of usb1_ctrl_root_clk should be usb_bus. Signed-off-by: Li Jun <[email protected]> Signed-off-by: Shawn Guo <[email protected]>
2019-12-09clk: imx: clk-imx7ulp: Add missing sentinel of ulp_div_tablePeng Fan1-0/+1
There should be a sentinel of ulp_div_table, otherwise _get_table_div may access data out of the array. Fixes: b1260067ac3d ("clk: imx: add imx7ulp clk driver") Signed-off-by: Peng Fan <[email protected]> Cc: <[email protected]> Signed-off-by: Shawn Guo <[email protected]>
2019-12-09clk: imx8m: Suppress bind attrsLeonard Crestez3-0/+15
The clock drivers on imx8m series are registered as platform devices and this opens the possibility of reloading the driver at runtime. This doesn't actually work: clocks are never removed and attempting to bind again results in registration errors and a crash. Almost all devices depend on clocks anyway so rebinding is unlikely to ever be useful Fix this by explicitly suppressing bind attrs like several other clock drivers. Signed-off-by: Leonard Crestez <[email protected]> Reviewed-by: Peng Fan <[email protected]> Signed-off-by: Shawn Guo <[email protected]>
2019-12-09clk: imx7ulp: Fix watchdog2 clock name typoFabio Estevam1-1/+1
There is a typo in the watchdog2 clock name. Fix it by changing it to "wdg2". Signed-off-by: Fabio Estevam <[email protected]> Reviewed-by: Abel Vesa <[email protected]> Signed-off-by: Shawn Guo <[email protected]>
2019-12-09clk: imx6q: disable non functional dividerJan Remmet1-1/+4
The /2 divider between pll4_audio_div and pll4_post_div is not working on imx6q. The frequency is not halved as reported by the clock tree and measured on clko. In the technical reference manual the divider was removed in revision 4. It's also not listed in the imx6qp manual. imx6dl manual mentions a divider for PLL4 and the according register description. So keep the divider here. Signed-off-by: Jan Remmet <[email protected]> Signed-off-by: Shawn Guo <[email protected]>
2019-12-09clk: imx: Mark dram pll on 8mm and 8mn with CLK_GET_RATE_NOCACHELeonard Crestez4-2/+10
DRAM frequency switches are executed in firmware and can change the configuration of the DRAM PLL outside linux. Mark these CLKs with CLK_GET_RATE_NOCACHE so we always read back the PLL config registers and recalculate rates. In current DRAM frequency tables on 8mm/8mn only the maximum frequency uses the PLL so it's always configured in the same way. However reading back the PLL configuration is the correct behavior and allows additional setpoints in the future. Signed-off-by: Leonard Crestez <[email protected]> Reviewed-by: Abel Vesa <[email protected]> Acked-by: Stephen Boyd <[email protected]> Signed-off-by: Shawn Guo <[email protected]>
2019-12-09clk: imx8m: Set CLK_GET_RATE_NOCACHE on dram clocksLeonard Crestez3-8/+23
These clocks are only modified as part of DRAM frequency switches during which DRAM itself is briefly inaccessible. The switch is performed with a SMC call to by TF-A which runs from a SRAM area; upon returning to linux several clocks bits are modified and we need to update them. For rate bits an easy solution is to just mark with CLK_GET_RATE_NOCACHE so that new rates are always read back from registers. Signed-off-by: Leonard Crestez <[email protected]> Reviewed-by: Abel Vesa <[email protected]> Acked-by: Stephen Boyd <[email protected]> Signed-off-by: Shawn Guo <[email protected]>
2019-12-09clk: imx: clk-composite-8m: add lock to gate/muxPeng Fan1-0/+2
There is a lock to divider in the composite driver, but that's not enough. lock to gate/mux are also needed to provide exclusive access to the register. Fixes: d3ff9728134e ("clk: imx: Add imx composite clock") Signed-off-by: Peng Fan <[email protected]> Cc: <[email protected]> Signed-off-by: Shawn Guo <[email protected]>
2019-12-09clk: imx: clk-divider-gate: drop redundant initializationPeng Fan1-4/+4
There is no need to initialize flags as 0. Signed-off-by: Peng Fan <[email protected]> Reviewed-by: Abel Vesa <[email protected]> Signed-off-by: Shawn Guo <[email protected]>
2019-12-09clk: imx: clk-divider-gate: fix a typo in commentPeng Fan1-1/+1
Fix a typo in comment: resue -> reuse. Signed-off-by: Peng Fan <[email protected]> Signed-off-by: Shawn Guo <[email protected]>
2019-12-01Merge tag 'clk-for-linus' of ↵Linus Torvalds10-301/+208
git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux Pull clk updates from Stephen Boyd: "This merge window we have one small clk provider API in the core framework and then a bunch of driver updates and a handful of new drivers. In terms of diffstat the Qualcomm and Amlogic drivers are high up there because of all the clk data introcued by new drivers. The Nvidia Tegra driver had a lot of work done this cycle too to support suspend/resume and memory controllers. And the OMAP clk driver got proper clk and reset handling in place. Rounding out the patches are various updates to remove unused data, mark things static, correct incorrect data in drivers, etc. All the little things that improve drivers and maintain code health. I will point out that there's a patch in here for the GPIO clk driver, that almost nobody uses, which changes behavior and causes clk_set_rate() to try to change the GPIO gate clk's parent. Other than that things are fairly well SoC specific here. Core: - Add a clk provider API to get current parent index - Plug a memory leak in clk_unregister() path New Drivers: - CGU in Ingenix X1000 - Bitmain BM1880 clks - Qualcomm MSM8998 GPU clk controllers - Qualcomm SC7180 GCC and RPMH clk controllers - Qualcomm QCS404 Q6SSTOP clk controllers - Add support for the Renesas R-Car M3-W+ (r8a77961) SoC - Add support for the Renesas RZ/G2N (r8a774b1) SoC - Add Tegra20/30 External Memory Clock (EMC) support Updates: - Make gpio gate clks propagate rate setting up to parent - Prepare Armada 3700 for suspend to RAM by moving PCIe suspend/resume priority - Drop unused variables, enums, etc. in various clk drivers - Convert various drivers to use devm_platform_ioremap_resource() - Use struct_size() some more in various clk drivers - Improve Rockchip px30 clk tree - Add suspend/resume support to Tegra210 clk driver - Reimplement SOR clks on earlier Tegra SoCs, helping HDMI and DP - Allwinner DT exports and H6 clk tree fixes - Proper clk and reset handling for OMAP SoCs - Revamped TI divider clk to clamp max divider - Make 1443X/1416X PLL clock structure common for reusing among i.MX8 SoCs - Drop IMX7ULP_CLK_MIPI_PLL clock, it shouldn't be used - Add VIDEO2_PLL clock for imx8mq - Add missing gate clock for pll1/2 fixed dividers on i.MX8 SoCs - Add sm1 support in the Amlogic audio clock controller - Switch some clocks on R-Car Gen2/3 to .determine_rate() - Remove Renesas R-Car Gen2 legacy DT clock support - Improve arithmetic divisions on Renesas R-Car Gen2 and Gen3 - Improve Renesas R-Car Gen3 SD clock handling - Add rate table for Samsung exynos542x GPU and VPLL clks - Fix potential CPU performance degradation after system suspend/resume cycle on exynos542x SoCs" * tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux: (160 commits) clk: aspeed: Add RMII RCLK gates for both AST2500 MACs MAINTAINERS: Add entry for BM1880 SoC clock driver clk: Add common clock driver for BM1880 SoC dt-bindings: clock: Add devicetree binding for BM1880 SoC clk: Add clk_hw_unregister_composite helper function definition clk: Zero init clk_init_data in helpers clk: ingenic: Allow drivers to be built with COMPILE_TEST MAINTAINERS: Update section for Ux500 clock drivers clk: mark clk_disable_unused() as __init clk: Fix memory leak in clk_unregister() clk: Ingenic: Add CGU driver for X1000. dt-bindings: clock: Add X1000 bindings. clk: tegra: Use match_string() helper to simplify the code clk: pxa: fix one of the pxa RTC clocks clk: sprd: Use IS_ERR() to validate the return value of syscon_regmap_lookup_by_phandle() clk: armada-xp: remove unused code clk: tegra: Fix build error without CONFIG_PM_SLEEP clk: tegra: Add missing stubs for the case of !CONFIG_PM_SLEEP clk: tegra: Optimize PLLX restore on Tegra20/30 clk: tegra: Add suspend and resume support on Tegra210 ...
2019-11-27Merge branches 'clk-hisi', 'clk-amlogic', 'clk-samsung', 'clk-renesas' and ↵Stephen Boyd10-287/+208
'clk-imx' into clk-next * clk-hisi: clk: hi6220: use CLK_OF_DECLARE_DRIVER * clk-amlogic: clk: meson: axg-audio: use devm_platform_ioremap_resource() to simplify code clk: meson: axg_audio: add sm1 support clk: meson: axg-audio: provide clk top signal name clk: meson: axg-audio: prepare sm1 addition clk: meson: axg-audio: fix regmap last register clk: meson: axg-audio: remove useless defines dt-bindings: clock: meson: add sm1 resets to the axg-audio controller dt-bindings: clk: axg-audio: add sm1 bindings clk: meson: g12a: set CLK_MUX_ROUND_CLOSEST on the cpu clock muxes clk: meson: g12a: fix cpu clock rate setting clk: meson: gxbb: let sar_adc_clk_div set the parent clock rate * clk-samsung: clk: samsung: exynos5420: Add SET_RATE_PARENT flag to clocks on G3D path clk: samsung: exynos5420: Preserve CPU clocks configuration during suspend/resume clk: samsung: exynos5420: Add VPLL rate table clk: samsung: exynos5420: Preserve PLL configuration during suspend/resume clk: samsung: exynos542x: Move G3D subsystem clocks to its sub-CMU clk: samsung: exynos5433: Fix error paths * clk-renesas: (23 commits) clk: renesas: r8a7796: Add R8A77961 CPG/MSSR support clk: renesas: Rename CLK_R8A7796 to CLK_R8A77960 dt-bindings: clock: renesas: cpg-mssr: Document r8a77961 support clk: renesas: r8a77965: Remove superfluous semicolon dt-bindings: clock: renesas: rcar-usb2-clock-sel: Fix typo in example dt-bindings: clock: renesas: Remove R-Car Gen2 legacy DT bindings dt-bindings: clock: Add r8a77961 CPG Core Clock Definitions dt-bindings: power: Add r8a77961 SYSC power domain definitions clk: renesas: rcar-gen3: Switch SD clocks to .determine_rate() clk: renesas: rcar-gen3: Switch Z clocks to .determine_rate() clk: renesas: rcar-gen2: Switch Z clock to .determine_rate() clk: renesas: r8a774b1: Add TMU clock clk: renesas: cpg-mssr: Add r8a774b1 support dt-bindings: clock: renesas: cpg-mssr: Document r8a774b1 binding clk: renesas: rcar-gen3: Loop to find best rate in cpg_sd_clock_round_rate() clk: renesas: rcar-gen3: Absorb cpg_sd_clock_calc_div() clk: renesas: rcar-gen3: Avoid double table iteration in SD .set_rate() clk: renesas: rcar-gen3: Improve arithmetic divisions clk: renesas: rcar-gen2: Improve arithmetic divisions clk: renesas: Remove R-Car Gen2 legacy DT clock support ... * clk-imx: clk: imx: imx8mq: fix sys3_pll_out_sels clk: imx7ulp: do not export out IMX7ULP_CLK_MIPI_PLL clock clk: imx: imx6ul: use imx_obtain_fixed_clk_hw to simplify code clk: imx: imx6sx: use imx_obtain_fixed_clk_hw to simplify code clk: imx: imx6sll: use imx_obtain_fixed_clk_hw to simplify code clk: imx: imx7d: use imx_obtain_fixed_clk_hw to simplify code clk: imx7ulp: Correct DDR clock mux options clk: imx7ulp: Correct system clock source option #7 clk: imx: imx8mq: mark sys1/2_pll as fixed clock clk: imx: imx8mn: mark sys_pll1/2 as fixed clock clk: imx: imx8mm: mark sys_pll1/2 as fixed clock clk: imx8mn: Define gates for pll1/2 fixed dividers clk: imx8mm: Define gates for pll1/2 fixed dividers clk: imx8mq: Define gates for pll1/2 fixed dividers clk: imx: clk-pll14xx: Make two variables static clk: imx8mq: Add VIDEO2_PLL clock clk: imx8mn: Use common 1443X/1416X PLL clock structure clk: imx8mm: Move 1443X/1416X PLL clock structure to common place clk: imx: pll14xx: Fix quick switch of S/K parameter
2019-11-04clk: imx: imx8mq: fix sys3_pll_out_selsPeng Fan1-2/+2
It is not correct that sys3_pll_out use sys2_pll1_ref_sel as parent. According to the current imx_clk_sccg_pll design, it uses both bypass1/2, however set bypass2 as 1 is not correct, because it will make sys[x]_pll_out use wrong parent and might access wrong registers. So correct bypass2 to 0 and fix sys3_pll_out_sels. Fixes: e9dda4af685f ("clk: imx: Refactor entire sccg pll clk") Signed-off-by: Peng Fan <[email protected]> Signed-off-by: Shawn Guo <[email protected]>
2019-10-28clk: imx7ulp: do not export out IMX7ULP_CLK_MIPI_PLL clockFancy Fang1-2/+1
The mipi pll clock comes from the MIPI PHY PLL output, so it should not be a fixed clock. MIPI PHY PLL is in the MIPI DSI space, and it is used as the bit clock for transferring the pixel data out and its output clock is configured according to the display mode. So it should be used only for MIPI DSI and not be exported out for other usages. Signed-off-by: Fancy Fang <[email protected]> Signed-off-by: Shawn Guo <[email protected]>
2019-10-28clk: imx8m: Use SYS_PLL1_800M as intermediate parent of CLK_ARMLeonard Crestez2-2/+2
During cpu frequency switching the main "CLK_ARM" is reparented to an intermediate "step" clock. On imx8mm and imx8mn the 24M oscillator is used for this purpose but it is extremely slow, increasing wakeup latencies to the point that i2c transactions can timeout and system becomes unresponsive. Fix by switching the "step" clk to SYS_PLL1_800M, matching the behavior of imx8m cpufreq drivers in imx vendor tree. This bug was not immediately apparent because upstream arm64 defconfig uses the "performance" governor by default so no cpufreq transitions happen. Fixes: ba5625c3e272 ("clk: imx: Add clock driver support for imx8mm") Fixes: 96d6392b54db ("clk: imx: Add support for i.MX8MN clock driver") Cc: [email protected] Signed-off-by: Leonard Crestez <[email protected]> Link: https://lkml.kernel.org/r/f5d2b9c53f1ed5ccb1dd3c6624f56759d92e1689.1571771777.git.leonard.crestez@nxp.com Acked-by: Shawn Guo <[email protected]> Signed-off-by: Stephen Boyd <[email protected]>
2019-10-28clk: imx: imx6ul: use imx_obtain_fixed_clk_hw to simplify codePeng Fan1-4/+4
imx_obtain_fixed_clk_hw could be used to simplify code to replace __clk_get_hw(of_clk_get_by_name(node, "name")) Signed-off-by: Peng Fan <[email protected]> Signed-off-by: Shawn Guo <[email protected]>
2019-10-28clk: imx: imx6sx: use imx_obtain_fixed_clk_hw to simplify codePeng Fan1-6/+6
imx_obtain_fixed_clk_hw could be used to simplify code to replace __clk_get_hw(of_clk_get_by_name(node, "name")) Signed-off-by: Peng Fan <[email protected]> Signed-off-by: Shawn Guo <[email protected]>
2019-10-28clk: imx: imx6sll: use imx_obtain_fixed_clk_hw to simplify codePeng Fan1-4/+4
imx_obtain_fixed_clk_hw could be used to simplify code to replace __clk_get_hw(of_clk_get_by_name(node, "name")) Signed-off-by: Peng Fan <[email protected]> Signed-off-by: Shawn Guo <[email protected]>
2019-10-28clk: imx: imx7d: use imx_obtain_fixed_clk_hw to simplify codePeng Fan1-2/+2
imx_obtain_fixed_clk_hw could be used to simplify code to replace __clk_get_hw(of_clk_get_by_name(node, "name")) Signed-off-by: Peng Fan <[email protected]> Signed-off-by: Shawn Guo <[email protected]>
2019-10-26clk: imx7ulp: Correct DDR clock mux optionsAnson Huang1-2/+2
In the latest reference manual Rev.0,06/2019, the DDR clock mux is extended to 2 bits, and the clock options are also changed, correct them accordingly. Fixes: b1260067ac3d ("clk: imx: add imx7ulp clk driver") Signed-off-by: Anson Huang <[email protected]> Reviewed-by: Fabio Estevam <[email protected]> Signed-off-by: Shawn Guo <[email protected]>
2019-10-26clk: imx7ulp: Correct system clock source option #7Anson Huang1-1/+1
In the latest reference manual Rev.0,06/2019, the SCS's option #7 is no longer from upll, it is reserved, update clock driver accordingly. Fixes: b1260067ac3d ("clk: imx: add imx7ulp clk driver") Signed-off-by: Anson Huang <[email protected]> Reviewed-by: Fabio Estevam <[email protected]> Signed-off-by: Shawn Guo <[email protected]>
2019-10-25clk: imx: imx8mq: mark sys1/2_pll as fixed clockPeng Fan1-6/+2
According Architecture definition guide, SYS1_PLL is fixed at 800MHz, SYS2_PLL is fixed at 1000MHz, so let's use imx_clk_fixed to register the clocks and drop code that could change the rate. Reviewed-by: Abel Vesa <[email protected]> Signed-off-by: Peng Fan <[email protected]> Signed-off-by: Shawn Guo <[email protected]>
2019-10-25clk: imx: imx8mn: mark sys_pll1/2 as fixed clockPeng Fan1-26/+20
According Architecture definition guide, SYS_PLL1 is fixed at 800MHz, SYS_PLL2 is fixed at 1000MHz, so let's use imx_clk_fixed to register the clocks and drop code that could change the rate. Reviewed-by: Abel Vesa <[email protected]> Signed-off-by: Peng Fan <[email protected]> Signed-off-by: Shawn Guo <[email protected]>
2019-10-25clk: imx: imx8mm: mark sys_pll1/2 as fixed clockPeng Fan1-26/+20
According Architecture definition guide, SYS_PLL1 is fixed at 800MHz, SYS_PLL2 is fixed at 1000MHz, so let's use imx_clk_fixed to register the clocks and drop code that could change the rate. Reviewed-by: Abel Vesa <[email protected]> Signed-off-by: Peng Fan <[email protected]> Signed-off-by: Shawn Guo <[email protected]>
2019-10-25clk: imx8mn: Define gates for pll1/2 fixed dividersLeonard Crestez1-19/+38
On imx8mn there are 9 fixed-factor dividers for SYS_PLL1 and SYS_PLL2 each with their own gate. Only one of these gates (the one "dividing" by one) is currently defined and it's incorrectly set as the parent of all the fixed-factor dividers. Add the other 8 gates to the clock tree between sys_pll1/2_bypass and the fixed dividers. Signed-off-by: Leonard Crestez <[email protected]> Reviewed-by: Abel Vesa <[email protected]> Signed-off-by: Shawn Guo <[email protected]>
2019-10-25clk: imx8mm: Define gates for pll1/2 fixed dividersLeonard Crestez1-19/+38
On imx8mm there are 9 fixed-factor dividers for SYS_PLL1 and SYS_PLL2 each with their own gate. Only one of these gates (the one "dividing" by one) is currently defined and it's incorrectly set as the parent of all the fixed-factor dividers. Add the other 8 gates to the clock tree between sys_pll1/2_bypass and the fixed dividers. Signed-off-by: Leonard Crestez <[email protected]> Reviewed-by: Abel Vesa <[email protected]> Signed-off-by: Shawn Guo <[email protected]>
2019-10-25clk: imx8mq: Define gates for pll1/2 fixed dividersLeonard Crestez1-20/+41
On imx8mq there are 9 fixed-factor dividers for SYS_PLL1 and SYS_PLL2 each with their own gate but these gates are not currently defined in the clock tree. Add them between sys1/2_pll_out and the fixed dividers. Signed-off-by: Leonard Crestez <[email protected]> Reviewed-by: Abel Vesa <[email protected]> Signed-off-by: Shawn Guo <[email protected]>
2019-10-16clk: imx: imx8mn: drop unused pll enumPeng Fan1-14/+0
The PLL enum definition is not used, so drop it. Signed-off-by: Peng Fan <[email protected]> Link: https://lkml.kernel.org/r/[email protected] Signed-off-by: Stephen Boyd <[email protected]>
2019-10-14clk: imx: clk-pll14xx: Make two variables staticYueHaibing1-2/+2
Fix sparse warnings: drivers/clk/imx/clk-pll14xx.c:44:37: warning: symbol 'imx_pll1416x_tbl' was not declared. Should it be static? drivers/clk/imx/clk-pll14xx.c:57:37: warning: symbol 'imx_pll1443x_tbl' was not declared. Should it be static? Reported-by: Hulk Robot <[email protected]> Signed-off-by: YueHaibing <[email protected]> Reviewed-by: Anson Huang <[email protected]> Signed-off-by: Shawn Guo <[email protected]>
2019-10-14clk: imx8mq: Add VIDEO2_PLL clockLaurentiu Palcu1-0/+4
This clock is needed by DCSS when high resolutions are used. Signed-off-by: Laurentiu Palcu <[email protected]> CC: Abel Vesa <[email protected]> Signed-off-by: Shawn Guo <[email protected]>
2019-10-06clk: imx8mn: Use common 1443X/1416X PLL clock structureAnson Huang2-79/+12
Use common 1413X/1416X PLL clock structure to save a lot of duplicated code on i.MX8MN clock driver. Signed-off-by: Anson Huang <[email protected]> Reviewed-by: Leonard Crestez <[email protected]> Signed-off-by: Shawn Guo <[email protected]>
2019-10-06clk: imx8mm: Move 1443X/1416X PLL clock structure to common placeAnson Huang3-77/+43
Many i.MX8M SoCs use same 1443X/1416X PLL, such as i.MX8MM, i.MX8MN and later i.MX8M SoCs, moving these PLL definitions to pll14xx driver can save a lot of duplicated code on each platform. Meanwhile, no need to define PLL clock structure for every module which uses same type of PLL, e.g., audio/video/dram use 1443X PLL, arm/gpu/vpu/sys use 1416X PLL, define 2 PLL clock structure for each group is enough. Signed-off-by: Anson Huang <[email protected]> Reviewed-by: Leonard Crestez <[email protected]> Signed-off-by: Shawn Guo <[email protected]>
2019-10-06clk: imx: pll14xx: Fix quick switch of S/K parameterLeonard Crestez1-32/+8
The PLL14xx on imx8m can change the S and K parameter without requiring a reset and relock of the whole PLL. Fix clk_pll144xx_mp_change register reading and use it for pll1443 as well since no reset+relock is required on K changes either. Signed-off-by: Leonard Crestez <[email protected]> Fixes: 8646d4dcc7fb ("clk: imx: Add PLLs driver for imx8mm soc") Signed-off-by: Shawn Guo <[email protected]>
2019-09-17clk: imx: imx8mn: fix pll mux bitPeng Fan1-22/+10
pll BYPASS bit should be kept inside pll driver for glitchless freq setting following spec. If exposing the bit, that means pll driver and clk driver has two paths to touch this bit, which is wrong. So use EXT_BYPASS bit here. And drop uneeded set parent, because EXT_BYPASS default is 0. Suggested-by: Jacky Bai <[email protected]> Reviewed-by: Leonard Crestez <[email protected]> Signed-off-by: Peng Fan <[email protected]> Link: https://lkml.kernel.org/r/[email protected] Signed-off-by: Stephen Boyd <[email protected]>
2019-09-17clk: imx: imx8mm: fix pll mux bitPeng Fan1-22/+10
pll BYPASS bit should be kept inside pll driver for glitchless freq setting following spec. If exposing the bit, that means pll driver and clk driver has two paths to touch this bit, which is wrong. So use EXT_BYPASS bit here. And drop uneeded set parent, because EXT_BYPASS default is 0. Fixes: ba5625c3e272 ("clk: imx: Add clock driver support for imx8mm") Suggested-by: Jacky Bai <[email protected]> Reviewed-by: Leonard Crestez <[email protected]> Signed-off-by: Peng Fan <[email protected]> Link: https://lkml.kernel.org/r/[email protected] Signed-off-by: Stephen Boyd <[email protected]>
2019-09-17clk: imx: clk-pll14xx: unbypass PLL by defaultPeng Fan1-0/+5
When registering the PLL, unbypass the PLL. The PLL has two bypass control bit, BYPASS and EXT_BYPASS. we will expose EXT_BYPASS to clk driver for mux usage, and keep BYPASS inside pll14xx usage. The PLL has a restriction that when M/P change, need to RESET/BYPASS pll to avoid glitch, so we could not expose BYPASS. To make it easy for clk driver usage, unbypass PLL which does not hurt current function. Fixes: 8646d4dcc7fb ("clk: imx: Add PLLs driver for imx8mm soc") Reviewed-by: Leonard Crestez <[email protected]> Signed-off-by: Peng Fan <[email protected]> Link: https://lkml.kernel.org/r/[email protected] Signed-off-by: Stephen Boyd <[email protected]>
2019-09-17clk: imx: pll14xx: avoid glitch when set ratePeng Fan1-1/+21
According to PLL1443XA and PLL1416X spec, "When BYPASS is 0 and RESETB is changed from 0 to 1, FOUT starts to output unstable clock until lock time passes. PLL1416X/PLL1443XA may generate a glitch at FOUT." So set BYPASS when RESETB is changed from 0 to 1 to avoid glitch. In the end of set rate, BYPASS will be cleared. When prepare clock, also need to take care to avoid glitch. So we also follow Spec to set BYPASS before RESETB changed from 0 to 1. And add a check if the RESETB is already 0, directly return 0; Fixes: 8646d4dcc7fb ("clk: imx: Add PLLs driver for imx8mm soc") Reviewed-by: Leonard Crestez <[email protected]> Signed-off-by: Peng Fan <[email protected]> Link: https://lkml.kernel.org/r/[email protected] Signed-off-by: Stephen Boyd <[email protected]>
2019-08-24clk: imx: imx8mn: fix audio pll settingPeng Fan1-2/+2
The AUDIO PLL max support 650M, so the original clk settings violate spec. This patch makes the output 786432000 -> 393216000, and 722534400 -> 361267200 to aligned with NXP vendor kernel without any impact on audio functionality and go within 650MHz PLL limit. Signed-off-by: Peng Fan <[email protected]> Reviewed-by: Shengjiu Wang <[email protected]> Signed-off-by: Shawn Guo <[email protected]>
2019-08-19clk: imx8mn: Add necessary frequency support for ARM PLL tableAnson Huang1-0/+2
i.MX8MN supports CPU running at 1.5GHz/1.4GHz/1.2GHz, add missing frequency for ARM PLL table. Signed-off-by: Anson Huang <[email protected]> Signed-off-by: Shawn Guo <[email protected]>
2019-08-19clk: imx8mn: Add missing rate_count assignment for each PLL structureAnson Huang1-0/+7
Add .rate_count assignment which is necessary for searching required PLL rate from the each PLL table. Signed-off-by: Anson Huang <[email protected]> Signed-off-by: Shawn Guo <[email protected]>
2019-08-19clk: imx8mn: fix int pll clk gatePeng Fan1-6/+6
To Frac pll, the gate shift is 13, however to Int PLL the gate shift is 11. Signed-off-by: Peng Fan <[email protected]> Reviewed-by: Jacky Bai <[email protected]> Signed-off-by: Shawn Guo <[email protected]>
2019-08-19clk: imx8mn: Add GIC clockLeonard Crestez1-0/+5
This is enabled by default but if it's not explicitly defined and marked as critical then its parent might get turned off. Signed-off-by: Leonard Crestez <[email protected]> Signed-off-by: Shawn Guo <[email protected]>
2019-08-19clk: imx8mn: Fix incorrect parentsLeonard Crestez1-7/+7
* Replace to audio_pll2_clk with audio_pll2_out * Replace sys3_pll2_out with sys_pll3_out * Replace sys1_pll_40m with sys_pll1_40m * qspi parent[2] is sys_pll2_333m not sys_pll1_800m Fixes: 96d6392b54db ("clk: imx: Add support for i.MX8MN clock driver") Signed-off-by: Leonard Crestez <[email protected]> Signed-off-by: Shawn Guo <[email protected]>
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