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path: root/drivers/clk/imx/clk-divider-gate.c
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2019-12-11clk: imx: Rename the imx_clk_divider_gate to imply it's clk_hw basedAbel Vesa1-1/+1
Renaming the imx_clk_divider_gate register function to imx_clk_hw_divider_gate to be more obvious it is clk_hw based. Signed-off-by: Abel Vesa <[email protected]> Reviewed-by: Peng Fan <[email protected]> Signed-off-by: Shawn Guo <[email protected]>
2019-12-09clk: imx: clk-divider-gate: drop redundant initializationPeng Fan1-4/+4
There is no need to initialize flags as 0. Signed-off-by: Peng Fan <[email protected]> Reviewed-by: Abel Vesa <[email protected]> Signed-off-by: Shawn Guo <[email protected]>
2019-12-09clk: imx: clk-divider-gate: fix a typo in commentPeng Fan1-1/+1
Fix a typo in comment: resue -> reuse. Signed-off-by: Peng Fan <[email protected]> Signed-off-by: Shawn Guo <[email protected]>
2019-04-23clk: core: replace clk_{readl,writel} with {readl,writel}Jonas Gorski1-10/+10
Now that clk_{readl,writel} is just an alias for {readl,writel}, we can switch all users of clk_* to use the accessors directly and remove the helpers. Signed-off-by: Jonas Gorski <[email protected]> [[email protected]: Also convert renesas file so that this can be compile independently] Signed-off-by: Stephen Boyd <[email protected]>
2018-12-03clk: imx: add gatable clock divider supportA.s. Dong1-0/+221
For dividers with zero indicating clock is disabled, instead of giving a warning each time like "clkx: Zero divisor and CLK_DIVIDER_ALLOW_ZERO not set" in exist code, we'd like to introduce enable/disable function for it. e.g. 000b - Clock disabled 001b - Divide by 1 010b - Divide by 2 ... Set rate when the clk is disabled will cache the rate request and only when the clk is enabled will the driver actually program the hardware to have the requested divider value. Similarly, when the clk is disabled we'll write a 0 there, but when the clk is enabled we'll restore whatever rate (divider) was chosen last. It does mean that recalc rate will be sort of odd, because when the clk is off it will return 0, and when the clk is on it will return the right rate. So to make things work, we'll need to return the cached rate in recalc rate when the clk is off and read the hardware when the clk is on. NOTE for the default off divider, the recalc rate will still return 0 as there's still no proper preset rate. Enable such divider will give user a reminder error message. Cc: Stephen Boyd <[email protected]> Cc: Michael Turquette <[email protected]> Cc: Shawn Guo <[email protected]> Signed-off-by: Dong Aisheng <[email protected]> [[email protected]: Include clk.h for sparse warnings] Signed-off-by: Stephen Boyd <[email protected]>