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path: root/drivers/clk/at91/at91rm9200.c
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2022-03-08clk: at91: clk-master: remove dead codeClaudiu Beznea1-2/+1
Commit facb87ad7560 ("clk: at91: sama7g5: remove prescaler part of master clock") removed the master clock's prescaler from clock tree of SAMA7G5 as it has been discovered that there is a hardware bug when trying to change it at run-time (bug is described in description of commit facb87ad7560 ("clk: at91: sama7g5: remove prescaler part of master clock")). This was previously changed at CPUFreq driver request. Thus, with commit facb87ad7560 ("clk: at91: sama7g5: remove prescaler part of master clock") there is no need of code that handles run-time changes of master clock's prescaler, thus remove this code. Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com> Signed-off-by: Nicolas Ferre <nicolas.ferre@microchip.com> Link: https://lore.kernel.org/r/20220203110202.18329-1-claudiu.beznea@microchip.com
2021-10-26clk: at91: clk-master: add notifier for dividerClaudiu Beznea1-1/+1
SAMA7G5 supports DVFS by changing cpuck. On SAMA7G5 mck0 shares the same parent with cpuck as seen in the following clock tree: +----------> cpuck | FRAC PLL ---> DIV PLL -+-> DIV ---> mck0 mck0 could go b/w 32KHz and 200MHz on SAMA7G5. To avoid mck0 overclocking while changing FRAC PLL or DIV PLL the commit implements a notifier for mck0 which applies a safe divider to register (maximum value of the divider which is 5) on PRE_RATE_CHANGE events (such that changes on PLL to not overclock mck0) and sets the maximum allowed rate on POST_RATE_CHANGE events. Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com> Link: https://lore.kernel.org/r/20211011112719.3951784-13-claudiu.beznea@microchip.com Acked-by: Nicolas Ferre <nicolas.ferre@microchip.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2021-02-09clk: at91: Fix the declaration of the clocksTudor Ambarus1-2/+1
These are all "early clocks" that require initialization just at of_clk_init() time. Use CLK_OF_DECLARE() to declare them. This also fixes a problem that was spotted when fw_devlink was set to 'on' by default: the boards failed to boot. The reason is that CLK_OF_DECLARE_DRIVER() clears the OF_POPULATED and causes the consumers of the clock to be postponed by fw_devlink until the second initialization routine of the clock has been completed. One of the consumers of the clock is the timer, which is used as a clocksource, and needs the clock initialized early. Postponing the timers caused the fail at boot. Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com> Link: https://lore.kernel.org/r/20210203154332.470587-1-tudor.ambarus@microchip.com Acked-by: Saravana Kannan <saravanak@google.com> Tested-by: Eugen Hristev <eugen.hristev@microchip.com> Acked-by: Nicolas Ferre <nicolas.ferre@microchip.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2020-12-19clk: at91: clk-master: re-factor master clockClaudiu Beznea1-4/+17
Re-factor master clock driver by splitting it into 2 clocks: prescaller and divider clocks. Based on registered clock flags the prescaler's rate could be changed at runtime. This is necessary for platforms supporting DVFS (e.g. SAMA7G5) where master clock could be changed at run-time. Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com> Link: https://lore.kernel.org/r/1605800597-16720-11-git-send-email-claudiu.beznea@microchip.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2020-07-24clk: at91: clk-programmable: add mux_table optionClaudiu Beznea1-1/+2
Add mux table option. This is necessary for IP versions that has gaps in the range of available clock sources (e.g. SAMA7G5). Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com> Link: https://lore.kernel.org/r/1595403506-8209-15-git-send-email-claudiu.beznea@microchip.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2020-05-26clk: at91: allow setting all PMC clock parents via DTMichał Mirosław1-1/+5
We need to have clocks accessible via phandle to select them as peripheral clock parent using assigned-clock-parents in DT. Add support for PLLACK/PLLBCK/AUDIOPLLCK clocks where available. Signed-off-by: Michał Mirosław <mirq-linux@rere.qmqm.pl> Acked-by: Alexandre Belloni <alexandre.belloni@bootlin.com> Link: https://lkml.kernel.org/r/fa39cc10dab8341ea4bc2b7152be9217b2cd34a5.1588630999.git.mirq-linux@rere.qmqm.pl Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2020-05-26clk: at91: allow setting PCKx parent via DTMichał Mirosław1-1/+3
This exposes PROGx clocks for use in assigned-clocks DeviceTree property for selecting PCKx parent clock. Signed-off-by: Michał Mirosław <mirq-linux@rere.qmqm.pl> Link: https://lkml.kernel.org/r/0054532c00163ddf405dad658b32f0d7d97fcc8e.1588630999.git.mirq-linux@rere.qmqm.pl Acked-by: Alexandre Belloni <alexandre.belloni@bootlin.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2020-05-26clk: at91: optimize pmc data allocationMichał Mirosław1-1/+1
Alloc whole data structure in one block. This makes the code shorter, more efficient and easier to extend in following patch. Signed-off-by: Michał Mirosław <mirq-linux@rere.qmqm.pl> Link: https://lkml.kernel.org/r/fc6f6d67b8cee0beace4a9d9cca7431e5efa769d.1588630999.git.mirq-linux@rere.qmqm.pl Acked-by: Alexandre Belloni <alexandre.belloni@bootlin.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2020-03-20clk: at91: add at91rm9200 pmc driverAlexandre Belloni1-0/+199
Add a driver for the PMC clocks of the at91rm9200. Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com> Link: https://lkml.kernel.org/r/20200214145934.53648-1-alexandre.belloni@bootlin.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
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